VirtualBox

Ignore:
Timestamp:
Nov 11, 2022 10:54:35 PM (2 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
154540
Message:

ValKit/bs3-cpu-basic-2: Added some basic indirect far call tests. bugref:9898

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.mac

    r97510 r97516  
    6767%endif
    6868
     69;;
     70; Macro for generating far jmp instruction w/o nasm adding REX.W prefixes.
     71;
     72; @param 1      The label of the memory pointer.
     73; @param 2      Set to 0 for no prefix, 1 for REX.W prefix.
    6974%ifndef BS3_CPUBAS2_JMP_FAR_MEM_LABEL_DEFINED
    7075%define BS3_CPUBAS2_JMP_FAR_MEM_LABEL_DEFINED
    … …  
    8489%endmacro
    8590%endif ; BS3_CPUBAS2_JMP_FAR_MEM_LABEL_DEFINED
     91
     92;;
     93; Macro for generating far call instruction w/o nasm adding REX.W prefixes.
     94;
     95; @param 1      The label of the memory pointer.
     96; @param 2      Set to 0 for no prefix, 1 for REX.W prefix.
     97%ifndef BS3_CPUBAS2_CALL_FAR_MEM_LABEL_DEFINED
     98%define BS3_CPUBAS2_CALL_FAR_MEM_LABEL_DEFINED
     99%macro BS3_CPUBAS2_CALL_FAR_MEM_LABEL 2
     100 %if TMPL_BITS != 64
     101        call far [BS3_CPUBAS2_REF_LABEL_VIA_CS(%1)]
     102 %elif TMPL_BITS == 64
     103  %if %2 != 0
     104        db      048h                        ; REX.W
     105  %endif
     106        db      0ffh, 01ch, 025h            ; call far [mem]
     107        dd      %1 wrt FLAT
     108 %else
     109  %error TMPL_BITS
     110 %endif
     111%endmacro
     112%endif ; BS3_CPUBAS2_CALL_FAR_MEM_LABEL_DEFINED
    86113
    87114
    … …  
    12661293 %endif
    12671294
    1268 ; The first 64-bit versions follow AMD behaviour
    1269 
     1295;;
     1296; Since AMD and Intel treat REX.W differently, we need two versions of the
     1297; test functions here and use a macro to accomplish that.
    12701298%ifndef jmpf_macro_defined
    12711299%define jmpf_macro_defined
    … …  
    13631391        BS3_CPUBAS2_JMP_FAR_MEM_LABEL   .fpfn, 0
    13641392.fpfn:
    1365   ;%if TMPL_BITS != 64 || %2 == 0
    1366         dw      .again wrt CGROUP16
    1367   ;%else
    1368   ;      dd      .again wrt CGROUP16, 0
    1369   ;%endif
     1393        dw      .again wrt CGROUP16
    13701394        dw      BS3_SEL_R0_CS16
    13711395        times 4 int3
    … …  
    14471471
    14481472
     1473;*********************************************************************************************************************************
     1474;*  INDIRECT FAR CALL                                                                                                            *
     1475;*********************************************************************************************************************************
     1476
     1477 %if TMPL_BITS == 16
     1478BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_rm__ud2
     1479BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_rm__ud2, BS3_PBC_NEAR
     1480        call    far [BS3_CPUBAS2_REF_LABEL_VIA_CS(.fpfn)]
     1481        int3
     1482.fpfn:
     1483        dw      .again wrt CGROUP16
     1484        dw      BS3_SEL_TEXT16
     1485.post_jmp:
     1486        times 2 int3
     1487.again: ud2
     1488        int3
     1489        jmp     .again
     1490BS3_PROC_END_CMN   bs3CpuBasic2_callf_mem_rm__ud2
     1491 %endif
     1492
     1493
     1494;;
     1495; Since AMD and Intel treat REX.W differently, we need two versions of the
     1496; test functions here and use a macro to accomplish that.
     1497%ifndef callf_macro_defined
     1498%define callf_macro_defined
     1499%macro callf_macro 2
     1500
     1501BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_same_r0__ud2 %+ %1
     1502BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_same_r0__ud2 %+ %1, BS3_PBC_NEAR
     1503        call    far [BS3_CPUBAS2_REF_LABEL_VIA_CS(.fpfn)]
     1504.fpfn:
     1505 %if TMPL_BITS == 16
     1506        dw      .again wrt CGROUP16
     1507        dw      BS3_SEL_R0_CS16
     1508 %elif TMPL_BITS == 32
     1509        dd      .again wrt FLAT
     1510        dw      BS3_SEL_R0_CS32
     1511 %else
     1512        dd      .again wrt FLAT
     1513  %if %2 != 0
     1514        dd      0fffff000h
     1515  %endif
     1516        dw      BS3_SEL_R0_CS64
     1517 %endif
     1518.post_call:
     1519        times 7 int3
     1520.again: ud2
     1521        int3
     1522        jmp     .again
     1523BS3_PROC_END_CMN   bs3CpuBasic2_callf_mem_same_r0__ud2 %+ %1
     1524
     1525BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_same_r1__ud2 %+ %1
     1526BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_same_r1__ud2 %+ %1, BS3_PBC_NEAR
     1527        call    far [BS3_CPUBAS2_REF_LABEL_VIA_CS(.fpfn)]
     1528.fpfn:
     1529 %if TMPL_BITS == 16
     1530        dw      .again wrt CGROUP16
     1531        dw      BS3_SEL_R1_CS16 | 1
     1532 %elif TMPL_BITS == 32
     1533        dd      .again wrt FLAT
     1534        dw      BS3_SEL_R1_CS32 | 1
     1535 %else
     1536        dd      .again wrt FLAT
     1537  %if %2 != 0
     1538        dd      0fffff000h
     1539  %endif
     1540        dw      BS3_SEL_R1_CS64 | 1
     1541 %endif
     1542.again: ud2
     1543        jmp     .again
     1544BS3_PROC_END_CMN   bs3CpuBasic2_callf_mem_same_r1__ud2 %+ %1
     1545
     1546BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_same_r2__ud2 %+ %1
     1547BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_same_r2__ud2 %+ %1, BS3_PBC_NEAR
     1548        BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, 0
     1549.fpfn:
     1550 %if TMPL_BITS == 16
     1551        dw      .again wrt CGROUP16
     1552        dw      BS3_SEL_R2_CS16 | 2
     1553 %elif TMPL_BITS == 32
     1554        dd      .again wrt FLAT
     1555        dw      BS3_SEL_R2_CS32 | 2
     1556 %else
     1557        dd      .again wrt FLAT
     1558        dw      BS3_SEL_R2_CS64 | 2
     1559 %endif
     1560.again: ud2
     1561        jmp     .again
     1562BS3_PROC_END_CMN   bs3CpuBasic2_callf_mem_same_r2__ud2 %+ %1
     1563
     1564BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_same_r3__ud2 %+ %1
     1565BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_same_r3__ud2 %+ %1, BS3_PBC_NEAR
     1566        BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, 1
     1567.fpfn:
     1568 %if TMPL_BITS == 16
     1569        dw      .again wrt CGROUP16
     1570        dw      BS3_SEL_R3_CS16 | 3
     1571 %elif TMPL_BITS == 32
     1572        dd      .again wrt FLAT
     1573        dw      BS3_SEL_R3_CS32 | 3
     1574 %else
     1575        dd      .again wrt FLAT
     1576  %if %2 != 0
     1577        dd      0fffff000h
     1578  %endif
     1579        dw      BS3_SEL_R3_CS64 | 3
     1580 %endif
     1581.again: ud2
     1582        jmp     .again
     1583BS3_PROC_END_CMN   bs3CpuBasic2_callf_mem_same_r3__ud2 %+ %1
     1584
     1585BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_r0_cs16__ud2 %+ %1
     1586BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_r0_cs16__ud2 %+ %1, BS3_PBC_NEAR
     1587  %if TMPL_BITS != 16
     1588        db      66h
     1589  %endif
     1590        BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, 0
     1591.fpfn:
     1592        dw      .again wrt CGROUP16
     1593        dw      BS3_SEL_R0_CS16
     1594        times 4 int3
     1595.again: ud2
     1596        jmp     .again
     1597BS3_PROC_END_CMN   bs3CpuBasic2_callf_mem_r0_cs16__ud2 %+ %1
     1598
     1599BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_r0_cs32__ud2 %+ %1
     1600BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_r0_cs32__ud2 %+ %1, BS3_PBC_NEAR
     1601  %if TMPL_BITS == 16
     1602        db      66h
     1603  %endif
     1604        BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, 0
     1605.fpfn:
     1606        dd      .again wrt FLAT
     1607        dw      BS3_SEL_R0_CS32
     1608        times 4 int3
     1609.again: ud2
     1610        jmp     .again
     1611BS3_PROC_END_CMN   bs3CpuBasic2_callf_mem_r0_cs32__ud2 %+ %1
     1612
     1613; Do a call to BS3_SEL_R0_CS64.  Except for when we're in long mode, this will
     1614; result in a 16-bit CS with zero base and 4G limit.
     1615BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_r0_cs64__ud2 %+ %1
     1616BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_r0_cs64__ud2 %+ %1, BS3_PBC_NEAR
     1617 %if TMPL_BITS == 16
     1618        db      066h
     1619 %endif
     1620        call    far [BS3_CPUBAS2_REF_LABEL_VIA_CS(.fpfn)]
     1621.fpfn:
     1622        dd      .call_target wrt FLAT
     1623 %if TMPL_BITS == 64 && %2 != 0
     1624        dd      0fffff000h
     1625 %endif
     1626        dw      BS3_SEL_R0_CS64
     1627        times 8 int3
     1628.call_target:
     1629 %if TMPL_BITS != 64
     1630        salc                            ; #UD in 64-bit mode
     1631 %endif
     1632.again: ud2
     1633        jmp     .again
     1634BS3_PROC_END_CMN   bs3CpuBasic2_callf_mem_r0_cs64__ud2 %+ %1
     1635
     1636; Variation of the previous with a CS16 copy that has the L bit set, emulating
     1637; pre-AMD64 software using the L bit for other stuff.  (Don't run _c16/32 in
     1638; long mode w/o copying the 3 bytes to the 0xxxxh memory range.)
     1639; The _c64 version will test that the base is ignored.
     1640BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_r0_cs16l__ud2 %+ %1
     1641BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_r0_cs16l__ud2 %+ %1, BS3_PBC_NEAR
     1642 %if TMPL_BITS == 32
     1643        db      066h
     1644 %endif
     1645        BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, 0
     1646.fpfn:
     1647 %if TMPL_BITS != 64
     1648        dw      .call_target wrt CGROUP16
     1649 %else
     1650        dd      .call_target wrt FLAT
     1651 %endif
     1652        dw      BS3_SEL_SPARE_00        ; ASSUMES this is set up as CGROUP16 but with L=1.
     1653        times 3 int3
     1654.call_target:
     1655 %if TMPL_BITS != 64
     1656        salc                            ; #UD in 64-bit mode
     1657 %endif
     1658.again: ud2
     1659        jmp     .again
     1660BS3_PROC_END_CMN   bs3CpuBasic2_callf_mem_r0_cs16l__ud2 %+ %1
     1661
     1662%endmacro ; callf_macro
     1663%endif
     1664
     1665; Instantiate the above code
     1666callf_macro , 0
     1667 %if TMPL_BITS == 64
     1668callf_macro _intel, 1
     1669 %endif
     1670
     1671
    14491672%endif ; BS3_INSTANTIATING_CMN
    14501673

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-x0.c

    r97510 r97516  
    41134113FNBS3FAR  bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2_intel_c64;
    41144114
     4115FNBS3FAR  bs3CpuBasic2_callf_mem_rm__ud2_c16;
     4116PROTO_ALL(bs3CpuBasic2_callf_mem_same_r0__ud2);
     4117PROTO_ALL(bs3CpuBasic2_callf_mem_same_r1__ud2);
     4118PROTO_ALL(bs3CpuBasic2_callf_mem_same_r2__ud2);
     4119PROTO_ALL(bs3CpuBasic2_callf_mem_same_r3__ud2);
     4120PROTO_ALL(bs3CpuBasic2_callf_mem_r0_cs16__ud2);
     4121PROTO_ALL(bs3CpuBasic2_callf_mem_r0_cs32__ud2);
     4122PROTO_ALL(bs3CpuBasic2_callf_mem_r0_cs64__ud2);
     4123PROTO_ALL(bs3CpuBasic2_callf_mem_r0_cs16l__ud2);
     4124
     4125FNBS3FAR  bs3CpuBasic2_callf_mem_same_r0__ud2_intel_c64;
     4126FNBS3FAR  bs3CpuBasic2_callf_mem_same_r1__ud2_intel_c64;
     4127FNBS3FAR  bs3CpuBasic2_callf_mem_same_r2__ud2_intel_c64;
     4128FNBS3FAR  bs3CpuBasic2_callf_mem_same_r3__ud2_intel_c64;
     4129FNBS3FAR  bs3CpuBasic2_callf_mem_r0_cs16__ud2_intel_c64;
     4130FNBS3FAR  bs3CpuBasic2_callf_mem_r0_cs32__ud2_intel_c64;
     4131FNBS3FAR  bs3CpuBasic2_callf_mem_r0_cs64__ud2_intel_c64;
     4132FNBS3FAR  bs3CpuBasic2_callf_mem_r0_cs16l__ud2_intel_c64;
     4133
    41154134#undef PROTO_ALL
    41164135
    … …  
    41984217            { false, false, BS3_SEL_R0_CS64,        64,  true, bs3CpuBasic2_jmpf_mem_r0_cs64__ud2_c16, },  /* 16-bit CS, except in LM. */
    41994218            { false, false, BS3_SEL_SPARE_00,       64, false, bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2_c16, }, /* 16-bit CS, except in LM. */
     4219
     4220            {  true,  true, BS3_SEL_TEXT16,         16, false, bs3CpuBasic2_callf_mem_rm__ud2_c16, },
     4221            { false,  true, BS3_SEL_R0_CS16,        16, false, bs3CpuBasic2_callf_mem_same_r0__ud2_c16, },
     4222            { false,  true, BS3_SEL_R1_CS16 | 1,    16, false, bs3CpuBasic2_callf_mem_same_r1__ud2_c16, },
     4223            { false,  true, BS3_SEL_R2_CS16 | 2,    16, false, bs3CpuBasic2_callf_mem_same_r2__ud2_c16, },
     4224            { false,  true, BS3_SEL_R3_CS16 | 3,    16, false, bs3CpuBasic2_callf_mem_same_r3__ud2_c16, },
     4225            { false,  true, BS3_SEL_R0_CS16,        16, false, bs3CpuBasic2_callf_mem_r0_cs16__ud2_c16, },
     4226            { false,  true, BS3_SEL_R0_CS32,        32,  true, bs3CpuBasic2_callf_mem_r0_cs32__ud2_c16, },
     4227            { false,  true, BS3_SEL_R0_CS64,        64,  true, bs3CpuBasic2_callf_mem_r0_cs64__ud2_c16, },  /* 16-bit CS, except in LM. */
     4228            { false,  true, BS3_SEL_SPARE_00,       64, false, bs3CpuBasic2_callf_mem_r0_cs16l__ud2_c16, }, /* 16-bit CS, except in LM. */
    42004229        };
    42014230        bool const fRmOrV86 = BS3_MODE_IS_RM_OR_V86(bMode);
    … …  
    43044333            { false, BS3_SEL_R0_CS64,        64, false, bs3CpuBasic2_jmpf_mem_r0_cs64__ud2_c32, },  /* 16-bit CS, except in LM. */
    43054334            { false, BS3_SEL_SPARE_00,       64,  true, bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2_c32, }, /* 16-bit CS, except in LM. */
     4335
     4336            {  true, BS3_SEL_R0_CS32,        32, false, bs3CpuBasic2_callf_mem_same_r0__ud2_c32, },
     4337            {  true, BS3_SEL_R1_CS32 | 1,    32, false, bs3CpuBasic2_callf_mem_same_r1__ud2_c32, },
     4338            {  true, BS3_SEL_R2_CS32 | 2,    32, false, bs3CpuBasic2_callf_mem_same_r2__ud2_c32, },
     4339            {  true, BS3_SEL_R3_CS32 | 3,    32, false, bs3CpuBasic2_callf_mem_same_r3__ud2_c32, },
     4340            {  true, BS3_SEL_R0_CS16,        16,  true, bs3CpuBasic2_callf_mem_r0_cs16__ud2_c32, },
     4341            {  true, BS3_SEL_R0_CS32,        32, false, bs3CpuBasic2_callf_mem_r0_cs32__ud2_c32, },
     4342            {  true, BS3_SEL_R0_CS64,        64, false, bs3CpuBasic2_callf_mem_r0_cs64__ud2_c32, },  /* 16-bit CS, except in LM. */
     4343            {  true, BS3_SEL_SPARE_00,       64,  true, bs3CpuBasic2_callf_mem_r0_cs16l__ud2_c32, }, /* 16-bit CS, except in LM. */
    43064344        };
    43074345
    … …  
    43794417            uint16_t    uDstSel;
    43804418            uint8_t     uDstBits;
    4381             bool        fOpSizePfx;
     4419            uint8_t     fOpSizePfx; /**< 0: none, 1: 066h, 2: REX.W, 3: 066h REX.W */
    43824420            int8_t      fFix64OpSize;
    43834421            FPFNBS3FAR  pfnTest;
    … …  
    43864424        {
    43874425            /* invalid opcodes: */
    4388             {  true, false, BS3_SEL_R0_CS32,        64, false,    -1, bs3CpuBasic2_jmpf_ptr_same_r0__ud2_c32, },
    4389             {  true, false, BS3_SEL_R1_CS32 | 1,    64, false,    -1, bs3CpuBasic2_jmpf_ptr_same_r1__ud2_c32, },
    4390             {  true, false, BS3_SEL_R2_CS32 | 2,    64, false,    -1, bs3CpuBasic2_jmpf_ptr_same_r2__ud2_c32, },
    4391             {  true, false, BS3_SEL_R3_CS32 | 3,    64, false,    -1, bs3CpuBasic2_jmpf_ptr_same_r3__ud2_c32, },
    4392             {  true, false, BS3_SEL_R0_CS16,        64, false,    -1, bs3CpuBasic2_jmpf_ptr_opsize_flipbit_r0__ud2_c32, },
    4393             {  true, false, BS3_SEL_R0_CS64,        64, false,    -1, bs3CpuBasic2_jmpf_ptr_r0_cs64__ud2_c32, },
    4394             {  true, false, BS3_SEL_SPARE_00,       64, false,    -1, bs3CpuBasic2_jmpf_ptr_r0_cs16l__ud2_c32, },
    4395 
    4396             {  true,  true, BS3_SEL_R0_CS32,        64, false,    -1, bs3CpuBasic2_callf_ptr_same_r0__ud2_c32, },
    4397             {  true,  true, BS3_SEL_R1_CS32 | 1,    64, false,    -1, bs3CpuBasic2_callf_ptr_same_r1__ud2_c32, },
    4398             {  true,  true, BS3_SEL_R2_CS32 | 2,    64, false,    -1, bs3CpuBasic2_callf_ptr_same_r2__ud2_c32, },
    4399             {  true,  true, BS3_SEL_R3_CS32 | 3,    64, false,    -1, bs3CpuBasic2_callf_ptr_same_r3__ud2_c32, },
    4400             {  true,  true, BS3_SEL_R0_CS16,        64, false,    -1, bs3CpuBasic2_callf_ptr_opsize_flipbit_r0__ud2_c32, },
    4401             {  true,  true, BS3_SEL_R0_CS64,        64, false,    -1, bs3CpuBasic2_callf_ptr_r0_cs64__ud2_c32, },
    4402             {  true,  true, BS3_SEL_SPARE_00,       64, false,    -1, bs3CpuBasic2_callf_ptr_r0_cs16l__ud2_c32, },
    4403 
    4404             { false, false, BS3_SEL_R0_CS64,        64, false, false, bs3CpuBasic2_jmpf_mem_same_r0__ud2_c64, },
    4405             { false, false, BS3_SEL_R1_CS64 | 1,    64, false, false, bs3CpuBasic2_jmpf_mem_same_r1__ud2_c64, },
    4406             { false, false, BS3_SEL_R2_CS64 | 2,    64, false, false, bs3CpuBasic2_jmpf_mem_same_r2__ud2_c64, },
    4407             { false, false, BS3_SEL_R3_CS64 | 3,    64, false, false, bs3CpuBasic2_jmpf_mem_same_r3__ud2_c64, },
    4408             { false, false, BS3_SEL_R0_CS16,        16,  true, false, bs3CpuBasic2_jmpf_mem_r0_cs16__ud2_c64, },
    4409             { false, false, BS3_SEL_R0_CS32,        32, false, false, bs3CpuBasic2_jmpf_mem_r0_cs32__ud2_c64, },
    4410             { false, false, BS3_SEL_R0_CS64,        64, false, false, bs3CpuBasic2_jmpf_mem_r0_cs64__ud2_c64, },  /* 16-bit CS, except in LM. */
    4411             { false, false, BS3_SEL_SPARE_00,       64,  true, false, bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2_c64, }, /* 16-bit CS, except in LM. */
    4412 
    4413             { false, false, BS3_SEL_R0_CS64,        64, false,  true, bs3CpuBasic2_jmpf_mem_same_r0__ud2_intel_c64, },
    4414             { false, false, BS3_SEL_R1_CS64 | 1,    64, false,  true, bs3CpuBasic2_jmpf_mem_same_r1__ud2_intel_c64, },
    4415             { false, false, BS3_SEL_R2_CS64 | 2,    64, false,  true, bs3CpuBasic2_jmpf_mem_same_r2__ud2_intel_c64, },
    4416             { false, false, BS3_SEL_R3_CS64 | 3,    64, false,  true, bs3CpuBasic2_jmpf_mem_same_r3__ud2_intel_c64, },
    4417             { false, false, BS3_SEL_R0_CS16,        16,  true,  true, bs3CpuBasic2_jmpf_mem_r0_cs16__ud2_intel_c64, },
    4418             { false, false, BS3_SEL_R0_CS32,        32, false,  true, bs3CpuBasic2_jmpf_mem_r0_cs32__ud2_intel_c64, },
    4419             { false, false, BS3_SEL_R0_CS64,        64, false,  true, bs3CpuBasic2_jmpf_mem_r0_cs64__ud2_intel_c64, },  /* 16-bit CS, except in LM. */
    4420             { false, false, BS3_SEL_SPARE_00,       64,  true,  true, bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2_intel_c64, }, /* 16-bit CS, except in LM. */
     4426            {  true, false, BS3_SEL_R0_CS32,        64, 0,    -1, bs3CpuBasic2_jmpf_ptr_same_r0__ud2_c32, },
     4427            {  true, false, BS3_SEL_R1_CS32 | 1,    64, 0,    -1, bs3CpuBasic2_jmpf_ptr_same_r1__ud2_c32, },
     4428            {  true, false, BS3_SEL_R2_CS32 | 2,    64, 0,    -1, bs3CpuBasic2_jmpf_ptr_same_r2__ud2_c32, },
     4429            {  true, false, BS3_SEL_R3_CS32 | 3,    64, 0,    -1, bs3CpuBasic2_jmpf_ptr_same_r3__ud2_c32, },
     4430            {  true, false, BS3_SEL_R0_CS16,        64, 0,    -1, bs3CpuBasic2_jmpf_ptr_opsize_flipbit_r0__ud2_c32, },
     4431            {  true, false, BS3_SEL_R0_CS64,        64, 0,    -1, bs3CpuBasic2_jmpf_ptr_r0_cs64__ud2_c32, },
     4432            {  true, false, BS3_SEL_SPARE_00,       64, 0,    -1, bs3CpuBasic2_jmpf_ptr_r0_cs16l__ud2_c32, },
     4433
     4434            {  true,  true, BS3_SEL_R0_CS32,        64, 0,    -1, bs3CpuBasic2_callf_ptr_same_r0__ud2_c32, },
     4435            {  true,  true, BS3_SEL_R1_CS32 | 1,    64, 0,    -1, bs3CpuBasic2_callf_ptr_same_r1__ud2_c32, },
     4436            {  true,  true, BS3_SEL_R2_CS32 | 2,    64, 0,    -1, bs3CpuBasic2_callf_ptr_same_r2__ud2_c32, },
     4437            {  true,  true, BS3_SEL_R3_CS32 | 3,    64, 0,    -1, bs3CpuBasic2_callf_ptr_same_r3__ud2_c32, },
     4438            {  true,  true, BS3_SEL_R0_CS16,        64, 0,    -1, bs3CpuBasic2_callf_ptr_opsize_flipbit_r0__ud2_c32, },
     4439            {  true,  true, BS3_SEL_R0_CS64,        64, 0,    -1, bs3CpuBasic2_callf_ptr_r0_cs64__ud2_c32, },
     4440            {  true,  true, BS3_SEL_SPARE_00,       64, 0,    -1, bs3CpuBasic2_callf_ptr_r0_cs16l__ud2_c32, },
     4441
     4442            { false, false, BS3_SEL_R0_CS64,        64, 0, false, bs3CpuBasic2_jmpf_mem_same_r0__ud2_c64, },
     4443            { false, false, BS3_SEL_R1_CS64 | 1,    64, 0, false, bs3CpuBasic2_jmpf_mem_same_r1__ud2_c64, },
     4444            { false, false, BS3_SEL_R2_CS64 | 2,    64, 0, false, bs3CpuBasic2_jmpf_mem_same_r2__ud2_c64, },
     4445            { false, false, BS3_SEL_R3_CS64 | 3,    64, 0, false, bs3CpuBasic2_jmpf_mem_same_r3__ud2_c64, },
     4446            { false, false, BS3_SEL_R0_CS16,        16, 1, false, bs3CpuBasic2_jmpf_mem_r0_cs16__ud2_c64, },
     4447            { false, false, BS3_SEL_R0_CS32,        32, 0, false, bs3CpuBasic2_jmpf_mem_r0_cs32__ud2_c64, },
     4448            { false, false, BS3_SEL_R0_CS64,        64, 0, false, bs3CpuBasic2_jmpf_mem_r0_cs64__ud2_c64, },  /* 16-bit CS, except in LM. */
     4449            { false, false, BS3_SEL_SPARE_00,       64, 0, false, bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2_c64, }, /* 16-bit CS, except in LM. */
     4450
     4451            { false, false, BS3_SEL_R0_CS64,        64, 2,  true, bs3CpuBasic2_jmpf_mem_same_r0__ud2_intel_c64, },
     4452            { false, false, BS3_SEL_R1_CS64 | 1,    64, 2,  true, bs3CpuBasic2_jmpf_mem_same_r1__ud2_intel_c64, },
     4453            { false, false, BS3_SEL_R2_CS64 | 2,    64, 0,  true, bs3CpuBasic2_jmpf_mem_same_r2__ud2_intel_c64, },
     4454            { false, false, BS3_SEL_R3_CS64 | 3,    64, 2,  true, bs3CpuBasic2_jmpf_mem_same_r3__ud2_intel_c64, },
     4455            { false, false, BS3_SEL_R0_CS16,        16, 1,  true, bs3CpuBasic2_jmpf_mem_r0_cs16__ud2_intel_c64, },
     4456            { false, false, BS3_SEL_R0_CS32,        32, 0,  true, bs3CpuBasic2_jmpf_mem_r0_cs32__ud2_intel_c64, },
     4457            { false, false, BS3_SEL_R0_CS64,        64, 2,  true, bs3CpuBasic2_jmpf_mem_r0_cs64__ud2_intel_c64, },  /* 16-bit CS, except in LM. */
     4458            { false, false, BS3_SEL_SPARE_00,       64, 0,  true, bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2_intel_c64, }, /* 16-bit CS, except in LM. */
     4459
     4460            { false,  true, BS3_SEL_R0_CS64,        64, 2, false, bs3CpuBasic2_callf_mem_same_r0__ud2_c64, },
     4461            { false,  true, BS3_SEL_R1_CS64 | 1,    64, 2, false, bs3CpuBasic2_callf_mem_same_r1__ud2_c64, },
     4462            { false,  true, BS3_SEL_R2_CS64 | 2,    64, 0, false, bs3CpuBasic2_callf_mem_same_r2__ud2_c64, },
     4463            { false,  true, BS3_SEL_R3_CS64 | 3,    64, 2, false, bs3CpuBasic2_callf_mem_same_r3__ud2_c64, },
     4464            { false,  true, BS3_SEL_R0_CS16,        16, 1, false, bs3CpuBasic2_callf_mem_r0_cs16__ud2_c64, },
     4465            { false,  true, BS3_SEL_R0_CS32,        32, 2, false, bs3CpuBasic2_callf_mem_r0_cs32__ud2_c64, },
     4466            { false,  true, BS3_SEL_R0_CS64,        64, 0, false, bs3CpuBasic2_callf_mem_r0_cs64__ud2_c64, },  /* 16-bit CS, except in LM. */
     4467            { false,  true, BS3_SEL_SPARE_00,       64, 0, false, bs3CpuBasic2_callf_mem_r0_cs16l__ud2_c64, }, /* 16-bit CS, except in LM. */
     4468
     4469            { false,  true, BS3_SEL_R0_CS64,        64, 2,  true, bs3CpuBasic2_callf_mem_same_r0__ud2_intel_c64, },
     4470            { false,  true, BS3_SEL_R1_CS64 | 1,    64, 2,  true, bs3CpuBasic2_callf_mem_same_r1__ud2_intel_c64, },
     4471            { false,  true, BS3_SEL_R2_CS64 | 2,    64, 0,  true, bs3CpuBasic2_callf_mem_same_r2__ud2_intel_c64, },
     4472            { false,  true, BS3_SEL_R3_CS64 | 3,    64, 2,  true, bs3CpuBasic2_callf_mem_same_r3__ud2_intel_c64, },
     4473            { false,  true, BS3_SEL_R0_CS16,        16, 1,  true, bs3CpuBasic2_callf_mem_r0_cs16__ud2_intel_c64, },
     4474            { false,  true, BS3_SEL_R0_CS32,        32, 0,  true, bs3CpuBasic2_callf_mem_r0_cs32__ud2_intel_c64, },
     4475            { false,  true, BS3_SEL_R0_CS64,        64, 2,  true, bs3CpuBasic2_callf_mem_r0_cs64__ud2_intel_c64, },  /* 16-bit CS, except in LM. */
     4476            { false,  true, BS3_SEL_SPARE_00,       64, 0,  true, bs3CpuBasic2_callf_mem_r0_cs16l__ud2_intel_c64, }, /* 16-bit CS, except in LM. */
    44214477        };
    44224478        BS3CPUVENDOR const enmCpuVendor = Bs3GetCpuVendor();
    … …  
    44274483            uint64_t const         uSavedRsp = Ctx.rsp.u;
    44284484            bool const             fUd       = s_aTests[iTest].fInvalid;
    4429             bool const             fGp       = !s_aTests[iTest].fCall && (s_aTests[iTest].uDstSel & X86_SEL_RPL) != 0;
     4485            bool const             fGp       = (s_aTests[iTest].uDstSel & X86_SEL_RPL) != 0;
    44304486            uint8_t const BS3_FAR *fpbCode   = Bs3SelLnkPtrToCurPtr(s_aTests[iTest].pfnTest);
    44314487
    … …  
    44494505            CtxExpected.rsp.u = Ctx.rsp.u;
    44504506            if (s_aTests[iTest].fCall && !fGp && !fUd)
    4451                 CtxExpected.rsp.u -= /*s_aTests[iTest].fOpSizePfx ? 4 :*/ 8;
     4507            {
     4508                CtxExpected.rsp.u -= s_aTests[iTest].fOpSizePfx == 0 ? 8
     4509                                   : s_aTests[iTest].fOpSizePfx == 1 ? 4 : 16;
     4510                //Bs3TestPrintf("cs:rsp=%04RX16:%04RX64 -> %04RX64 (fOpSizePfx=%d)\n", Ctx.ss, Ctx.rsp.u, CtxExpected.rsp.u, s_aTests[iTest].fOpSizePfx);
     4511            }
    44524512            //Bs3TestPrintf("cs:rip=%04RX16:%04RX64 -> %04RX16:%04RX64\n", Ctx.cs, Ctx.rip.u, CtxExpected.cs, CtxExpected.rip.u);
    44534513            Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx);
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