Changeset 97705 in vbox for trunk/include/VBox/vmm

Timestamp:

Nov 29, 2022 2:11:49 PM (2 years ago)

Author:

vboxsync

Message:

VMM/IEM,DBGF,CPUM: Do debugger I/O breakpoints via the internal EFLAGS bits too. Seems we might need two bits, so had to shift the internal bits down from 24 to 22. bugref:9898

Location:

trunk/include/VBox/vmm

Files:

• cpumctx.h (modified) (3 diffs)
• dbgf.h (modified) (1 diff)

trunk/include/VBox/vmm/cpumctx.h

@@ -261 +261 @@
  * clear drop in thruput, it would on the whole make the most sense to use 24
  * here.
- */
-#define CPUMX86EFLAGS_HW_BITS       24
+ *
+ * Update: We need more than 8 bits because of DBGF, so using 22 now.
+ */
+#define CPUMX86EFLAGS_HW_BITS       22
 /** Mask for the hardware EFLAGS bits, 64-bit version. */
 #define CPUMX86EFLAGS_HW_MASK_64    (RT_BIT_64(CPUMX86EFLAGS_HW_BITS) - UINT64_C(1))
@@ -275 +277 @@
 
 /** Mask of internal flags kept with EFLAGS, 64-bit version.
- * The first 3 available bits are taken by CPUMCTX_INHIBIT_SHADOW_SS,
- * CPUMCTX_INHIBIT_SHADOW_STI and CPUMCTX_INHIBIT_NMI.  The next 4 bits are
- * taken by CPUMCTX_DBG_HIT_DRX_MASK.
- */
-#define CPUMX86EFLAGS_INT_MASK_64   UINT64_C(0x000000007f000000)
+ * Bits 22-24 are taken by CPUMCTX_INHIBIT_SHADOW_SS, CPUMCTX_INHIBIT_SHADOW_STI
+ * and CPUMCTX_INHIBIT_NMI, bits 25-28 are for CPUMCTX_DBG_HIT_DRX_MASK, and
+ * bits 29-30 are for DBGF events and breakpoints.
+ *
+ * @todo The two DBGF bits could be merged.  The NMI inhibiting could move to
+ *       bit 32 or higher as it isn't automatically cleared on instruction
+ *       completion (except for iret).
+ */
+#define CPUMX86EFLAGS_INT_MASK_64   UINT64_C(0x00000000ffc00000)
 /** Mask of internal flags kept with EFLAGS, 32-bit version. */
-#define CPUMX86EFLAGS_INT_MASK_32           UINT32_C(0x7f000000)
+#define CPUMX86EFLAGS_INT_MASK_32           UINT32_C(0xffc00000)
 
 
@@ -1054 +1060 @@
 #define CPUMCTX_DBG_HIT_DRX_SHIFT       CPUMCTX_DBG_HIT_DR0_BIT
 /** Mask of all guest pending DR0-DR3 breakpoint indicators. */
-#define CPUMCTX_DBG_HIT_DRX_MASK       (CPUMCTX_DBG_HIT_DR0 | CPUMCTX_DBG_HIT_DR1 | CPUMCTX_DBG_HIT_DR2 | CPUMCTX_DBG_HIT_DR3)
-AssertCompile(CPUMCTX_DBG_HIT_DRX_MASK < UINT32_MAX);
+#define CPUMCTX_DBG_HIT_DRX_MASK        (CPUMCTX_DBG_HIT_DR0 | CPUMCTX_DBG_HIT_DR1 | CPUMCTX_DBG_HIT_DR2 | CPUMCTX_DBG_HIT_DR3)
+/** DBGF event/breakpoint pending. */
+#define CPUMCTX_DBG_DBGF_EVENT          RT_BIT_32(CPUMCTX_DBG_DBGF_EVENT_BIT)
+#define CPUMCTX_DBG_DBGF_EVENT_BIT      (7 + CPUMX86EFLAGS_HW_BITS)
+/** DBGF event/breakpoint pending. */
+#define CPUMCTX_DBG_DBGF_BP             RT_BIT_32(CPUMCTX_DBG_DBGF_BP_BIT)
+#define CPUMCTX_DBG_DBGF_BP_BIT         (8 + CPUMX86EFLAGS_HW_BITS)
+/** Mask of all DBGF indicators. */
+#define CPUMCTX_DBG_DBGF_MASK           (CPUMCTX_DBG_DBGF_EVENT | CPUMCTX_DBG_DBGF_BP)
+AssertCompile((CPUMCTX_DBG_HIT_DRX_MASK | CPUMCTX_DBG_DBGF_MASK) < UINT32_MAX);
 /** @}  */
 

trunk/include/VBox/vmm/dbgf.h

@@ -1124 +1124 @@
 VMM_INT_DECL(VBOXSTRICTRC)  DBGFBpCheckInstruction(PVMCC pVM, PVMCPUCC pVCpu, RTGCPTR GCPtrPC);
 VMM_INT_DECL(VBOXSTRICTRC)  DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue);
+VMM_INT_DECL(uint32_t)      DBGFBpCheckIo2(PVMCC pVM, PVMCPUCC pVCpu, RTIOPORT uIoPort, uint8_t cbValue);
 VMM_INT_DECL(VBOXSTRICTRC)  DBGFBpCheckPortIo(PVMCC pVM, PVMCPU pVCpu, RTIOPORT uIoPort,
                                               uint32_t fAccess, uint32_t uValue, bool fBefore);