Changeset 99404 in vbox for trunk/src/VBox/Devices/EFI/FirmwareNew/MdePkg/Include/IndustryStandard/Cxl11.h
- Timestamp:
- Apr 14, 2023 3:17:44 PM (2 years ago)
- svn:sync-xref-src-repo-rev:
- 156854
- Location:
- trunk/src/VBox/Devices/EFI/FirmwareNew
- Files:
-
- 2 edited
-
. (modified) (1 prop)
-
MdePkg/Include/IndustryStandard/Cxl11.h (modified) (11 diffs)
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- Removed
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trunk/src/VBox/Devices/EFI/FirmwareNew
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to (toggle deleted branches)/vendor/edk2/current 103735-103757,103769-103776,129194-145445 /vendor/edk2/current 103735-103757,103769-103776,129194-156846
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Property svn:mergeinfo
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trunk/src/VBox/Devices/EFI/FirmwareNew/MdePkg/Include/IndustryStandard/Cxl11.h
r89983 r99404 19 19 // (subject to change as per CXL assigned Vendor ID) 20 20 // 21 #define INTEL_CXL_DVSEC_VENDOR_ID 21 #define INTEL_CXL_DVSEC_VENDOR_ID 0x8086 22 22 23 23 // … … 25 25 // Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 26 26 // 27 #define CXL_DEV_DEV 28 #define CXL_DEV_FUNC 27 #define CXL_DEV_DEV 0 28 #define CXL_DEV_FUNC 0 29 29 30 30 // … … 72 72 typedef union { 73 73 struct { 74 UINT16 CacheCapable : 1;// bit 075 UINT16 IoCapable : 1;// bit 176 UINT16 MemCapable : 1;// bit 277 UINT16 MemHwInitMode : 1;// bit 378 UINT16 HdmCount : 2;// bit 4..579 UINT16 Reserved1 : 8;// bit 6..1380 UINT16 ViralCapable : 1;// bit 1481 UINT16 Reserved2 : 1;// bit 1582 } Bits; 83 UINT16 74 UINT16 CacheCapable : 1; // bit 0 75 UINT16 IoCapable : 1; // bit 1 76 UINT16 MemCapable : 1; // bit 2 77 UINT16 MemHwInitMode : 1; // bit 3 78 UINT16 HdmCount : 2; // bit 4..5 79 UINT16 Reserved1 : 8; // bit 6..13 80 UINT16 ViralCapable : 1; // bit 14 81 UINT16 Reserved2 : 1; // bit 15 82 } Bits; 83 UINT16 Uint16; 84 84 } CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY; 85 85 86 86 typedef union { 87 87 struct { 88 UINT16 CacheEnable : 1;// bit 089 UINT16 IoEnable : 1;// bit 190 UINT16 MemEnable : 1;// bit 291 UINT16 CacheSfCoverage : 5;// bit 3..792 UINT16 CacheSfGranularity : 3;// bit 8..1093 UINT16 CacheCleanEviction : 1;// bit 1194 UINT16 Reserved1 : 2;// bit 12..1395 UINT16 ViralEnable : 1;// bit 1496 UINT16 Reserved2 : 1;// bit 1597 } Bits; 98 UINT16 88 UINT16 CacheEnable : 1; // bit 0 89 UINT16 IoEnable : 1; // bit 1 90 UINT16 MemEnable : 1; // bit 2 91 UINT16 CacheSfCoverage : 5; // bit 3..7 92 UINT16 CacheSfGranularity : 3; // bit 8..10 93 UINT16 CacheCleanEviction : 1; // bit 11 94 UINT16 Reserved1 : 2; // bit 12..13 95 UINT16 ViralEnable : 1; // bit 14 96 UINT16 Reserved2 : 1; // bit 15 97 } Bits; 98 UINT16 Uint16; 99 99 } CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL; 100 100 101 101 typedef union { 102 102 struct { 103 UINT16 Reserved1 : 14;// bit 0..13104 UINT16 ViralStatus : 1;// bit 14105 UINT16 Reserved2 : 1;// bit 15106 } Bits; 107 UINT16 103 UINT16 Reserved1 : 14; // bit 0..13 104 UINT16 ViralStatus : 1; // bit 14 105 UINT16 Reserved2 : 1; // bit 15 106 } Bits; 107 UINT16 Uint16; 108 108 } CXL_DVSEC_FLEX_BUS_DEVICE_STATUS; 109 109 110 110 typedef union { 111 111 struct { 112 UINT16 Reserved1 : 1;// bit 0113 UINT16 Reserved2 : 1;// bit 1114 UINT16 Reserved3 : 1;// bit 2115 UINT16 Reserved4 : 13;// bit 3..15116 } Bits; 117 UINT16 112 UINT16 Reserved1 : 1; // bit 0 113 UINT16 Reserved2 : 1; // bit 1 114 UINT16 Reserved3 : 1; // bit 2 115 UINT16 Reserved4 : 13; // bit 3..15 116 } Bits; 117 UINT16 Uint16; 118 118 } CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2; 119 119 120 120 typedef union { 121 121 struct { 122 UINT16 Reserved1 : 1;// bit 0123 UINT16 Reserved2 : 1;// bit 1124 UINT16 Reserved3 : 14;// bit 2..15125 } Bits; 126 UINT16 122 UINT16 Reserved1 : 1; // bit 0 123 UINT16 Reserved2 : 1; // bit 1 124 UINT16 Reserved3 : 14; // bit 2..15 125 } Bits; 126 UINT16 Uint16; 127 127 } CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2; 128 128 129 129 typedef union { 130 130 struct { 131 UINT16 ConfigLock : 1;// bit 0132 UINT16 Reserved1 : 15;// bit 1..15133 } Bits; 134 UINT16 131 UINT16 ConfigLock : 1; // bit 0 132 UINT16 Reserved1 : 15; // bit 1..15 133 } Bits; 134 UINT16 Uint16; 135 135 } CXL_DVSEC_FLEX_BUS_DEVICE_LOCK; 136 136 137 137 typedef union { 138 138 struct { 139 UINT32 MemorySizeHigh : 32;// bit 0..31140 } Bits; 141 UINT32 139 UINT32 MemorySizeHigh : 32; // bit 0..31 140 } Bits; 141 UINT32 Uint32; 142 142 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH; 143 143 144 144 typedef union { 145 145 struct { 146 UINT32 MemoryInfoValid : 1;// bit 0147 UINT32 MemoryActive : 1;// bit 1148 UINT32 MediaType : 3;// bit 2..4149 UINT32 MemoryClass : 3;// bit 5..7150 UINT32 DesiredInterleave : 3;// bit 8..10151 UINT32 Reserved : 17;// bit 11..27152 UINT32 MemorySizeLow : 4;// bit 28..31153 } Bits; 154 UINT32 146 UINT32 MemoryInfoValid : 1; // bit 0 147 UINT32 MemoryActive : 1; // bit 1 148 UINT32 MediaType : 3; // bit 2..4 149 UINT32 MemoryClass : 3; // bit 5..7 150 UINT32 DesiredInterleave : 3; // bit 8..10 151 UINT32 Reserved : 17; // bit 11..27 152 UINT32 MemorySizeLow : 4; // bit 28..31 153 } Bits; 154 UINT32 Uint32; 155 155 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW; 156 156 157 157 typedef union { 158 158 struct { 159 UINT32 MemoryBaseHigh : 32;// bit 0..31160 } Bits; 161 UINT32 159 UINT32 MemoryBaseHigh : 32; // bit 0..31 160 } Bits; 161 UINT32 Uint32; 162 162 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH; 163 163 164 164 typedef union { 165 165 struct { 166 UINT32 Reserved : 28;// bit 0..27167 UINT32 MemoryBaseLow : 4;// bit 28..31168 } Bits; 169 UINT32 166 UINT32 Reserved : 28; // bit 0..27 167 UINT32 MemoryBaseLow : 4; // bit 28..31 168 } Bits; 169 UINT32 Uint32; 170 170 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW; 171 171 172 173 typedef union { 174 struct { 175 UINT32 MemorySizeHigh : 32; // bit 0..31 176 } Bits; 177 UINT32 Uint32; 172 typedef union { 173 struct { 174 UINT32 MemorySizeHigh : 32; // bit 0..31 175 } Bits; 176 UINT32 Uint32; 178 177 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH; 179 178 180 179 typedef union { 181 180 struct { 182 UINT32 MemoryInfoValid : 1;// bit 0183 UINT32 MemoryActive : 1;// bit 1184 UINT32 MediaType : 3;// bit 2..4185 UINT32 MemoryClass : 3;// bit 5..7186 UINT32 DesiredInterleave : 3;// bit 8..10187 UINT32 Reserved : 17;// bit 11..27188 UINT32 MemorySizeLow : 4;// bit 28..31189 } Bits; 190 UINT32 181 UINT32 MemoryInfoValid : 1; // bit 0 182 UINT32 MemoryActive : 1; // bit 1 183 UINT32 MediaType : 3; // bit 2..4 184 UINT32 MemoryClass : 3; // bit 5..7 185 UINT32 DesiredInterleave : 3; // bit 8..10 186 UINT32 Reserved : 17; // bit 11..27 187 UINT32 MemorySizeLow : 4; // bit 28..31 188 } Bits; 189 UINT32 Uint32; 191 190 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW; 192 191 193 192 typedef union { 194 193 struct { 195 UINT32 MemoryBaseHigh : 32;// bit 0..31196 } Bits; 197 UINT32 194 UINT32 MemoryBaseHigh : 32; // bit 0..31 195 } Bits; 196 UINT32 Uint32; 198 197 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH; 199 198 200 199 typedef union { 201 200 struct { 202 UINT32 Reserved : 28;// bit 0..27203 UINT32 MemoryBaseLow : 4;// bit 28..31204 } Bits; 205 UINT32 201 UINT32 Reserved : 28; // bit 0..27 202 UINT32 MemoryBaseLow : 4; // bit 28..31 203 } Bits; 204 UINT32 Uint32; 206 205 } CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW; 207 206 … … 210 209 // Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Table 58 211 210 // 212 #define FLEX_BUS_DEVICE_DVSEC_ID 211 #define FLEX_BUS_DEVICE_DVSEC_ID 0 213 212 214 213 // … … 217 216 // 218 217 typedef struct { 219 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;// offset 0220 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;// offset 4221 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;// offset 8222 CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability;// offset 10223 CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl;// offset 12224 CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus;// offset 14225 CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2;// offset 16226 CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2;// offset 18227 CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock;// offset 20228 UINT16 Reserved;// offset 22229 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh;// offset 24230 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow;// offset 28231 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh;// offset 32232 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow;// offset 36233 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh;// offset 40234 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow;// offset 44235 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh;// offset 48236 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow;// offset 52218 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0 219 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4 220 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8 221 CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10 222 CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12 223 CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14 224 CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16 225 CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18 226 CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20 227 UINT16 Reserved; // offset 22 228 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24 229 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28 230 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32 231 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36 232 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40 233 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44 234 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48 235 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52 237 236 } CXL_1_1_DVSEC_FLEX_BUS_DEVICE; 238 237 239 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header 238 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header, 0x00); 240 239 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader1, 0x04); 241 240 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader2, 0x08); 242 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability 243 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl 244 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus 245 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2 246 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2 247 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock 248 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh 249 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow 250 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh 251 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow 252 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh 253 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow 254 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh 255 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow 256 CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, 0x38);241 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability, 0x0A); 242 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl, 0x0C); 243 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus, 0x0E); 244 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2, 0x10); 245 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2, 0x12); 246 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock, 0x14); 247 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh, 0x18); 248 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow, 0x1C); 249 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh, 0x20); 250 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow, 0x24); 251 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh, 0x28); 252 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow, 0x2C); 253 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh, 0x30); 254 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow, 0x34); 255 CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, 0x38); 257 256 ///@} 258 257 … … 262 261 typedef union { 263 262 struct { 264 UINT16 CacheCapable : 1;// bit 0265 UINT16 IoCapable : 1;// bit 1266 UINT16 MemCapable : 1;// bit 2267 UINT16 Reserved : 13;// bit 3..15268 } Bits; 269 UINT16 263 UINT16 CacheCapable : 1; // bit 0 264 UINT16 IoCapable : 1; // bit 1 265 UINT16 MemCapable : 1; // bit 2 266 UINT16 Reserved : 13; // bit 3..15 267 } Bits; 268 UINT16 Uint16; 270 269 } CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY; 271 270 272 271 typedef union { 273 272 struct { 274 UINT16 CacheEnable : 1;// bit 0275 UINT16 IoEnable : 1;// bit 1276 UINT16 MemEnable : 1;// bit 2277 UINT16 CxlSyncBypassEnable : 1;// bit 3278 UINT16 DriftBufferEnable : 1;// bit 4279 UINT16 Reserved : 3;// bit 5..7280 UINT16 Retimer1Present : 1;// bit 8281 UINT16 Retimer2Present : 1;// bit 9282 UINT16 Reserved2 : 6;// bit 10..15283 } Bits; 284 UINT16 273 UINT16 CacheEnable : 1; // bit 0 274 UINT16 IoEnable : 1; // bit 1 275 UINT16 MemEnable : 1; // bit 2 276 UINT16 CxlSyncBypassEnable : 1; // bit 3 277 UINT16 DriftBufferEnable : 1; // bit 4 278 UINT16 Reserved : 3; // bit 5..7 279 UINT16 Retimer1Present : 1; // bit 8 280 UINT16 Retimer2Present : 1; // bit 9 281 UINT16 Reserved2 : 6; // bit 10..15 282 } Bits; 283 UINT16 Uint16; 285 284 } CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL; 286 285 287 286 typedef union { 288 287 struct { 289 UINT16 CacheEnable : 1;// bit 0290 UINT16 IoEnable : 1;// bit 1291 UINT16 MemEnable : 1;// bit 2292 UINT16 CxlSyncBypassEnable : 1;// bit 3293 UINT16 DriftBufferEnable : 1;// bit 4294 UINT16 Reserved : 3;// bit 5..7295 UINT16 CxlCorrectableProtocolIdFramingError : 1;// bit 8296 UINT16 CxlUncorrectableProtocolIdFramingError : 1;// bit 9297 UINT16 CxlUnexpectedProtocolIdDropped : 1;// bit 10298 UINT16 Reserved2 : 5;// bit 11..15299 } Bits; 300 UINT16 288 UINT16 CacheEnable : 1; // bit 0 289 UINT16 IoEnable : 1; // bit 1 290 UINT16 MemEnable : 1; // bit 2 291 UINT16 CxlSyncBypassEnable : 1; // bit 3 292 UINT16 DriftBufferEnable : 1; // bit 4 293 UINT16 Reserved : 3; // bit 5..7 294 UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8 295 UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9 296 UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10 297 UINT16 Reserved2 : 5; // bit 11..15 298 } Bits; 299 UINT16 Uint16; 301 300 } CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS; 302 301 … … 305 304 // Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Table 62 306 305 // 307 #define FLEX_BUS_PORT_DVSEC_ID 306 #define FLEX_BUS_PORT_DVSEC_ID 7 308 307 309 308 // … … 312 311 // 313 312 typedef struct { 314 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;// offset 0315 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;// offset 4316 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;// offset 8317 CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability;// offset 10318 CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl;// offset 12319 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus;// offset 14313 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0 314 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4 315 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8 316 CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10 317 CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12 318 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14 320 319 } CXL_1_1_DVSEC_FLEX_BUS_PORT; 321 320 322 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header 321 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header, 0x00); 323 322 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader1, 0x04); 324 323 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader2, 0x08); 325 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability 326 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl 327 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus 328 CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, 0x10);324 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability, 0x0A); 325 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl, 0x0C); 326 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus, 0x0E); 327 CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, 0x10); 329 328 ///@} 330 329 … … 337 336 ///@{ 338 337 339 #define CXL_CAPABILITY_HEADER_OFFSET 340 typedef union { 341 struct { 342 UINT32 CxlCapabilityId : 16;// bit 0..15343 UINT32 CxlCapabilityVersion : 4;// bit 16..19344 UINT32 CxlCacheMemVersion : 4;// bit 20..23345 UINT32 ArraySize : 8;// bit 24..31346 } Bits; 347 UINT32 338 #define CXL_CAPABILITY_HEADER_OFFSET 0 339 typedef union { 340 struct { 341 UINT32 CxlCapabilityId : 16; // bit 0..15 342 UINT32 CxlCapabilityVersion : 4; // bit 16..19 343 UINT32 CxlCacheMemVersion : 4; // bit 20..23 344 UINT32 ArraySize : 8; // bit 24..31 345 } Bits; 346 UINT32 Uint32; 348 347 } CXL_CAPABILITY_HEADER; 349 348 350 #define CXL_RAS_CAPABILITY_HEADER_OFFSET 351 typedef union { 352 struct { 353 UINT32 CxlCapabilityId : 16;// bit 0..15354 UINT32 CxlCapabilityVersion : 4;// bit 16..19355 UINT32 CxlRasCapabilityPointer : 12;// bit 20..31356 } Bits; 357 UINT32 349 #define CXL_RAS_CAPABILITY_HEADER_OFFSET 4 350 typedef union { 351 struct { 352 UINT32 CxlCapabilityId : 16; // bit 0..15 353 UINT32 CxlCapabilityVersion : 4; // bit 16..19 354 UINT32 CxlRasCapabilityPointer : 12; // bit 20..31 355 } Bits; 356 UINT32 Uint32; 358 357 } CXL_RAS_CAPABILITY_HEADER; 359 358 360 #define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 361 typedef union { 362 struct { 363 UINT32 CxlCapabilityId : 16;// bit 0..15364 UINT32 CxlCapabilityVersion : 4;// bit 16..19365 UINT32 CxlSecurityCapabilityPointer : 12;// bit 20..31366 } Bits; 367 UINT32 359 #define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8 360 typedef union { 361 struct { 362 UINT32 CxlCapabilityId : 16; // bit 0..15 363 UINT32 CxlCapabilityVersion : 4; // bit 16..19 364 UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31 365 } Bits; 366 UINT32 Uint32; 368 367 } CXL_SECURITY_CAPABILITY_HEADER; 369 368 370 #define CXL_LINK_CAPABILITY_HEADER_OFFSET 371 typedef union { 372 struct { 373 UINT32 CxlCapabilityId : 16;// bit 0..15374 UINT32 CxlCapabilityVersion : 4;// bit 16..19375 UINT32 CxlLinkCapabilityPointer : 12;// bit 20..31376 } Bits; 377 UINT32 369 #define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC 370 typedef union { 371 struct { 372 UINT32 CxlCapabilityId : 16; // bit 0..15 373 UINT32 CxlCapabilityVersion : 4; // bit 16..19 374 UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31 375 } Bits; 376 UINT32 Uint32; 378 377 } CXL_LINK_CAPABILITY_HEADER; 379 378 380 379 typedef union { 381 380 struct { 382 UINT32 CacheDataParity : 1;// bit 0..0383 UINT32 CacheAddressParity : 1;// bit 1..1384 UINT32 CacheByteEnableParity : 1;// bit 2..2385 UINT32 CacheDataEcc : 1;// bit 3..3386 UINT32 MemDataParity : 1;// bit 4..4387 UINT32 MemAddressParity : 1;// bit 5..5388 UINT32 MemByteEnableParity : 1;// bit 6..6389 UINT32 MemDataEcc : 1;// bit 7..7390 UINT32 ReInitThreshold : 1;// bit 8..8391 UINT32 RsvdEncodingViolation : 1;// bit 9..9392 UINT32 PoisonReceived : 1;// bit 10..10393 UINT32 ReceiverOverflow : 1;// bit 11..11394 UINT32 Reserved : 20;// bit 12..31395 } Bits; 396 UINT32 381 UINT32 CacheDataParity : 1; // bit 0..0 382 UINT32 CacheAddressParity : 1; // bit 1..1 383 UINT32 CacheByteEnableParity : 1; // bit 2..2 384 UINT32 CacheDataEcc : 1; // bit 3..3 385 UINT32 MemDataParity : 1; // bit 4..4 386 UINT32 MemAddressParity : 1; // bit 5..5 387 UINT32 MemByteEnableParity : 1; // bit 6..6 388 UINT32 MemDataEcc : 1; // bit 7..7 389 UINT32 ReInitThreshold : 1; // bit 8..8 390 UINT32 RsvdEncodingViolation : 1; // bit 9..9 391 UINT32 PoisonReceived : 1; // bit 10..10 392 UINT32 ReceiverOverflow : 1; // bit 11..11 393 UINT32 Reserved : 20; // bit 12..31 394 } Bits; 395 UINT32 Uint32; 397 396 } CXL_1_1_UNCORRECTABLE_ERROR_STATUS; 398 397 399 398 typedef union { 400 399 struct { 401 UINT32 CacheDataParityMask : 1;// bit 0..0402 UINT32 CacheAddressParityMask : 1;// bit 1..1403 UINT32 CacheByteEnableParityMask : 1;// bit 2..2404 UINT32 CacheDataEccMask : 1;// bit 3..3405 UINT32 MemDataParityMask : 1;// bit 4..4406 UINT32 MemAddressParityMask : 1;// bit 5..5407 UINT32 MemByteEnableParityMask : 1;// bit 6..6408 UINT32 MemDataEccMask : 1;// bit 7..7409 UINT32 ReInitThresholdMask : 1;// bit 8..8410 UINT32 RsvdEncodingViolationMask : 1;// bit 9..9411 UINT32 PoisonReceivedMask : 1;// bit 10..10412 UINT32 ReceiverOverflowMask : 1;// bit 11..11413 UINT32 Reserved : 20;// bit 12..31414 } Bits; 415 UINT32 400 UINT32 CacheDataParityMask : 1; // bit 0..0 401 UINT32 CacheAddressParityMask : 1; // bit 1..1 402 UINT32 CacheByteEnableParityMask : 1; // bit 2..2 403 UINT32 CacheDataEccMask : 1; // bit 3..3 404 UINT32 MemDataParityMask : 1; // bit 4..4 405 UINT32 MemAddressParityMask : 1; // bit 5..5 406 UINT32 MemByteEnableParityMask : 1; // bit 6..6 407 UINT32 MemDataEccMask : 1; // bit 7..7 408 UINT32 ReInitThresholdMask : 1; // bit 8..8 409 UINT32 RsvdEncodingViolationMask : 1; // bit 9..9 410 UINT32 PoisonReceivedMask : 1; // bit 10..10 411 UINT32 ReceiverOverflowMask : 1; // bit 11..11 412 UINT32 Reserved : 20; // bit 12..31 413 } Bits; 414 UINT32 Uint32; 416 415 } CXL_1_1_UNCORRECTABLE_ERROR_MASK; 417 416 418 417 typedef union { 419 418 struct { 420 UINT32 CacheDataParitySeverity : 1;// bit 0..0421 UINT32 CacheAddressParitySeverity : 1;// bit 1..1422 UINT32 CacheByteEnableParitySeverity : 1;// bit 2..2423 UINT32 CacheDataEccSeverity : 1;// bit 3..3424 UINT32 MemDataParitySeverity : 1;// bit 4..4425 UINT32 MemAddressParitySeverity : 1;// bit 5..5426 UINT32 MemByteEnableParitySeverity : 1;// bit 6..6427 UINT32 MemDataEccSeverity : 1;// bit 7..7428 UINT32 ReInitThresholdSeverity : 1;// bit 8..8429 UINT32 RsvdEncodingViolationSeverity : 1;// bit 9..9430 UINT32 PoisonReceivedSeverity : 1;// bit 10..10431 UINT32 ReceiverOverflowSeverity : 1;// bit 11..11432 UINT32 Reserved : 20;// bit 12..31433 } Bits; 434 UINT32 419 UINT32 CacheDataParitySeverity : 1; // bit 0..0 420 UINT32 CacheAddressParitySeverity : 1; // bit 1..1 421 UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2 422 UINT32 CacheDataEccSeverity : 1; // bit 3..3 423 UINT32 MemDataParitySeverity : 1; // bit 4..4 424 UINT32 MemAddressParitySeverity : 1; // bit 5..5 425 UINT32 MemByteEnableParitySeverity : 1; // bit 6..6 426 UINT32 MemDataEccSeverity : 1; // bit 7..7 427 UINT32 ReInitThresholdSeverity : 1; // bit 8..8 428 UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9 429 UINT32 PoisonReceivedSeverity : 1; // bit 10..10 430 UINT32 ReceiverOverflowSeverity : 1; // bit 11..11 431 UINT32 Reserved : 20; // bit 12..31 432 } Bits; 433 UINT32 Uint32; 435 434 } CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY; 436 435 437 436 typedef union { 438 437 struct { 439 UINT32 CacheDataEcc : 1;// bit 0..0440 UINT32 MemoryDataEcc : 1;// bit 1..1441 UINT32 CrcThreshold : 1;// bit 2..2442 UINT32 RetryThreshold : 1;// bit 3..3443 UINT32 CachePoisonReceived : 1;// bit 4..4444 UINT32 MemoryPoisonReceived : 1;// bit 5..5445 UINT32 PhysicalLayerError : 1;// bit 6..6446 UINT32 Reserved : 25;// bit 7..31447 } Bits; 448 UINT32 438 UINT32 CacheDataEcc : 1; // bit 0..0 439 UINT32 MemoryDataEcc : 1; // bit 1..1 440 UINT32 CrcThreshold : 1; // bit 2..2 441 UINT32 RetryThreshold : 1; // bit 3..3 442 UINT32 CachePoisonReceived : 1; // bit 4..4 443 UINT32 MemoryPoisonReceived : 1; // bit 5..5 444 UINT32 PhysicalLayerError : 1; // bit 6..6 445 UINT32 Reserved : 25; // bit 7..31 446 } Bits; 447 UINT32 Uint32; 449 448 } CXL_CORRECTABLE_ERROR_STATUS; 450 449 451 450 typedef union { 452 451 struct { 453 UINT32 CacheDataEccMask : 1;// bit 0..0454 UINT32 MemoryDataEccMask : 1;// bit 1..1455 UINT32 CrcThresholdMask : 1;// bit 2..2456 UINT32 RetryThresholdMask : 1;// bit 3..3457 UINT32 CachePoisonReceivedMask : 1;// bit 4..4458 UINT32 MemoryPoisonReceivedMask : 1;// bit 5..5459 UINT32 PhysicalLayerErrorMask : 1;// bit 6..6460 UINT32 Reserved : 25;// bit 7..31461 } Bits; 462 UINT32 452 UINT32 CacheDataEccMask : 1; // bit 0..0 453 UINT32 MemoryDataEccMask : 1; // bit 1..1 454 UINT32 CrcThresholdMask : 1; // bit 2..2 455 UINT32 RetryThresholdMask : 1; // bit 3..3 456 UINT32 CachePoisonReceivedMask : 1; // bit 4..4 457 UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5 458 UINT32 PhysicalLayerErrorMask : 1; // bit 6..6 459 UINT32 Reserved : 25; // bit 7..31 460 } Bits; 461 UINT32 Uint32; 463 462 } CXL_CORRECTABLE_ERROR_MASK; 464 463 465 464 typedef union { 466 465 struct { 467 UINT32 FirstErrorPointer : 4;// bit 0..3468 UINT32 Reserved1 : 5;// bit 4..8469 UINT32 MultipleHeaderRecordingCapability : 1;// bit 9..9470 UINT32 Reserved2 : 3;// bit 10..12471 UINT32 PoisonEnabled : 1;// bit 13..13472 UINT32 Reserved3 : 18;// bit 14..31473 } Bits; 474 UINT32 466 UINT32 FirstErrorPointer : 4; // bit 0..3 467 UINT32 Reserved1 : 5; // bit 4..8 468 UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9 469 UINT32 Reserved2 : 3; // bit 10..12 470 UINT32 PoisonEnabled : 1; // bit 13..13 471 UINT32 Reserved3 : 18; // bit 14..31 472 } Bits; 473 UINT32 Uint32; 475 474 } CXL_ERROR_CAPABILITIES_AND_CONTROL; 476 475 477 476 typedef struct { 478 CXL_1_1_UNCORRECTABLE_ERROR_STATUS 479 CXL_1_1_UNCORRECTABLE_ERROR_MASK 480 CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY 481 CXL_CORRECTABLE_ERROR_STATUS 482 CXL_CORRECTABLE_ERROR_MASK 483 CXL_ERROR_CAPABILITIES_AND_CONTROL 484 UINT32 477 CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus; 478 CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask; 479 CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity; 480 CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus; 481 CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask; 482 CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl; 483 UINT32 HeaderLog[16]; 485 484 } CXL_1_1_RAS_CAPABILITY_STRUCTURE; 486 485 487 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus 488 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask 489 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity 490 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus 491 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask 486 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus, 0x00); 487 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask, 0x04); 488 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity, 0x08); 489 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus, 0x0C); 490 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask, 0x10); 492 491 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, ErrorCapabilitiesAndControl, 0x14); 493 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog 494 CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, 0x58);495 496 typedef union { 497 struct { 498 UINT32 DeviceTrustLevel : 2;// bit 0..1499 UINT32 Reserved : 30;// bit 2..31500 } Bits; 501 UINT32 492 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog, 0x18); 493 CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, 0x58); 494 495 typedef union { 496 struct { 497 UINT32 DeviceTrustLevel : 2; // bit 0..1 498 UINT32 Reserved : 30; // bit 2..31 499 } Bits; 500 UINT32 Uint32; 502 501 } CXL_1_1_SECURITY_POLICY; 503 502 504 503 typedef struct { 505 CXL_1_1_SECURITY_POLICY 504 CXL_1_1_SECURITY_POLICY SecurityPolicy; 506 505 } CXL_1_1_SECURITY_CAPABILITY_STRUCTURE; 507 506 508 507 CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, SecurityPolicy, 0x0); 509 CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE,0x4);510 511 typedef union { 512 struct { 513 UINT64 CxlLinkVersionSupported : 4;// bit 0..3514 UINT64 CxlLinkVersionReceived : 4;// bit 4..7515 UINT64 LlrWrapValueSupported : 8;// bit 8..15516 UINT64 LlrWrapValueReceived : 8;// bit 16..23517 UINT64 NumRetryReceived : 5;// bit 24..28518 UINT64 NumPhyReinitReceived : 5;// bit 29..33519 UINT64 WrPtrReceived : 8;// bit 34..41520 UINT64 EchoEseqReceived : 8;// bit 42..49521 UINT64 NumFreeBufReceived : 8;// bit 50..57522 UINT64 Reserved : 6;// bit 58..63523 } Bits; 524 UINT64 508 CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4); 509 510 typedef union { 511 struct { 512 UINT64 CxlLinkVersionSupported : 4; // bit 0..3 513 UINT64 CxlLinkVersionReceived : 4; // bit 4..7 514 UINT64 LlrWrapValueSupported : 8; // bit 8..15 515 UINT64 LlrWrapValueReceived : 8; // bit 16..23 516 UINT64 NumRetryReceived : 5; // bit 24..28 517 UINT64 NumPhyReinitReceived : 5; // bit 29..33 518 UINT64 WrPtrReceived : 8; // bit 34..41 519 UINT64 EchoEseqReceived : 8; // bit 42..49 520 UINT64 NumFreeBufReceived : 8; // bit 50..57 521 UINT64 Reserved : 6; // bit 58..63 522 } Bits; 523 UINT64 Uint64; 525 524 } CXL_LINK_LAYER_CAPABILITY; 526 525 527 526 typedef union { 528 527 struct { 529 UINT16 LlReset : 1;// bit 0..0530 UINT16 LlInitStall : 1;// bit 1..1531 UINT16 LlCrdStall : 1;// bit 2..2532 UINT16 InitState : 2;// bit 3..4533 UINT16 LlRetryBufferConsumed : 8;// bit 5..12534 UINT16 Reserved : 3;// bit 13..15535 } Bits; 536 UINT64 528 UINT16 LlReset : 1; // bit 0..0 529 UINT16 LlInitStall : 1; // bit 1..1 530 UINT16 LlCrdStall : 1; // bit 2..2 531 UINT16 InitState : 2; // bit 3..4 532 UINT16 LlRetryBufferConsumed : 8; // bit 5..12 533 UINT16 Reserved : 3; // bit 13..15 534 } Bits; 535 UINT64 Uint64; 537 536 } CXL_LINK_LAYER_CONTROL_AND_STATUS; 538 537 539 538 typedef union { 540 539 struct { 541 UINT64 CacheReqCredits : 10;// bit 0..9542 UINT64 CacheRspCredits : 10;// bit 10..19543 UINT64 CacheDataCredits : 10;// bit 20..29544 UINT64 MemReqRspCredits : 10;// bit 30..39545 UINT64 MemDataCredits : 10;// bit 40..49546 } Bits; 547 UINT64 540 UINT64 CacheReqCredits : 10; // bit 0..9 541 UINT64 CacheRspCredits : 10; // bit 10..19 542 UINT64 CacheDataCredits : 10; // bit 20..29 543 UINT64 MemReqRspCredits : 10; // bit 30..39 544 UINT64 MemDataCredits : 10; // bit 40..49 545 } Bits; 546 UINT64 Uint64; 548 547 } CXL_LINK_LAYER_RX_CREDIT_CONTROL; 549 548 550 549 typedef union { 551 550 struct { 552 UINT64 CacheReqCredits : 10;// bit 0..9553 UINT64 CacheRspCredits : 10;// bit 10..19554 UINT64 CacheDataCredits : 10;// bit 20..29555 UINT64 MemReqRspCredits : 10;// bit 30..39556 UINT64 MemDataCredits : 10;// bit 40..49557 } Bits; 558 UINT64 551 UINT64 CacheReqCredits : 10; // bit 0..9 552 UINT64 CacheRspCredits : 10; // bit 10..19 553 UINT64 CacheDataCredits : 10; // bit 20..29 554 UINT64 MemReqRspCredits : 10; // bit 30..39 555 UINT64 MemDataCredits : 10; // bit 40..49 556 } Bits; 557 UINT64 Uint64; 559 558 } CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS; 560 559 561 560 typedef union { 562 561 struct { 563 UINT64 CacheReqCredits : 10;// bit 0..9564 UINT64 CacheRspCredits : 10;// bit 10..19565 UINT64 CacheDataCredits : 10;// bit 20..29566 UINT64 MemReqRspCredits : 10;// bit 30..39567 UINT64 MemDataCredits : 10;// bit 40..49568 } Bits; 569 UINT64 562 UINT64 CacheReqCredits : 10; // bit 0..9 563 UINT64 CacheRspCredits : 10; // bit 10..19 564 UINT64 CacheDataCredits : 10; // bit 20..29 565 UINT64 MemReqRspCredits : 10; // bit 30..39 566 UINT64 MemDataCredits : 10; // bit 40..49 567 } Bits; 568 UINT64 Uint64; 570 569 } CXL_LINK_LAYER_TX_CREDIT_STATUS; 571 570 572 571 typedef union { 573 572 struct { 574 UINT32 AckForceThreshold : 8;// bit 0..7575 UINT32 AckFLushRetimer : 10;// bit 8..17576 } Bits; 577 UINT64 573 UINT32 AckForceThreshold : 8; // bit 0..7 574 UINT32 AckFLushRetimer : 10; // bit 8..17 575 } Bits; 576 UINT64 Uint64; 578 577 } CXL_LINK_LAYER_ACK_TIMER_CONTROL; 579 578 580 579 typedef union { 581 580 struct { 582 UINT32 MdhDisable : 1;// bit 0..0583 UINT32 Reserved : 31;// bit 1..31584 } Bits; 585 UINT64 581 UINT32 MdhDisable : 1; // bit 0..0 582 UINT32 Reserved : 31; // bit 1..31 583 } Bits; 584 UINT64 Uint64; 586 585 } CXL_LINK_LAYER_DEFEATURE; 587 586 588 587 typedef struct { 589 CXL_LINK_LAYER_CAPABILITY 590 CXL_LINK_LAYER_CONTROL_AND_STATUS 591 CXL_LINK_LAYER_RX_CREDIT_CONTROL 592 CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS 593 CXL_LINK_LAYER_TX_CREDIT_STATUS 594 CXL_LINK_LAYER_ACK_TIMER_CONTROL 595 CXL_LINK_LAYER_DEFEATURE 588 CXL_LINK_LAYER_CAPABILITY LinkLayerCapability; 589 CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus; 590 CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl; 591 CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus; 592 CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus; 593 CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl; 594 CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature; 596 595 } CXL_1_1_LINK_CAPABILITY_STRUCTURE; 597 596 598 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability 599 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus 600 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl 597 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability, 0x00); 598 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus, 0x08); 599 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl, 0x10); 601 600 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditReturnStatus, 0x18); 602 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus 603 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl 604 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature 605 CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, 0x38);606 607 #define CXL_IO_ARBITRATION_CONTROL_OFFSET 608 typedef union { 609 struct { 610 UINT32 Reserved1 : 4;// bit 0..3611 UINT32 WeightedRoundRobinArbitrationWeight : 4;// bit 4..7612 UINT32 Reserved2 : 24;// bit 8..31613 } Bits; 614 UINT32 601 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus, 0x20); 602 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl, 0x28); 603 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature, 0x30); 604 CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, 0x38); 605 606 #define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180 607 typedef union { 608 struct { 609 UINT32 Reserved1 : 4; // bit 0..3 610 UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7 611 UINT32 Reserved2 : 24; // bit 8..31 612 } Bits; 613 UINT32 Uint32; 615 614 } CXL_IO_ARBITRATION_CONTROL; 616 615 617 616 CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL, 0x4); 618 617 619 #define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 620 typedef union { 621 struct { 622 UINT32 Reserved1 : 4;// bit 0..3623 UINT32 WeightedRoundRobinArbitrationWeight : 4;// bit 4..7624 UINT32 Reserved2 : 24;// bit 8..31625 } Bits; 626 UINT32 618 #define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0 619 typedef union { 620 struct { 621 UINT32 Reserved1 : 4; // bit 0..3 622 UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7 623 UINT32 Reserved2 : 24; // bit 8..31 624 } Bits; 625 UINT32 Uint32; 627 626 } CXL_CACHE_MEMORY_ARBITRATION_CONTROL; 628 627 … … 636 635 typedef union { 637 636 struct { 638 UINT64 RcrbEnable : 1;// bit 0..0639 UINT64 Reserved : 12;// bit 1..12640 UINT64 RcrbBaseAddress : 51;// bit 13..63641 } Bits; 642 UINT64 637 UINT64 RcrbEnable : 1; // bit 0..0 638 UINT64 Reserved : 12; // bit 1..12 639 UINT64 RcrbBaseAddress : 51; // bit 13..63 640 } Bits; 641 UINT64 Uint64; 643 642 } CXL_RCRB_BASE; 644 643 … … 653 652 // Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - Figure 97 654 653 // 655 #define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 656 #define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 657 #define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 654 #define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010 655 #define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014 656 #define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100 658 657 659 658 #endif
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