Changeset 99576 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

May 3, 2023 10:24:27 AM (20 months ago)

Author:

vboxsync

Message:

VMM: Preparations for getting interrupts injected into the guest. With ARMv8 there are two types of interrupts (normal interrupts and fast interrupts) which need to be mapped to forced action flags. Because the PIC and APIC flags are not needed those are mapped to IRQs and FIQs on ARM respectively, bugref:10389

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• CPUMAllRegs-armv8.cpp (modified) (2 diffs)
• PDMAll.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/VMMAll/CPUMAllRegs-armv8.cpp

@@ -46 +46 @@
 #include <VBox/vmm/hm.h>
 #include <VBox/vmm/tm.h>
+
+#include <iprt/armv8.h>
 #include <iprt/assert.h>
 #include <iprt/asm.h>
@@ -99 +101 @@
     AssertReleaseFailed(); /** @todo Exception level. */
     return pVCpu->cpum.s.Guest.aSpReg[0].u64;
+}
+
+
+/**
+ * Returns whether IRQs are currently masked.
+ *
+ * @returns true if IRQs are masked as indicated by the PState value.
+ * @param   pVCpu       The cross context virtual CPU structure.
+ */
+VMMDECL(bool)       CPUMGetGuestIrqMasked(PVMCPUCC pVCpu)
+{
+    CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_PSTATE);
+    return RT_BOOL(pVCpu->cpum.s.Guest.fPState & ARMV8_SPSR_EL2_AARCH64_I);
+}
+
+
+/**
+ * Returns whether FIQs are currently masked.
+ *
+ * @returns true if FIQs are masked as indicated by the PState value.
+ * @param   pVCpu       The cross context virtual CPU structure.
+ */
+VMMDECL(bool)       CPUMGetGuestFiqMasked(PVMCPUCC pVCpu)
+{
+    CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_PSTATE);
+    return RT_BOOL(pVCpu->cpum.s.Guest.fPState & ARMV8_SPSR_EL2_AARCH64_F);
 }
 

trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

@@ -46 +46 @@
 
 
-
+#if !defined(VBOX_VMM_TARGET_ARMV8)
 /**
  * Gets the pending interrupt.
@@ -70 +70 @@
     {
         VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
-#if defined(VBOX_VMM_TARGET_ARMV8)
-        AssertReleaseFailed();
-#else
+
         uint32_t uTagSrc;
         rc = APICGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
@@ -83 +81 @@
         /* else if it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
            interrupts shouldn't prevent ExtINT from being delivered. */
-#endif
     }
 
@@ -121 +118 @@
     return rc;
 }
+#endif