| 1 | /* $Id: IEMAllInstCommonBodyMacros.h 103642 2024-03-02 01:01:44Z vboxsync $ */
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| 2 | /** @file
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| 3 | * IEM - Instruction Decoding and Emulation, Common Body Macros.
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| 4 | *
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| 5 | * This is placed in its own file without anything else in it, so that it can
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| 6 | * be digested by SimplerParser in IEMAllInstPython.py prior processing
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| 7 | * any of the other IEMAllInstruction*.cpp.h files. For instance
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| 8 | * IEMAllInstCommon.cpp.h wouldn't do as it defines several invalid
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| 9 | * instructions and such that could confuse the parser result.
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| 10 | */
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| 11 |
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| 12 | /*
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| 13 | * Copyright (C) 2011-2023 Oracle and/or its affiliates.
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| 14 | *
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| 15 | * This file is part of VirtualBox base platform packages, as
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| 16 | * available from https://www.virtualbox.org.
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| 17 | *
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| 18 | * This program is free software; you can redistribute it and/or
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| 19 | * modify it under the terms of the GNU General Public License
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| 20 | * as published by the Free Software Foundation, in version 3 of the
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| 21 | * License.
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| 22 | *
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| 23 | * This program is distributed in the hope that it will be useful, but
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| 24 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 26 | * General Public License for more details.
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| 27 | *
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| 28 | * You should have received a copy of the GNU General Public License
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| 29 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 30 | *
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| 31 | * SPDX-License-Identifier: GPL-3.0-only
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| 32 | */
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| 33 |
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| 34 |
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| 35 | /**
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| 36 | * Body for word/dword/qword instructions like ADD, AND, OR, ++ with a register
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| 37 | * as the destination.
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| 38 | *
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| 39 | * @note Used both in OneByte and TwoByte0f.
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| 40 | */
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| 41 | #define IEMOP_BODY_BINARY_rv_rm(a_bRm, a_fnNormalU16, a_fnNormalU32, a_fnNormalU64, a_fModifiesDstReg, a_f16BitMcFlag, a_EmitterBasename, a_fNativeArchs) \
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| 42 | /* \
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| 43 | * If rm is denoting a register, no more instruction bytes. \
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| 44 | */ \
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| 45 | if (IEM_IS_MODRM_REG_MODE(a_bRm)) \
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| 46 | { \
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| 47 | switch (pVCpu->iem.s.enmEffOpSize) \
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| 48 | { \
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| 49 | case IEMMODE_16BIT: \
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| 50 | IEM_MC_BEGIN(3, 0, a_f16BitMcFlag, 0); \
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| 51 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| 52 | IEM_MC_ARG(uint16_t, u16Src, 1); \
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| 53 | IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
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| 54 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 55 | IEM_MC_LOCAL(uint16_t, u16Dst); \
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| 56 | IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| 57 | /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \
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| 58 | IEM_MC_LOCAL(uint32_t, uEFlags); \
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| 59 | IEM_MC_FETCH_EFLAGS(uEFlags); \
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| 60 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
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| 61 | IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \
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| 62 | IEM_MC_COMMIT_EFLAGS(uEFlags); \
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| 63 | } IEM_MC_NATIVE_ELSE() { \
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| 64 | IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
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| 65 | IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| 66 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
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| 67 | IEM_MC_REF_EFLAGS(pEFlags); \
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| 68 | IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \
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| 69 | } IEM_MC_NATIVE_ENDIF(); \
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| 70 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 71 | IEM_MC_END(); \
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| 72 | break; \
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| 73 | \
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| 74 | case IEMMODE_32BIT: \
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| 75 | IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
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| 76 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| 77 | IEM_MC_ARG(uint32_t, u32Src, 1); \
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| 78 | IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
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| 79 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 80 | IEM_MC_LOCAL(uint32_t, u32Dst); \
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| 81 | IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| 82 | /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \
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| 83 | IEM_MC_LOCAL(uint32_t, uEFlags); \
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| 84 | IEM_MC_FETCH_EFLAGS(uEFlags); \
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| 85 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
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| 86 | IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \
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| 87 | IEM_MC_COMMIT_EFLAGS(uEFlags); \
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| 88 | } IEM_MC_NATIVE_ELSE() { \
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| 89 | IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
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| 90 | IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| 91 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
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| 92 | IEM_MC_REF_EFLAGS(pEFlags); \
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| 93 | IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \
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| 94 | if (a_fModifiesDstReg) \
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| 95 | IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
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| 96 | } IEM_MC_NATIVE_ENDIF(); \
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| 97 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 98 | IEM_MC_END(); \
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| 99 | break; \
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| 100 | \
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| 101 | case IEMMODE_64BIT: \
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| 102 | IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
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| 103 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| 104 | IEM_MC_ARG(uint64_t, u64Src, 1); \
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| 105 | IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
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| 106 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 107 | IEM_MC_LOCAL(uint64_t, u64Dst); \
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| 108 | IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| 109 | /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \
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| 110 | IEM_MC_LOCAL(uint32_t, uEFlags); \
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| 111 | IEM_MC_FETCH_EFLAGS(uEFlags); \
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| 112 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
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| 113 | IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \
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| 114 | IEM_MC_COMMIT_EFLAGS(uEFlags); \
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| 115 | } IEM_MC_NATIVE_ELSE() { \
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| 116 | IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
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| 117 | IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| 118 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
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| 119 | IEM_MC_REF_EFLAGS(pEFlags); \
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| 120 | IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \
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| 121 | } IEM_MC_NATIVE_ENDIF(); \
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| 122 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 123 | IEM_MC_END(); \
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| 124 | break; \
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| 125 | \
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| 126 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
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| 127 | } \
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| 128 | } \
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| 129 | else \
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| 130 | { \
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| 131 | /* \
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| 132 | * We're accessing memory. \
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| 133 | */ \
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| 134 | switch (pVCpu->iem.s.enmEffOpSize) \
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| 135 | { \
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| 136 | case IEMMODE_16BIT: \
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| 137 | IEM_MC_BEGIN(3, 1, a_f16BitMcFlag, 0); \
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| 138 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
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| 139 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
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| 140 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| 141 | IEM_MC_ARG(uint16_t, u16Src, 1); \
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| 142 | IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
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| 143 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 144 | IEM_MC_LOCAL(uint16_t, u16Dst); \
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| 145 | IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| 146 | /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \
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| 147 | IEM_MC_LOCAL(uint32_t, uEFlags); \
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| 148 | IEM_MC_FETCH_EFLAGS(uEFlags); \
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| 149 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
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| 150 | IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \
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| 151 | IEM_MC_COMMIT_EFLAGS(uEFlags); \
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| 152 | } IEM_MC_NATIVE_ELSE() { \
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| 153 | IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
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| 154 | IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
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| 155 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
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| 156 | IEM_MC_REF_EFLAGS(pEFlags); \
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| 157 | IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \
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| 158 | } IEM_MC_NATIVE_ENDIF(); \
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| 159 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 160 | IEM_MC_END(); \
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| 161 | break; \
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| 162 | \
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| 163 | case IEMMODE_32BIT: \
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| 164 | IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386, 0); \
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| 165 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
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| 166 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
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| 167 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| 168 | IEM_MC_ARG(uint32_t, u32Src, 1); \
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| 169 | IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
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| 170 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 171 | IEM_MC_LOCAL(uint32_t, u32Dst); \
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| 172 | IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| 173 | /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \
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| 174 | IEM_MC_LOCAL(uint32_t, uEFlags); \
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| 175 | IEM_MC_FETCH_EFLAGS(uEFlags); \
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| 176 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
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| 177 | IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \
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| 178 | IEM_MC_COMMIT_EFLAGS(uEFlags); \
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| 179 | } IEM_MC_NATIVE_ELSE() { \
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| 180 | IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
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| 181 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
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| 182 | IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
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| 183 | IEM_MC_REF_EFLAGS(pEFlags); \
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| 184 | IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \
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| 185 | if (a_fModifiesDstReg) \
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| 186 | IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
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| 187 | } IEM_MC_NATIVE_ENDIF(); \
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| 188 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 189 | IEM_MC_END(); \
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| 190 | break; \
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| 191 | \
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| 192 | case IEMMODE_64BIT: \
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| 193 | IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0); \
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| 194 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
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| 195 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
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| 196 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
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| 197 | IEM_MC_ARG(uint64_t, u64Src, 1); \
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| 198 | IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
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| 199 | IEM_MC_NATIVE_IF(a_fNativeArchs) { \
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| 200 | IEM_MC_LOCAL(uint64_t, u64Dst); \
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| 201 | IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
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| 202 | /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \
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| 203 | IEM_MC_LOCAL(uint32_t, uEFlags); \
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| 204 | IEM_MC_FETCH_EFLAGS(uEFlags); \
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| 205 | IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
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| 206 | IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \
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| 207 | IEM_MC_COMMIT_EFLAGS(uEFlags); \
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| 208 | } IEM_MC_NATIVE_ELSE() { \
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| 209 | IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
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| 210 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
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| 211 | IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
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| 212 | IEM_MC_REF_EFLAGS(pEFlags); \
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| 213 | IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \
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| 214 | } IEM_MC_NATIVE_ENDIF(); \
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| 215 | IEM_MC_ADVANCE_RIP_AND_FINISH(); \
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| 216 | IEM_MC_END(); \
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| 217 | break; \
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| 218 | \
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| 219 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
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| 220 | } \
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| 221 | } \
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| 222 | (void)0
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| 223 |
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