Changeset 12657 in vbox for trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp

Timestamp:

Sep 22, 2008 6:29:06 PM (16 years ago)

Author:

vboxsync

Message:

#1865: CPUM. Also added missing aliasing for DR4&5 to the guest DRx setter and getter.

File:

• trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp (modified) (15 diffs)

trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp

@@ -36 +36 @@
 
 
-
 /**
  * Does Ring-0 CPUM initialization.
@@ -53 +52 @@
      * Check CR0 & CR4 flags.
      */
-    uint32_t    u32CR0 = ASMGetCR0();
+    uint32_t u32CR0 = ASMGetCR0();
     if ((u32CR0 & (X86_CR0_PE | X86_CR0_PG)) != (X86_CR0_PE | X86_CR0_PG)) /* a bit paranoid perhaps.. */
     {
@@ -99 +98 @@
      * This ASSUMES that DR7.GD is not set, or that it's handled transparently!
      */
-    uint32_t    u32DR7 = ASMGetDR7();
+    uint32_t u32DR7 = ASMGetDR7();
     if (u32DR7 & X86_DR7_ENABLED_MASK)
     {
@@ -155 +154 @@
      */
 
-    switch(pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
-    {
-    case X86_CR0_MP | X86_CR0_TS:
-    case X86_CR0_MP | X86_CR0_EM | X86_CR0_TS:
-        return VINF_EM_RAW_GUEST_TRAP;
-
-    default:
-        break;
+    switch (pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
+    {
+        case X86_CR0_MP | X86_CR0_TS:
+        case X86_CR0_MP | X86_CR0_EM | X86_CR0_TS:
+            return VINF_EM_RAW_GUEST_TRAP;
+        default:
+            break;
     }
 
@@ -172 +170 @@
     if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
     {
-        /* @todo Do we really need to read this every time?? The host could change this on the fly though. */
+        /** @todo Do we really need to read this every time?? The host could change this on the fly though.
+         *  bird: what about starting by skipping the ASMWrMsr below if we didn't
+         *        change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
         oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
-
         if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
         {
@@ -193 +192 @@
         /* CPUMHandleLazyFPU could have changed CR0; restore it. */
     ASMSetCR0(oldCR0);
-#else
-    /* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
+
+#else  /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
+
+    /*
+     * Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
      * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
      */
@@ -203 +205 @@
     CPUMLoadFPUAsm(pCtx);
 
-    /* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
+    /*
+     * The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
      *
      * MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
@@ -209 +212 @@
     if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
     {
-        /* @todo Do we really need to read this every time?? The host could change this on the fly though. */
+        /** @todo Do we really need to read this every time?? The host could change this on the fly though. */
         uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
 
@@ -219 +222 @@
         }
     }
-#endif
+#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
 
     pVM->cpum.s.fUseFlags |= CPUM_USED_FPU;
@@ -254 +257 @@
         ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost | MSR_K6_EFER_FFXSR);
 
-#else
+#else  /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
     CPUMSaveFPUAsm(pCtx);
     if (pVM->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
@@ -261 +264 @@
         CPUMSaveXMMAsm(pCtx);
     }
-    /* Restore the original FPU control word and MXCSR.
+
+    /*
+     * Restore the original FPU control word and MXCSR.
      * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
      */
@@ -267 +272 @@
     if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
         CPUMSetMXCSR(pVM->cpum.s.Host.fpu.MXCSR);
-#endif
-
-    pVM->cpum.s.fUseFlags &= ~(CPUM_USED_FPU|CPUM_MANUAL_XMM_RESTORE);
+#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
+
+    pVM->cpum.s.fUseFlags &= ~(CPUM_USED_FPU | CPUM_MANUAL_XMM_RESTORE);
     return VINF_SUCCESS;
 }
@@ -294 +299 @@
         pCtx->dr[6] = ASMGetDR6();
 
-    /* Restore the host's debug state. DR0-3, DR6 and only then DR7! 
+    /*
+     * Restore the host's debug state. DR0-3, DR6 and only then DR7!
      * DR7 contains 0x400 right now.
      */
@@ -325 +331 @@
     pVM->cpum.s.Host.dr3 = ASMGetDR3();
     pVM->cpum.s.Host.dr6 = ASMGetDR6();
-    /* @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
+    /** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
     pVM->cpum.s.Host.dr7 = ASMGetDR7();
     /* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
@@ -341 +347 @@
     return VINF_SUCCESS;
 }
+