HMSVMR0.cpp@ 70000

Last change on this file since 70000 was 70000, checked in by vboxsync, 7 years ago
VMM: Nested Hw.virt: Make SVM intercept functions smarter. Avoids swapping of modified VMCB state in a lot of tricky to detect situations and makes it a lot cleaner that the VMCB is only finally restored before the #VMEXIT is done.
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File size: 295.5 KB

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1	/* $Id: HMSVMR0.cpp 70000 2017-12-08 05:57:18Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/gim.h>
33	#include <VBox/vmm/apic.h>
34	#include "HMInternal.h"
35	#include <VBox/vmm/vm.h>
36	#include "HMSVMR0.h"
37	#include "dtrace/VBoxVMM.h"
38
39	#define HMSVM_USE_IEM_EVENT_REFLECTION
40	#ifdef DEBUG_ramshankar
41	# define HMSVM_SYNC_FULL_GUEST_STATE
42	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
43	# define HMSVM_ALWAYS_TRAP_PF
44	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
45	#endif
46
47
48	/*********************************************************************************************************************************
49	* Defined Constants And Macros *
50	*********************************************************************************************************************************/
51	#ifdef VBOX_WITH_STATISTICS
52	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
53	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
54	if ((u64ExitCode) == SVM_EXIT_NPF) \
55	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
56	else \
57	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
58	} while (0)
59	#else
60	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
61	#endif
62
63	/** If we decide to use a function table approach this can be useful to
64	* switch to a "static DECLCALLBACK(int)". */
65	#define HMSVM_EXIT_DECL static int
66
67	/** Macro for checking and returning from the using function for
68	* \#VMEXIT intercepts that maybe caused during delivering of another
69	* event in the guest. */
70	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
71	do \
72	{ \
73	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
74	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* likely */ } \
75	else if (rc == VINF_HM_DOUBLE_FAULT) \
76	return VINF_SUCCESS; \
77	else \
78	return rc; \
79	} while (0)
80
81	/**
82	* Updates interrupt shadow for the current RIP.
83	*/
84	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
85	do { \
86	/* Update interrupt shadow. */ \
87	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
88	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
89	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
90	} while (0)
91
92	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
93	* instruction that exited. */
94	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
95	do { \
96	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
97	(a_rc) = VINF_EM_DBG_STEPPED; \
98	} while (0)
99
100	/** Assert that preemption is disabled or covered by thread-context hooks. */
101	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
102	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
103
104	/** Assert that we haven't migrated CPUs when thread-context hooks are not
105	* used. */
106	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
107	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
108	("Illegal migration! Entered on CPU %u Current %u\n", \
109	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
110
111	/** Assert that we're not executing a nested-guest. */
112	#ifdef VBOX_WITH_NESTED_HWVIRT
113	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
114	#else
115	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
116	#endif
117
118	/** Assert that we're executing a nested-guest. */
119	#ifdef VBOX_WITH_NESTED_HWVIRT
120	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
121	#else
122	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
123	#endif
124
125	/**
126	* Exception bitmap mask for all contributory exceptions.
127	*
128	* Page fault is deliberately excluded here as it's conditional as to whether
129	* it's contributory or benign. Page faults are handled separately.
130	*/
131	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
132	\| RT_BIT(X86_XCPT_DE))
133
134	/**
135	* Mandatory/unconditional guest control intercepts.
136	*/
137	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
138	\| SVM_CTRL_INTERCEPT_NMI \
139	\| SVM_CTRL_INTERCEPT_INIT \
140	\| SVM_CTRL_INTERCEPT_RDPMC \
141	\| SVM_CTRL_INTERCEPT_CPUID \
142	\| SVM_CTRL_INTERCEPT_RSM \
143	\| SVM_CTRL_INTERCEPT_HLT \
144	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
145	\| SVM_CTRL_INTERCEPT_MSR_PROT \
146	\| SVM_CTRL_INTERCEPT_INVLPGA \
147	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
148	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
149	\| SVM_CTRL_INTERCEPT_VMRUN \
150	\| SVM_CTRL_INTERCEPT_VMMCALL \
151	\| SVM_CTRL_INTERCEPT_VMLOAD \
152	\| SVM_CTRL_INTERCEPT_VMSAVE \
153	\| SVM_CTRL_INTERCEPT_STGI \
154	\| SVM_CTRL_INTERCEPT_CLGI \
155	\| SVM_CTRL_INTERCEPT_SKINIT \
156	\| SVM_CTRL_INTERCEPT_WBINVD \
157	\| SVM_CTRL_INTERCEPT_MONITOR \
158	\| SVM_CTRL_INTERCEPT_MWAIT \
159	\| SVM_CTRL_INTERCEPT_XSETBV)
160
161	/**
162	* Mandatory/unconditional nested-guest control intercepts.
163	*/
164	#define HMSVM_MANDATORY_NESTED_GUEST_CTRL_INTERCEPTS ( HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS \
165	\| SVM_CTRL_INTERCEPT_SMI)
166
167	/** @name VMCB Clean Bits.
168	*
169	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
170	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
171	* memory.
172	*
173	* @{ */
174	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
175	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
176	/** I/O permission bitmap, MSR permission bitmap. */
177	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
178	/** ASID. */
179	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
180	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
181	V_INTR_VECTOR. */
182	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
183	/** Nested Paging: Nested CR3 (nCR3), PAT. */
184	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
185	/** Control registers (CR0, CR3, CR4, EFER). */
186	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
187	/** Debug registers (DR6, DR7). */
188	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
189	/** GDT, IDT limit and base. */
190	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
191	/** Segment register: CS, SS, DS, ES limit and base. */
192	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
193	/** CR2.*/
194	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
195	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
196	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
197	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
198	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
199	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
200	/** Mask of all valid VMCB Clean bits. */
201	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
202	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
203	\| HMSVM_VMCB_CLEAN_ASID \
204	\| HMSVM_VMCB_CLEAN_TPR \
205	\| HMSVM_VMCB_CLEAN_NP \
206	\| HMSVM_VMCB_CLEAN_CRX_EFER \
207	\| HMSVM_VMCB_CLEAN_DRX \
208	\| HMSVM_VMCB_CLEAN_DT \
209	\| HMSVM_VMCB_CLEAN_SEG \
210	\| HMSVM_VMCB_CLEAN_CR2 \
211	\| HMSVM_VMCB_CLEAN_LBR \
212	\| HMSVM_VMCB_CLEAN_AVIC)
213	/** @} */
214
215	/** @name SVM transient.
216	*
217	* A state structure for holding miscellaneous information across AMD-V
218	* VMRUN/\#VMEXIT operation, restored after the transition.
219	*
220	* @{ */
221	typedef struct SVMTRANSIENT
222	{
223	/** The host's rflags/eflags. */
224	RTCCUINTREG fEFlags;
225	#if HC_ARCH_BITS == 32
226	uint32_t u32Alignment0;
227	#endif
228
229	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
230	uint64_t u64ExitCode;
231	/** The guest's TPR value used for TPR shadowing. */
232	uint8_t u8GuestTpr;
233	/** Alignment. */
234	uint8_t abAlignment0[7];
235
236	/** Whether the guest FPU state was active at the time of \#VMEXIT. */
237	bool fWasGuestFPUStateActive;
238	/** Whether the guest debug state was active at the time of \#VMEXIT. */
239	bool fWasGuestDebugStateActive;
240	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
241	bool fWasHyperDebugStateActive;
242	/** Whether the TSC offset mode needs to be updated. */
243	bool fUpdateTscOffsetting;
244	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
245	bool fRestoreTscAuxMsr;
246	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
247	* contributary exception or a page-fault. */
248	bool fVectoringDoublePF;
249	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
250	* external interrupt or NMI. */
251	bool fVectoringPF;
252	} SVMTRANSIENT, *PSVMTRANSIENT;
253	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
254	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
255	/** @} */
256
257	/**
258	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
259	*/
260	typedef enum SVMMSREXITREAD
261	{
262	/** Reading this MSR causes a \#VMEXIT. */
263	SVMMSREXIT_INTERCEPT_READ = 0xb,
264	/** Reading this MSR does not cause a \#VMEXIT. */
265	SVMMSREXIT_PASSTHRU_READ
266	} SVMMSREXITREAD;
267
268	/**
269	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
270	*/
271	typedef enum SVMMSREXITWRITE
272	{
273	/** Writing to this MSR causes a \#VMEXIT. */
274	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
275	/** Writing to this MSR does not cause a \#VMEXIT. */
276	SVMMSREXIT_PASSTHRU_WRITE
277	} SVMMSREXITWRITE;
278
279	/**
280	* SVM \#VMEXIT handler.
281	*
282	* @returns VBox status code.
283	* @param pVCpu The cross context virtual CPU structure.
284	* @param pMixedCtx Pointer to the guest-CPU context.
285	* @param pSvmTransient Pointer to the SVM-transient structure.
286	*/
287	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
288
289
290	/*********************************************************************************************************************************
291	* Internal Functions *
292	*********************************************************************************************************************************/
293	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
294	SVMMSREXITWRITE enmWrite);
295	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
296	static void hmR0SvmLeave(PVMCPU pVCpu);
297
298	/** @name \#VMEXIT handlers.
299	* @{
300	*/
301	static FNSVMEXITHANDLER hmR0SvmExitIntr;
302	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
303	static FNSVMEXITHANDLER hmR0SvmExitInvd;
304	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
305	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
306	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
307	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
308	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
309	static FNSVMEXITHANDLER hmR0SvmExitHlt;
310	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
311	static FNSVMEXITHANDLER hmR0SvmExitMwait;
312	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
313	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
314	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
315	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
316	static FNSVMEXITHANDLER hmR0SvmExitMsr;
317	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
318	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
319	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
320	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
321	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
322	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
323	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
324	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
325	static FNSVMEXITHANDLER hmR0SvmExitPause;
326	static FNSVMEXITHANDLER hmR0SvmExitIret;
327	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
328	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
329	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
330	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
331	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
332	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
333	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
334	#ifdef VBOX_WITH_NESTED_HWVIRT
335	static FNSVMEXITHANDLER hmR0SvmExitXcptPFNested;
336	static FNSVMEXITHANDLER hmR0SvmExitClgi;
337	static FNSVMEXITHANDLER hmR0SvmExitStgi;
338	static FNSVMEXITHANDLER hmR0SvmExitVmload;
339	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
340	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
341	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
342	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
343	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
344	#endif
345	/** @} */
346
347	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
348	#ifdef VBOX_WITH_NESTED_HWVIRT
349	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
350	#endif
351
352
353	/*********************************************************************************************************************************
354	* Global Variables *
355	*********************************************************************************************************************************/
356	/** Ring-0 memory object for the IO bitmap. */
357	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
358	/** Physical address of the IO bitmap. */
359	RTHCPHYS g_HCPhysIOBitmap = 0;
360	/** Pointer to the IO bitmap. */
361	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
362
363	#ifdef VBOX_WITH_NESTED_HWVIRT
364	/** Ring-0 memory object for the nested-guest MSRPM bitmap. */
365	RTR0MEMOBJ g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
366	/** Physical address of the nested-guest MSRPM bitmap. */
367	RTHCPHYS g_HCPhysNstGstMsrBitmap = 0;
368	/** Pointer to the nested-guest MSRPM bitmap. */
369	R0PTRTYPE(void *) g_pvNstGstMsrBitmap = NULL;
370	#endif
371
372	/**
373	* Sets up and activates AMD-V on the current CPU.
374	*
375	* @returns VBox status code.
376	* @param pCpu Pointer to the CPU info struct.
377	* @param pVM The cross context VM structure. Can be
378	* NULL after a resume!
379	* @param pvCpuPage Pointer to the global CPU page.
380	* @param HCPhysCpuPage Physical address of the global CPU page.
381	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
382	* @param pvArg Unused on AMD-V.
383	*/
384	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
385	void *pvArg)
386	{
387	Assert(!fEnabledByHost);
388	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
389	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
390	Assert(pvCpuPage); NOREF(pvCpuPage);
391	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
392
393	NOREF(pvArg);
394	NOREF(fEnabledByHost);
395
396	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
397	RTCCUINTREG fEFlags = ASMIntDisableFlags();
398
399	/*
400	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
401	*/
402	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
403	if (u64HostEfer & MSR_K6_EFER_SVME)
404	{
405	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
406	if ( pVM
407	&& pVM->hm.s.svm.fIgnoreInUseError)
408	{
409	pCpu->fIgnoreAMDVInUseError = true;
410	}
411
412	if (!pCpu->fIgnoreAMDVInUseError)
413	{
414	ASMSetFlags(fEFlags);
415	return VERR_SVM_IN_USE;
416	}
417	}
418
419	/* Turn on AMD-V in the EFER MSR. */
420	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
421
422	/* Write the physical page address where the CPU will store the host state while executing the VM. */
423	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
424
425	/* Restore interrupts. */
426	ASMSetFlags(fEFlags);
427
428	/*
429	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
430	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
431	* upon VMRUN). Therefore, flag that we need to flush the TLB entirely with before executing any
432	* guest code.
433	*/
434	pCpu->fFlushAsidBeforeUse = true;
435
436	/*
437	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
438	*/
439	++pCpu->cTlbFlushes;
440
441	return VINF_SUCCESS;
442	}
443
444
445	/**
446	* Deactivates AMD-V on the current CPU.
447	*
448	* @returns VBox status code.
449	* @param pCpu Pointer to the CPU info struct.
450	* @param pvCpuPage Pointer to the global CPU page.
451	* @param HCPhysCpuPage Physical address of the global CPU page.
452	*/
453	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
454	{
455	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
456	AssertReturn( HCPhysCpuPage
457	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
458	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
459	NOREF(pCpu);
460
461	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
462	RTCCUINTREG fEFlags = ASMIntDisableFlags();
463
464	/* Turn off AMD-V in the EFER MSR. */
465	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
466	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
467
468	/* Invalidate host state physical address. */
469	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
470
471	/* Restore interrupts. */
472	ASMSetFlags(fEFlags);
473
474	return VINF_SUCCESS;
475	}
476
477
478	/**
479	* Does global AMD-V initialization (called during module initialization).
480	*
481	* @returns VBox status code.
482	*/
483	VMMR0DECL(int) SVMR0GlobalInit(void)
484	{
485	/*
486	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
487	* once globally here instead of per-VM.
488	*/
489	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
490	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
491	if (RT_FAILURE(rc))
492	return rc;
493
494	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
495	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
496
497	/* Set all bits to intercept all IO accesses. */
498	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
499
500	#ifdef VBOX_WITH_NESTED_HWVIRT
501	/*
502	* Allocate 8 KB for the MSR permission bitmap for the nested-guest.
503	*/
504	Assert(g_hMemObjNstGstMsrBitmap == NIL_RTR0MEMOBJ);
505	rc = RTR0MemObjAllocCont(&g_hMemObjNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
506	if (RT_FAILURE(rc))
507	return rc;
508
509	g_pvNstGstMsrBitmap = RTR0MemObjAddress(g_hMemObjNstGstMsrBitmap);
510	g_HCPhysNstGstMsrBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjNstGstMsrBitmap, 0 /* iPage */);
511
512	/* Set all bits to intercept all MSR accesses. */
513	ASMMemFill32(g_pvNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
514	#endif
515
516	return VINF_SUCCESS;
517	}
518
519
520	/**
521	* Does global AMD-V termination (called during module termination).
522	*/
523	VMMR0DECL(void) SVMR0GlobalTerm(void)
524	{
525	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
526	{
527	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
528	g_pvIOBitmap = NULL;
529	g_HCPhysIOBitmap = 0;
530	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
531	}
532
533	#ifdef VBOX_WITH_NESTED_HWVIRT
534	if (g_hMemObjNstGstMsrBitmap != NIL_RTR0MEMOBJ)
535	{
536	RTR0MemObjFree(g_hMemObjNstGstMsrBitmap, true /* fFreeMappings */);
537	g_pvNstGstMsrBitmap = NULL;
538	g_HCPhysNstGstMsrBitmap = 0;
539	g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
540	}
541	#endif
542	}
543
544
545	/**
546	* Frees any allocated per-VCPU structures for a VM.
547	*
548	* @param pVM The cross context VM structure.
549	*/
550	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
551	{
552	for (uint32_t i = 0; i < pVM->cCpus; i++)
553	{
554	PVMCPU pVCpu = &pVM->aCpus[i];
555	AssertPtr(pVCpu);
556
557	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
558	{
559	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
560	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
561	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
562	}
563
564	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
565	{
566	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
567	pVCpu->hm.s.svm.pVmcb = NULL;
568	pVCpu->hm.s.svm.HCPhysVmcb = 0;
569	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
570	}
571
572	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
573	{
574	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
575	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
576	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
577	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
578	}
579	}
580	}
581
582
583	/**
584	* Does per-VM AMD-V initialization.
585	*
586	* @returns VBox status code.
587	* @param pVM The cross context VM structure.
588	*/
589	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
590	{
591	int rc = VERR_INTERNAL_ERROR_5;
592
593	/*
594	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
595	*/
596	uint32_t u32Family;
597	uint32_t u32Model;
598	uint32_t u32Stepping;
599	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
600	{
601	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
602	pVM->hm.s.svm.fAlwaysFlushTLB = true;
603	}
604
605	/*
606	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
607	*/
608	for (VMCPUID i = 0; i < pVM->cCpus; i++)
609	{
610	PVMCPU pVCpu = &pVM->aCpus[i];
611	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
612	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
613	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
614	}
615
616	for (VMCPUID i = 0; i < pVM->cCpus; i++)
617	{
618	PVMCPU pVCpu = &pVM->aCpus[i];
619
620	/*
621	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
622	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
623	*/
624	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
625	if (RT_FAILURE(rc))
626	goto failure_cleanup;
627
628	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
629	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
630	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
631	ASMMemZeroPage(pvVmcbHost);
632
633	/*
634	* Allocate one page for the guest-state VMCB.
635	*/
636	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
637	if (RT_FAILURE(rc))
638	goto failure_cleanup;
639
640	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
641	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
642	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
643	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
644
645	/*
646	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
647	* SVM to not require one.
648	*/
649	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
650	false /* fExecutable */);
651	if (RT_FAILURE(rc))
652	goto failure_cleanup;
653
654	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
655	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
656	/* Set all bits to intercept all MSR accesses (changed later on). */
657	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
658	}
659
660	return VINF_SUCCESS;
661
662	failure_cleanup:
663	hmR0SvmFreeStructs(pVM);
664	return rc;
665	}
666
667
668	/**
669	* Does per-VM AMD-V termination.
670	*
671	* @returns VBox status code.
672	* @param pVM The cross context VM structure.
673	*/
674	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
675	{
676	hmR0SvmFreeStructs(pVM);
677	return VINF_SUCCESS;
678	}
679
680
681	/**
682	* Returns whether VMCB Clean Bits feature is supported.
683	*
684	* @param pVCpu The cross context virtual CPU structure.
685	* @param pCtx Pointer to the guest-CPU context.
686	*/
687	DECLINLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPU pVCpu, PCPUMCTX pCtx)
688	{
689	PVM pVM = pVCpu->CTX_SUFF(pVM);
690	#ifdef VBOX_WITH_NESTED_HWVIRT
691	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
692	{
693	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
694	&& pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
695	}
696	#else
697	RT_NOREF(pCtx);
698	#endif
699	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
700	}
701
702
703	/**
704	* Returns whether decode-assist feature is supported.
705	*
706	* @param pVCpu The cross context virtual CPU structure.
707	* @param pCtx Pointer to the guest-CPU context.
708	*/
709	DECLINLINE(bool) hmR0SvmSupportsDecodeAssist(PVMCPU pVCpu, PCPUMCTX pCtx)
710	{
711	PVM pVM = pVCpu->CTX_SUFF(pVM);
712	#ifdef VBOX_WITH_NESTED_HWVIRT
713	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
714	{
715	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
716	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssist;
717	}
718	#else
719	RT_NOREF(pCtx);
720	#endif
721	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST);
722	}
723
724
725	/**
726	* Returns whether NRIP_SAVE feature is supported.
727	*
728	* @param pVCpu The cross context virtual CPU structure.
729	* @param pCtx Pointer to the guest-CPU context.
730	*/
731	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPU pVCpu, PCPUMCTX pCtx)
732	{
733	PVM pVM = pVCpu->CTX_SUFF(pVM);
734	#ifdef VBOX_WITH_NESTED_HWVIRT
735	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
736	{
737	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
738	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
739	}
740	#else
741	RT_NOREF(pCtx);
742	#endif
743	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
744	}
745
746
747	/**
748	* Sets the permission bits for the specified MSR in the MSRPM.
749	*
750	* @param pVmcb Pointer to the VM control block.
751	* @param pbMsrBitmap Pointer to the MSR bitmap.
752	* @param uMsr The MSR for which the access permissions are being set.
753	* @param enmRead MSR read permissions.
754	* @param enmWrite MSR write permissions.
755	*/
756	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
757	SVMMSREXITWRITE enmWrite)
758	{
759	uint16_t offMsrpm;
760	uint32_t uMsrpmBit;
761	int rc = HMSvmGetMsrpmOffsetAndBit(uMsr, &offMsrpm, &uMsrpmBit);
762	AssertRC(rc);
763
764	Assert(uMsrpmBit < 0x3fff);
765	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
766
767	pbMsrBitmap += offMsrpm;
768	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
769	ASMBitSet(pbMsrBitmap, uMsrpmBit);
770	else
771	ASMBitClear(pbMsrBitmap, uMsrpmBit);
772
773	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
774	ASMBitSet(pbMsrBitmap, uMsrpmBit + 1);
775	else
776	ASMBitClear(pbMsrBitmap, uMsrpmBit + 1);
777
778	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
779	}
780
781
782	/**
783	* Sets up AMD-V for the specified VM.
784	* This function is only called once per-VM during initalization.
785	*
786	* @returns VBox status code.
787	* @param pVM The cross context VM structure.
788	*/
789	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
790	{
791	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
792	AssertReturn(pVM, VERR_INVALID_PARAMETER);
793	Assert(pVM->hm.s.svm.fSupported);
794
795	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
796	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
797	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter && pVM->hm.s.svm.cPauseFilterThresholdTicks;
798
799	for (VMCPUID i = 0; i < pVM->cCpus; i++)
800	{
801	PVMCPU pVCpu = &pVM->aCpus[i];
802	PSVMVMCB pVmcb = pVM->aCpus[i].hm.s.svm.pVmcb;
803
804	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
805
806	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
807	Assert(!pVCpu->hm.s.idxExitHistoryFree);
808	HMCPU_EXIT_HISTORY_RESET(pVCpu);
809
810	/* Always trap #AC for reasons of security. */
811	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
812
813	/* Always trap #DB for reasons of security. */
814	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
815
816	/* Trap exceptions unconditionally (debug purposes). */
817	#ifdef HMSVM_ALWAYS_TRAP_PF
818	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
819	#endif
820	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
821	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
822	pVmcb->ctrl.u32InterceptXcpt \|= 0
823	\| RT_BIT(X86_XCPT_BP)
824	\| RT_BIT(X86_XCPT_DE)
825	\| RT_BIT(X86_XCPT_NM)
826	\| RT_BIT(X86_XCPT_UD)
827	\| RT_BIT(X86_XCPT_NP)
828	\| RT_BIT(X86_XCPT_SS)
829	\| RT_BIT(X86_XCPT_GP)
830	\| RT_BIT(X86_XCPT_PF)
831	\| RT_BIT(X86_XCPT_MF)
832	;
833	#endif
834
835	/* Set up unconditional intercepts and conditions. */
836	pVmcb->ctrl.u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
837
838	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
839	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
840
841	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
842	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
843
844	/* Intercept all DRx reads and writes by default. Changed later on. */
845	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
846	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
847
848	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
849	pVmcb->ctrl.IntCtrl.n.u1VIntrMasking = 1;
850
851	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
852	and we currently deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
853	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
854
855	/* Set IO and MSR bitmap permission bitmap physical addresses. */
856	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
857	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
858
859	/* No LBR virtualization. */
860	pVmcb->ctrl.u64LBRVirt = 0;
861
862	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
863	pVmcb->ctrl.u64VmcbCleanBits = 0;
864
865	/* The host ASID MBZ, for the guest start with 1. */
866	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
867
868	/*
869	* Setup the PAT MSR (applicable for Nested Paging only).
870	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
871	* so choose type 6 for all PAT slots.
872	*/
873	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
874
875	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
876	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
877
878	/* Without Nested Paging, we need additionally intercepts. */
879	if (!pVM->hm.s.fNestedPaging)
880	{
881	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
882	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
883	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
884
885	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
886	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
887	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
888
889	/* Page faults must be intercepted to implement shadow paging. */
890	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
891	}
892
893	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
894	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
895	#endif
896
897	/* Apply the exceptions intercepts needed by the GIM provider. */
898	if (pVCpu->hm.s.fGIMTrapXcptUD)
899	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
900
901	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
902	if (fUsePauseFilter)
903	{
904	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
905	if (fPauseFilterThreshold)
906	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
907	}
908
909	/*
910	* The following MSRs are saved/restored automatically during the world-switch.
911	* Don't intercept guest read/write accesses to these MSRs.
912	*/
913	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
914	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
915	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
916	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
917	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
918	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
919	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
920	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
921	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
922	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
923	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
924	}
925
926	return VINF_SUCCESS;
927	}
928
929
930	/**
931	* Gets a pointer to the currently active guest or nested-guest VMCB.
932	*
933	* @returns Pointer to the current context VMCB.
934	* @param pVCpu The cross context virtual CPU structure.
935	* @param pCtx Pointer to the guest-CPU context.
936	*/
937	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
938	{
939	#ifdef VBOX_WITH_NESTED_HWVIRT
940	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
941	return pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
942	#else
943	RT_NOREF(pCtx);
944	#endif
945	return pVCpu->hm.s.svm.pVmcb;
946	}
947
948
949	/**
950	* Invalidates a guest page by guest virtual address.
951	*
952	* @returns VBox status code.
953	* @param pVM The cross context VM structure.
954	* @param pVCpu The cross context virtual CPU structure.
955	* @param GCVirt Guest virtual address of the page to invalidate.
956	*/
957	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
958	{
959	AssertReturn(pVM, VERR_INVALID_PARAMETER);
960	Assert(pVM->hm.s.svm.fSupported);
961
962	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
963
964	/* Skip it if a TLB flush is already pending. */
965	if (!fFlushPending)
966	{
967	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
968
969	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
970	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
971	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
972
973	#if HC_ARCH_BITS == 32
974	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
975	if (CPUMIsGuestInLongMode(pVCpu))
976	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
977	else
978	#endif
979	{
980	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
981	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
982	}
983	}
984	return VINF_SUCCESS;
985	}
986
987
988	/**
989	* Flushes the appropriate tagged-TLB entries.
990	*
991	* @param pVCpu The cross context virtual CPU structure.
992	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
993	* @param pVmcb Pointer to the VM control block.
994	*/
995	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
996	{
997	#ifndef VBOX_WITH_NESTED_HWVIRT
998	RT_NOREF(pCtx);
999	#endif
1000
1001	PVM pVM = pVCpu->CTX_SUFF(pVM);
1002	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
1003
1004	/*
1005	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
1006	* This can happen both for start & resume due to long jumps back to ring-3.
1007	*
1008	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no correlation
1009	* between it and the physical CPU.
1010	*
1011	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
1012	* so we cannot reuse the ASIDs without flushing.
1013	*/
1014	bool fNewAsid = false;
1015	Assert(pCpu->idCpu != NIL_RTCPUID);
1016	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1017	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes
1018	#ifdef VBOX_WITH_NESTED_HWVIRT
1019	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
1020	#endif
1021	)
1022	{
1023	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1024	pVCpu->hm.s.fForceTLBFlush = true;
1025	fNewAsid = true;
1026	}
1027
1028	/* Set TLB flush state as checked until we return from the world switch. */
1029	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1030
1031	/* Check for explicit TLB flushes. */
1032	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1033	{
1034	pVCpu->hm.s.fForceTLBFlush = true;
1035	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1036	}
1037
1038	/*
1039	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1040	* This Host CPU requirement takes precedence.
1041	*/
1042	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1043	{
1044	pCpu->uCurrentAsid = 1;
1045	pVCpu->hm.s.uCurrentAsid = 1;
1046	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1047	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1048
1049	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1050	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1051
1052	/* Keep track of last CPU ID even when flushing all the time. */
1053	if (fNewAsid)
1054	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1055	}
1056	else
1057	{
1058	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1059	if (pVCpu->hm.s.fForceTLBFlush)
1060	{
1061	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1062	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1063
1064	if (fNewAsid)
1065	{
1066	++pCpu->uCurrentAsid;
1067
1068	bool fHitASIDLimit = false;
1069	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1070	{
1071	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1072	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1073	fHitASIDLimit = true;
1074	}
1075
1076	if ( fHitASIDLimit
1077	\|\| pCpu->fFlushAsidBeforeUse)
1078	{
1079	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1080	pCpu->fFlushAsidBeforeUse = false;
1081	}
1082
1083	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
1084	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1085	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1086	}
1087	else
1088	{
1089	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1090	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1091	else
1092	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1093	}
1094
1095	pVCpu->hm.s.fForceTLBFlush = false;
1096	}
1097	}
1098
1099	/* Update VMCB with the ASID. */
1100	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1101	{
1102	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1103	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1104	}
1105
1106	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
1107	("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
1108	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
1109	("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1110	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1111	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
1112	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1113	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1114
1115	#ifdef VBOX_WITH_STATISTICS
1116	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1117	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1118	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1119	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1120	{
1121	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1122	}
1123	else
1124	{
1125	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1126	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1127	}
1128	#endif
1129	}
1130
1131
1132	/** @name 64-bit guest on 32-bit host OS helper functions.
1133	*
1134	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1135	* mode (code segment, paging). These wrappers/helpers perform the necessary
1136	* bits for the 32->64 switcher.
1137	*
1138	* @{ */
1139	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1140	/**
1141	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1142	*
1143	* @returns VBox status code.
1144	* @param HCPhysVmcbHost Physical address of host VMCB.
1145	* @param HCPhysVmcb Physical address of the VMCB.
1146	* @param pCtx Pointer to the guest-CPU context.
1147	* @param pVM The cross context VM structure.
1148	* @param pVCpu The cross context virtual CPU structure.
1149	*/
1150	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1151	{
1152	uint32_t aParam[8];
1153	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1154	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1155	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1156	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1157	aParam[4] = VM_RC_ADDR(pVM, pVM);
1158	aParam[5] = 0;
1159	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1160	aParam[7] = 0;
1161
1162	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1163	}
1164
1165
1166	/**
1167	* Executes the specified VMRUN handler in 64-bit mode.
1168	*
1169	* @returns VBox status code.
1170	* @param pVM The cross context VM structure.
1171	* @param pVCpu The cross context virtual CPU structure.
1172	* @param pCtx Pointer to the guest-CPU context.
1173	* @param enmOp The operation to perform.
1174	* @param cParams Number of parameters.
1175	* @param paParam Array of 32-bit parameters.
1176	*/
1177	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1178	uint32_t cParams, uint32_t *paParam)
1179	{
1180	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1181	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1182
1183	NOREF(pCtx);
1184
1185	/* Disable interrupts. */
1186	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1187
1188	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1189	RTCPUID idHostCpu = RTMpCpuId();
1190	CPUMR0SetLApic(pVCpu, idHostCpu);
1191	#endif
1192
1193	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1194	CPUMSetHyperEIP(pVCpu, enmOp);
1195	for (int i = (int)cParams - 1; i >= 0; i--)
1196	CPUMPushHyper(pVCpu, paParam[i]);
1197
1198	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1199	/* Call the switcher. */
1200	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1201	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1202
1203	/* Restore interrupts. */
1204	ASMSetFlags(uOldEFlags);
1205	return rc;
1206	}
1207
1208	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1209	/** @} */
1210
1211
1212	/**
1213	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1214	* the corresponding VMCB Clean bit.
1215	*
1216	* @param pVmcb Pointer to the VM control block.
1217	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1218	*/
1219	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1220	{
1221	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt)))
1222	{
1223	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(u32Xcpt);
1224	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1225	}
1226	}
1227
1228
1229	/**
1230	* Removes an exception from the intercept-exception bitmap in the VMCB and
1231	* updates the corresponding VMCB Clean bit.
1232	*
1233	* @param pVCpu The cross context virtual CPU structure.
1234	* @param pCtx Pointer to the guest-CPU context.
1235	* @param pVmcb Pointer to the VM control block.
1236	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1237	*
1238	* @remarks This takes into account if we're executing a nested-guest and only
1239	* removes the exception intercept if both the guest -and- nested-guest
1240	* are not intercepting it.
1241	*/
1242	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb, uint32_t u32Xcpt)
1243	{
1244	Assert(u32Xcpt != X86_XCPT_DB);
1245	Assert(u32Xcpt != X86_XCPT_AC);
1246	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1247	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt))
1248	{
1249	bool fRemoveXcpt = true;
1250	#ifdef VBOX_WITH_NESTED_HWVIRT
1251	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1252	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1253	{
1254	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
1255	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
1256	fRemoveXcpt = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(u32Xcpt));
1257	}
1258	#else
1259	RT_NOREF2(pVCpu, pCtx);
1260	#endif
1261	if (fRemoveXcpt)
1262	{
1263	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(u32Xcpt);
1264	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1265	}
1266	}
1267	#else
1268	RT_NOREF3(pVCpu, pCtx, pVmcb);
1269	#endif
1270	}
1271
1272
1273	/**
1274	* Loads the guest (or nested-guest) CR0 control register into the guest-state
1275	* area in the VMCB.
1276	*
1277	* Although the guest CR0 is a separate field in the VMCB we have to consider
1278	* the FPU state itself which is shared between the host and the guest.
1279	*
1280	* @returns VBox status code.
1281	* @param pVCpu The cross context virtual CPU structure.
1282	* @param pVmcb Pointer to the VM control block.
1283	* @param pCtx Pointer to the guest-CPU context.
1284	*
1285	* @remarks No-long-jump zone!!!
1286	*/
1287	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1288	{
1289	uint64_t u64GuestCR0 = pCtx->cr0;
1290
1291	/* Always enable caching. */
1292	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1293
1294	/*
1295	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1296	*/
1297	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1298	{
1299	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1300	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1301	}
1302
1303	/*
1304	* Guest FPU bits.
1305	*/
1306	bool fInterceptNM = false;
1307	bool fInterceptMF = false;
1308	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1309	if (CPUMIsGuestFPUStateActive(pVCpu))
1310	{
1311	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1312	if (!(pCtx->cr0 & X86_CR0_NE))
1313	{
1314	Log4(("hmR0SvmLoadSharedCR0: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1315	fInterceptMF = true;
1316	}
1317	}
1318	else
1319	{
1320	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1321	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1322	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1323	}
1324
1325	/*
1326	* Update the exception intercept bitmap.
1327	*/
1328	if (fInterceptNM)
1329	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1330	else
1331	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_NM);
1332
1333	if (fInterceptMF)
1334	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1335	else
1336	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_MF);
1337
1338	pVmcb->guest.u64CR0 = u64GuestCR0;
1339	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1340	}
1341
1342
1343	/**
1344	* Loads the guest/nested-guest control registers (CR2, CR3, CR4) into the VMCB.
1345	*
1346	* @returns VBox status code.
1347	* @param pVCpu The cross context virtual CPU structure.
1348	* @param pVmcb Pointer to the VM control block.
1349	* @param pCtx Pointer to the guest-CPU context.
1350	*
1351	* @remarks No-long-jump zone!!!
1352	*/
1353	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1354	{
1355	PVM pVM = pVCpu->CTX_SUFF(pVM);
1356
1357	/*
1358	* Guest CR2.
1359	*/
1360	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1361	{
1362	pVmcb->guest.u64CR2 = pCtx->cr2;
1363	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1364	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1365	}
1366
1367	/*
1368	* Guest CR3.
1369	*/
1370	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1371	{
1372	if (pVM->hm.s.fNestedPaging)
1373	{
1374	PGMMODE enmShwPagingMode;
1375	#if HC_ARCH_BITS == 32
1376	if (CPUMIsGuestInLongModeEx(pCtx))
1377	enmShwPagingMode = PGMMODE_AMD64_NX;
1378	else
1379	#endif
1380	enmShwPagingMode = PGMGetHostMode(pVM);
1381
1382	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1383	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1384	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1385	pVmcb->guest.u64CR3 = pCtx->cr3;
1386	}
1387	else
1388	{
1389	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1390	Log4(("hmR0SvmLoadGuestControlRegs: CR3=%#RX64 (HyperCR3=%#RX64)\n", pCtx->cr3, pVmcb->guest.u64CR3));
1391	}
1392
1393	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1394	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1395	}
1396
1397	/*
1398	* Guest CR4.
1399	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1400	*/
1401	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1402	{
1403	uint64_t u64GuestCR4 = pCtx->cr4;
1404	Assert(RT_HI_U32(u64GuestCR4) == 0);
1405	if (!pVM->hm.s.fNestedPaging)
1406	{
1407	switch (pVCpu->hm.s.enmShadowMode)
1408	{
1409	case PGMMODE_REAL:
1410	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1411	AssertFailed();
1412	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1413
1414	case PGMMODE_32_BIT: /* 32-bit paging. */
1415	u64GuestCR4 &= ~X86_CR4_PAE;
1416	break;
1417
1418	case PGMMODE_PAE: /* PAE paging. */
1419	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1420	/** Must use PAE paging as we could use physical memory > 4 GB */
1421	u64GuestCR4 \|= X86_CR4_PAE;
1422	break;
1423
1424	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1425	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1426	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1427	break;
1428	#else
1429	AssertFailed();
1430	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1431	#endif
1432
1433	default: /* shut up gcc */
1434	AssertFailed();
1435	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1436	}
1437	}
1438
1439	pVmcb->guest.u64CR4 = u64GuestCR4;
1440	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1441
1442	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1443	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1444
1445	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1446	}
1447
1448	return VINF_SUCCESS;
1449	}
1450
1451
1452	#ifdef VBOX_WITH_NESTED_HWVIRT
1453	/**
1454	* Loads the nested-guest control registers (CR0, CR2, CR3, CR4) into the VMCB.
1455	*
1456	* @returns VBox status code.
1457	* @param pVCpu The cross context virtual CPU structure.
1458	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1459	* @param pCtx Pointer to the guest-CPU context.
1460	*
1461	* @remarks No-long-jump zone!!!
1462	*/
1463	static int hmR0SvmLoadGuestControlRegsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst, PCPUMCTX pCtx)
1464	{
1465	/*
1466	* Guest CR0.
1467	*/
1468	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1469	{
1470	pVmcbNstGst->guest.u64CR0 = pCtx->cr0;
1471	pVmcbNstGst->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1472	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
1473	}
1474
1475	return hmR0SvmLoadGuestControlRegs(pVCpu, pVmcbNstGst, pCtx);
1476	}
1477	#endif
1478
1479
1480	/**
1481	* Loads the guest segment registers into the VMCB.
1482	*
1483	* @returns VBox status code.
1484	* @param pVCpu The cross context virtual CPU structure.
1485	* @param pVmcb Pointer to the VM control block.
1486	* @param pCtx Pointer to the guest-CPU context.
1487	*
1488	* @remarks No-long-jump zone!!!
1489	*/
1490	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1491	{
1492	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1493	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1494	{
1495	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1496	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1497	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1498	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1499	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1500	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1501
1502	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1503	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1504	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1505	}
1506
1507	/* Guest TR. */
1508	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1509	{
1510	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1511	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1512	}
1513
1514	/* Guest LDTR. */
1515	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1516	{
1517	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1518	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1519	}
1520
1521	/* Guest GDTR. */
1522	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1523	{
1524	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1525	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1526	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1527	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1528	}
1529
1530	/* Guest IDTR. */
1531	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1532	{
1533	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1534	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1535	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1536	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1537	}
1538	}
1539
1540
1541	/**
1542	* Loads the guest MSRs into the VMCB.
1543	*
1544	* @param pVCpu The cross context virtual CPU structure.
1545	* @param pVmcb Pointer to the VM control block.
1546	* @param pCtx Pointer to the guest-CPU context.
1547	*
1548	* @remarks No-long-jump zone!!!
1549	*/
1550	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1551	{
1552	/* Guest Sysenter MSRs. */
1553	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1554	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1555	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1556
1557	/*
1558	* Guest EFER MSR.
1559	* AMD-V requires guest EFER.SVME to be set. Weird.
1560	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1561	*/
1562	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1563	{
1564	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1565	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1566	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1567	}
1568
1569	/* 64-bit MSRs. */
1570	if (CPUMIsGuestInLongModeEx(pCtx))
1571	{
1572	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1573	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1574	}
1575	else
1576	{
1577	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1578	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1579	{
1580	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1581	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1582	}
1583	}
1584
1585	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1586	* be writable in 32-bit mode. Clarify with AMD spec. */
1587	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1588	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1589	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1590	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1591	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1592	}
1593
1594
1595	/**
1596	* Loads the guest (or nested-guest) debug state into the VMCB and programs the
1597	* necessary intercepts accordingly.
1598	*
1599	* @param pVCpu The cross context virtual CPU structure.
1600	* @param pVmcb Pointer to the VM control block.
1601	* @param pCtx Pointer to the guest-CPU context.
1602	*
1603	* @remarks No-long-jump zone!!!
1604	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1605	*/
1606	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1607	{
1608	bool fInterceptMovDRx = false;
1609
1610	/*
1611	* Anyone single stepping on the host side? If so, we'll have to use the
1612	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1613	* the VMM level like the VT-x implementations does.
1614	*/
1615	bool const fStepping = pVCpu->hm.s.fSingleInstruction;
1616	if (fStepping)
1617	{
1618	pVCpu->hm.s.fClearTrapFlag = true;
1619	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1620	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1621	}
1622	else
1623	Assert(!DBGFIsStepping(pVCpu));
1624
1625	if ( fStepping
1626	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1627	{
1628	/*
1629	* Use the combined guest and host DRx values found in the hypervisor
1630	* register set because the debugger has breakpoints active or someone
1631	* is single stepping on the host side.
1632	*
1633	* Note! DBGF expects a clean DR6 state before executing guest code.
1634	*/
1635	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1636	if ( CPUMIsGuestInLongModeEx(pCtx)
1637	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1638	{
1639	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1640	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1641	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1642	}
1643	else
1644	#endif
1645	if (!CPUMIsHyperDebugStateActive(pVCpu))
1646	{
1647	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1648	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1649	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1650	}
1651
1652	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1653	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1654	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1655	{
1656	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1657	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1658	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1659	pVCpu->hm.s.fUsingHyperDR7 = true;
1660	}
1661
1662	/** @todo If we cared, we could optimize to allow the guest to read registers
1663	* with the same values. */
1664	fInterceptMovDRx = true;
1665	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1666	}
1667	else
1668	{
1669	/*
1670	* Update DR6, DR7 with the guest values if necessary.
1671	*/
1672	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1673	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1674	{
1675	pVmcb->guest.u64DR7 = pCtx->dr[7];
1676	pVmcb->guest.u64DR6 = pCtx->dr[6];
1677	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1678	pVCpu->hm.s.fUsingHyperDR7 = false;
1679	}
1680
1681	/*
1682	* If the guest has enabled debug registers, we need to load them prior to
1683	* executing guest code so they'll trigger at the right time.
1684	*/
1685	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1686	{
1687	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1688	if ( CPUMIsGuestInLongModeEx(pCtx)
1689	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1690	{
1691	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1692	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1693	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1694	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1695	}
1696	else
1697	#endif
1698	if (!CPUMIsGuestDebugStateActive(pVCpu))
1699	{
1700	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1701	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1702	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1703	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1704	}
1705	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1706	}
1707	/*
1708	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1709	* intercept #DB as DR6 is updated in the VMCB.
1710	*
1711	* Note! If we cared and dared, we could skip intercepting \#DB here.
1712	* However, \#DB shouldn't be performance critical, so we'll play safe
1713	* and keep the code similar to the VT-x code and always intercept it.
1714	*/
1715	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1716	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1717	&& !CPUMIsGuestDebugStateActive(pVCpu))
1718	#else
1719	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1720	#endif
1721	{
1722	fInterceptMovDRx = true;
1723	}
1724	}
1725
1726	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1727	if (fInterceptMovDRx)
1728	{
1729	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1730	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1731	{
1732	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1733	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1734	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1735	}
1736	}
1737	else
1738	{
1739	if ( pVmcb->ctrl.u16InterceptRdDRx
1740	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1741	{
1742	pVmcb->ctrl.u16InterceptRdDRx = 0;
1743	pVmcb->ctrl.u16InterceptWrDRx = 0;
1744	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1745	}
1746	}
1747	Log4(("hmR0SvmLoadSharedDebugState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1748	}
1749
1750
1751	#ifdef VBOX_WITH_NESTED_HWVIRT
1752	/**
1753	* Loads the nested-guest APIC state (currently just the TPR).
1754	*
1755	* @param pVCpu The cross context virtual CPU structure.
1756	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1757	*/
1758	static void hmR0SvmLoadGuestApicStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1759	{
1760	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1761	{
1762	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
1763	pVmcbNstGst->ctrl.IntCtrl.n.u1VIntrMasking = 1;
1764	pVCpu->hm.s.svm.fSyncVTpr = false;
1765	pVmcbNstGst->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_TPR;
1766
1767	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1768	}
1769	}
1770	#endif
1771
1772	/**
1773	* Loads the guest APIC state (currently just the TPR).
1774	*
1775	* @returns VBox status code.
1776	* @param pVCpu The cross context virtual CPU structure.
1777	* @param pVmcb Pointer to the VM control block.
1778	* @param pCtx Pointer to the guest-CPU context.
1779	*/
1780	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1781	{
1782	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1783	return VINF_SUCCESS;
1784
1785	int rc = VINF_SUCCESS;
1786	PVM pVM = pVCpu->CTX_SUFF(pVM);
1787	if ( PDMHasApic(pVM)
1788	&& APICIsEnabled(pVCpu))
1789	{
1790	bool fPendingIntr;
1791	uint8_t u8Tpr;
1792	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1793	AssertRCReturn(rc, rc);
1794
1795	/* Assume that we need to trap all TPR accesses and thus need not check on
1796	every #VMEXIT if we should update the TPR. */
1797	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
1798	pVCpu->hm.s.svm.fSyncVTpr = false;
1799
1800	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1801	if (pVM->hm.s.fTPRPatchingActive)
1802	{
1803	pCtx->msrLSTAR = u8Tpr;
1804	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1805
1806	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1807	if (fPendingIntr)
1808	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1809	else
1810	{
1811	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1812	pVCpu->hm.s.svm.fSyncVTpr = true;
1813	}
1814	}
1815	else
1816	{
1817	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1818	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1819
1820	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1821	if (fPendingIntr)
1822	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1823	else
1824	{
1825	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1826	pVCpu->hm.s.svm.fSyncVTpr = true;
1827	}
1828
1829	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1830	}
1831	}
1832
1833	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1834	return rc;
1835	}
1836
1837
1838	/**
1839	* Loads the exception interrupts required for guest (or nested-guest) execution in
1840	* the VMCB.
1841	*
1842	* @param pVCpu The cross context virtual CPU structure.
1843	* @param pVmcb Pointer to the VM control block.
1844	* @param pCtx Pointer to the guest-CPU context.
1845	*/
1846	static void hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1847	{
1848	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1849	{
1850	/* Trap #UD for GIM provider (e.g. for hypercalls). */
1851	if (pVCpu->hm.s.fGIMTrapXcptUD)
1852	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1853	else
1854	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_UD);
1855
1856	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
1857	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
1858	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_BP);
1859	else
1860	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_BP);
1861
1862	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1863	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1864	}
1865	}
1866
1867
1868	#ifdef VBOX_WITH_NESTED_HWVIRT
1869	/**
1870	* Loads the intercepts required for nested-guest execution in the VMCB.
1871	*
1872	* This merges the guest and nested-guest intercepts in a way that if the outer
1873	* guest intercepts an exception we need to intercept it in the nested-guest as
1874	* well and handle it accordingly.
1875	*
1876	* @param pVCpu The cross context virtual CPU structure.
1877	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1878	* @param pCtx Pointer to the guest-CPU context.
1879	*/
1880	static void hmR0SvmLoadGuestXcptInterceptsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst, PCPUMCTX pCtx)
1881	{
1882	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1883	{
1884	/* First, load the guest intercepts into the guest VMCB. */
1885	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
1886	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
1887
1888	/* Next, merge the intercepts into the nested-guest VMCB. */
1889	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
1890	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
1891
1892	/* Always intercept CR0, CR4 reads and writes as we alter them. */
1893	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(0) \| RT_BIT(4);
1894	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(0) \| RT_BIT(4);
1895
1896	/* Always intercept CR3 reads and writes without nested-paging as we load shadow page tables. */
1897	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1898	{
1899	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
1900	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
1901	}
1902
1903	/** @todo Figure out debugging with nested-guests, till then just intercept
1904	* all DR[0-15] accesses. */
1905	pVmcbNstGst->ctrl.u16InterceptRdDRx \|= 0xffff;
1906	pVmcbNstGst->ctrl.u16InterceptWrDRx \|= 0xffff;
1907
1908	pVmcbNstGst->ctrl.u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
1909	pVmcbNstGst->ctrl.u64InterceptCtrl \|= pVmcb->ctrl.u64InterceptCtrl
1910	\| HMSVM_MANDATORY_NESTED_GUEST_CTRL_INTERCEPTS;
1911
1912	/*
1913	* Remove control intercepts that we don't need while executing the nested-guest.
1914	*
1915	* VMMCALL when not intercepted raises a \#UD exception in the guest. However,
1916	* other SVM instructions like VMSAVE when not intercept can cause havoc on the
1917	* host as they can write to any location in physical memory, hence they always
1918	* need to be intercepted (they are included in HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS).
1919	*/
1920	Assert( (pVmcbNstGst->ctrl.u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
1921	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
1922	pVmcbNstGst->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VMMCALL;
1923
1924	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS));
1925	}
1926	}
1927	#endif
1928
1929
1930	/**
1931	* Sets up the appropriate function to run guest code.
1932	*
1933	* @returns VBox status code.
1934	* @param pVCpu The cross context virtual CPU structure.
1935	*
1936	* @remarks No-long-jump zone!!!
1937	*/
1938	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu)
1939	{
1940	if (CPUMIsGuestInLongMode(pVCpu))
1941	{
1942	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1943	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1944	#endif
1945	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1946	#if HC_ARCH_BITS == 32
1947	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1948	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1949	#else
1950	/* 64-bit host or hybrid host. */
1951	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1952	#endif
1953	}
1954	else
1955	{
1956	/* Guest is not in long mode, use the 32-bit handler. */
1957	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1958	}
1959	return VINF_SUCCESS;
1960	}
1961
1962
1963	/**
1964	* Enters the AMD-V session.
1965	*
1966	* @returns VBox status code.
1967	* @param pVM The cross context VM structure.
1968	* @param pVCpu The cross context virtual CPU structure.
1969	* @param pCpu Pointer to the CPU info struct.
1970	*/
1971	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1972	{
1973	AssertPtr(pVM);
1974	AssertPtr(pVCpu);
1975	Assert(pVM->hm.s.svm.fSupported);
1976	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1977	NOREF(pVM); NOREF(pCpu);
1978
1979	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1980	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1981
1982	pVCpu->hm.s.fLeaveDone = false;
1983	return VINF_SUCCESS;
1984	}
1985
1986
1987	/**
1988	* Thread-context callback for AMD-V.
1989	*
1990	* @param enmEvent The thread-context event.
1991	* @param pVCpu The cross context virtual CPU structure.
1992	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1993	* @thread EMT(pVCpu)
1994	*/
1995	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1996	{
1997	NOREF(fGlobalInit);
1998
1999	switch (enmEvent)
2000	{
2001	case RTTHREADCTXEVENT_OUT:
2002	{
2003	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2004	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2005	VMCPU_ASSERT_EMT(pVCpu);
2006
2007	/* No longjmps (log-flush, locks) in this fragile context. */
2008	VMMRZCallRing3Disable(pVCpu);
2009
2010	if (!pVCpu->hm.s.fLeaveDone)
2011	{
2012	hmR0SvmLeave(pVCpu);
2013	pVCpu->hm.s.fLeaveDone = true;
2014	}
2015
2016	/* Leave HM context, takes care of local init (term). */
2017	int rc = HMR0LeaveCpu(pVCpu);
2018	AssertRC(rc); NOREF(rc);
2019
2020	/* Restore longjmp state. */
2021	VMMRZCallRing3Enable(pVCpu);
2022	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2023	break;
2024	}
2025
2026	case RTTHREADCTXEVENT_IN:
2027	{
2028	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2029	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2030	VMCPU_ASSERT_EMT(pVCpu);
2031
2032	/* No longjmps (log-flush, locks) in this fragile context. */
2033	VMMRZCallRing3Disable(pVCpu);
2034
2035	/*
2036	* Initialize the bare minimum state required for HM. This takes care of
2037	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2038	*/
2039	int rc = HMR0EnterCpu(pVCpu);
2040	AssertRC(rc); NOREF(rc);
2041	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
2042
2043	pVCpu->hm.s.fLeaveDone = false;
2044
2045	/* Restore longjmp state. */
2046	VMMRZCallRing3Enable(pVCpu);
2047	break;
2048	}
2049
2050	default:
2051	break;
2052	}
2053	}
2054
2055
2056	/**
2057	* Saves the host state.
2058	*
2059	* @returns VBox status code.
2060	* @param pVM The cross context VM structure.
2061	* @param pVCpu The cross context virtual CPU structure.
2062	*
2063	* @remarks No-long-jump zone!!!
2064	*/
2065	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
2066	{
2067	NOREF(pVM);
2068	NOREF(pVCpu);
2069	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2070	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
2071	return VINF_SUCCESS;
2072	}
2073
2074
2075	/**
2076	* Loads the guest state into the VMCB.
2077	*
2078	* The CPU state will be loaded from these fields on every successful VM-entry.
2079	* Also sets up the appropriate VMRUN function to execute guest code based on
2080	* the guest CPU mode.
2081	*
2082	* @returns VBox status code.
2083	* @param pVM The cross context VM structure.
2084	* @param pVCpu The cross context virtual CPU structure.
2085	* @param pCtx Pointer to the guest-CPU context.
2086	*
2087	* @remarks No-long-jump zone!!!
2088	*/
2089	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2090	{
2091	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
2092
2093	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2094	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
2095
2096	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2097
2098	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
2099	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2100
2101	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
2102	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
2103
2104	pVmcb->guest.u64RIP = pCtx->rip;
2105	pVmcb->guest.u64RSP = pCtx->rsp;
2106	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2107	pVmcb->guest.u64RAX = pCtx->rax;
2108
2109	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
2110	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2111
2112	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
2113
2114	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2115	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2116
2117	/* Clear any unused and reserved bits. */
2118	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2119	\| HM_CHANGED_GUEST_RSP
2120	\| HM_CHANGED_GUEST_RFLAGS
2121	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2122	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2123	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2124	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2125	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2126	\| HM_CHANGED_SVM_RESERVED2
2127	\| HM_CHANGED_SVM_RESERVED3
2128	\| HM_CHANGED_SVM_RESERVED4);
2129
2130	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2131	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2132	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2133	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2134
2135	Log4(("hmR0SvmLoadGuestState: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 CR4=%#RX32\n", pCtx->cs.Sel, pCtx->rip,
2136	pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pCtx->cr4));
2137	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2138	return rc;
2139	}
2140
2141
2142	#ifdef VBOX_WITH_NESTED_HWVIRT
2143	/**
2144	* Caches the nested-guest VMCB fields before we modify them for execution using
2145	* hardware-assisted SVM.
2146	*
2147	* @returns true if the VMCB was previously already cached, false otherwise.
2148	* @param pCtx Pointer to the guest-CPU context.
2149	*
2150	* @sa HMSvmNstGstVmExitNotify.
2151	*/
2152	static bool hmR0SvmVmRunCacheVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2153	{
2154	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2155	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2156	PCSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
2157	PSVMNESTEDVMCBCACHE pNstGstVmcbCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2158
2159	/*
2160	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2161	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2162	*
2163	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2164	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2165	*/
2166	bool const fWasCached = pCtx->hwvirt.svm.fHMCachedVmcb;
2167	if (!fWasCached)
2168	{
2169	pNstGstVmcbCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2170	pNstGstVmcbCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2171	pNstGstVmcbCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2172	pNstGstVmcbCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2173	pNstGstVmcbCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2174	pNstGstVmcbCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2175	pNstGstVmcbCache->u64CR0 = pVmcbNstGstState->u64CR0;
2176	pNstGstVmcbCache->u64CR3 = pVmcbNstGstState->u64CR3;
2177	pNstGstVmcbCache->u64CR4 = pVmcbNstGstState->u64CR4;
2178	pNstGstVmcbCache->u64EFER = pVmcbNstGstState->u64EFER;
2179	pNstGstVmcbCache->u64IOPMPhysAddr = pVmcbNstGstCtrl->u64IOPMPhysAddr;
2180	pNstGstVmcbCache->u64MSRPMPhysAddr = pVmcbNstGstCtrl->u64MSRPMPhysAddr;
2181	pNstGstVmcbCache->u64VmcbCleanBits = pVmcbNstGstCtrl->u64VmcbCleanBits;
2182	pNstGstVmcbCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2183	pNstGstVmcbCache->TLBCtrl = pVmcbNstGstCtrl->TLBCtrl;
2184	pNstGstVmcbCache->NestedPagingCtrl = pVmcbNstGstCtrl->NestedPaging;
2185	pCtx->hwvirt.svm.fHMCachedVmcb = true;
2186	Log4(("hmR0SvmVmRunCacheVmcb: Cached VMCB fields\n"));
2187	}
2188
2189	return fWasCached;
2190	}
2191
2192
2193	/**
2194	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2195	*
2196	* @param pVCpu The cross context virtual CPU structure.
2197	* @param pCtx Pointer to the guest-CPU context.
2198	*/
2199	static void hmR0SvmVmRunSetupVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2200	{
2201	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2202	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2203
2204	/*
2205	* First cache the nested-guest VMCB fields we may potentially modify.
2206	*/
2207	bool const fVmcbCached = hmR0SvmVmRunCacheVmcb(pVCpu, pCtx);
2208	if (!fVmcbCached)
2209	{
2210	/*
2211	* The IOPM of the nested-guest can be ignored because the the guest always
2212	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2213	* into the nested-guest one and swap it back on the #VMEXIT.
2214	*/
2215	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2216
2217	/*
2218	* Load the host-physical address into the MSRPM rather than the nested-guest
2219	* physical address (currently we trap all MSRs in the nested-guest).
2220	*/
2221	pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap;
2222
2223	/*
2224	* Use the same nested-paging as the "outer" guest. We can't dynamically
2225	* switch off nested-paging suddenly while executing a VM (see assertion at the
2226	* end of Trap0eHandler in PGMAllBth.h).
2227	*/
2228	pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2229	}
2230	else
2231	{
2232	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2233	Assert(pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap);
2234	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2235	}
2236	}
2237
2238
2239	/**
2240	* Loads the nested-guest state into the VMCB.
2241	*
2242	* @returns VBox status code.
2243	* @param pVCpu The cross context virtual CPU structure.
2244	* @param pCtx Pointer to the guest-CPU context.
2245	*
2246	* @remarks No-long-jump zone!!!
2247	*/
2248	static int hmR0SvmLoadGuestStateNested(PVMCPU pVCpu, PCPUMCTX pCtx)
2249	{
2250	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2251
2252	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2253	Assert(pVmcbNstGst);
2254
2255	hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
2256	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx);
2257	hmR0SvmLoadGuestMsrs(pVCpu, pVmcbNstGst, pCtx);
2258
2259	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2260	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2261	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2262	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2263
2264	int rc = hmR0SvmLoadGuestControlRegsNested(pVCpu, pVmcbNstGst, pCtx);
2265	AssertRCReturn(rc, rc);
2266
2267	hmR0SvmLoadGuestApicStateNested(pVCpu, pVmcbNstGst);
2268	hmR0SvmLoadGuestXcptInterceptsNested(pVCpu, pVmcbNstGst, pCtx);
2269
2270	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2271	AssertRCReturn(rc, rc);
2272
2273	/* Clear any unused and reserved bits. */
2274	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2275	\| HM_CHANGED_GUEST_RSP
2276	\| HM_CHANGED_GUEST_RFLAGS
2277	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2278	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2279	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2280	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2281	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2282	\| HM_CHANGED_SVM_RESERVED2
2283	\| HM_CHANGED_SVM_RESERVED3
2284	\| HM_CHANGED_SVM_RESERVED4);
2285
2286	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2287	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2288	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2289	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2290
2291	Log4(("hmR0SvmLoadGuestStateNested: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 (HyperCR3=%#RX64) CR4=%#RX32 rc=%d\n",
2292	pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pVmcbNstGst->guest.u64CR3, pCtx->cr4, rc));
2293	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2294	return rc;
2295	}
2296	#endif
2297
2298
2299	/**
2300	* Loads the state shared between the host and guest or nested-guest into the
2301	* VMCB.
2302	*
2303	* @param pVCpu The cross context virtual CPU structure.
2304	* @param pVmcb Pointer to the VM control block.
2305	* @param pCtx Pointer to the guest-CPU context.
2306	*
2307	* @remarks No-long-jump zone!!!
2308	*/
2309	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2310	{
2311	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2312	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2313
2314	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
2315	{
2316	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2317	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
2318	}
2319
2320	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
2321	{
2322	/** @todo Figure out stepping with nested-guest. */
2323	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2324	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
2325	else
2326	{
2327	pVmcb->guest.u64DR6 = pCtx->dr[6];
2328	pVmcb->guest.u64DR7 = pCtx->dr[7];
2329	Log4(("hmR0SvmLoadSharedState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2330	}
2331
2332	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
2333	}
2334
2335	/* Unused on AMD-V. */
2336	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
2337
2338	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
2339	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2340	}
2341
2342
2343	/**
2344	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU context.
2345	*
2346	* Currently there is no residual state left in the CPU that is not updated in the
2347	* VMCB.
2348	*
2349	* @returns VBox status code.
2350	* @param pVCpu The cross context virtual CPU structure.
2351	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
2352	* out-of-sync. Make sure to update the required fields
2353	* before using them.
2354	* @param pVmcb Pointer to the VM control block.
2355	*/
2356	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PCSVMVMCB pVmcb)
2357	{
2358	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2359
2360	pMixedCtx->rip = pVmcb->guest.u64RIP;
2361	pMixedCtx->rsp = pVmcb->guest.u64RSP;
2362	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
2363	pMixedCtx->rax = pVmcb->guest.u64RAX;
2364
2365	/*
2366	* Guest interrupt shadow.
2367	*/
2368	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
2369	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
2370	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2371	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2372
2373	/*
2374	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
2375	*/
2376	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
2377
2378	/*
2379	* Guest MSRs.
2380	*/
2381	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
2382	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
2383	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
2384	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
2385	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
2386	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
2387	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
2388	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
2389
2390	/*
2391	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
2392	*/
2393	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, CS, cs);
2394	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, SS, ss);
2395	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, DS, ds);
2396	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, ES, es);
2397	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, FS, fs);
2398	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, GS, gs);
2399
2400	/*
2401	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
2402	* register (yet).
2403	*/
2404	/** @todo SELM might need to be fixed as it too should not care about the
2405	* granularity bit. See @bugref{6785}. */
2406	if ( !pMixedCtx->cs.Attr.n.u1Granularity
2407	&& pMixedCtx->cs.Attr.n.u1Present
2408	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
2409	{
2410	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
2411	pMixedCtx->cs.Attr.n.u1Granularity = 1;
2412	}
2413
2414	#ifdef VBOX_STRICT
2415	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
2416	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
2417	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
2418	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
2419	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
2420	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
2421	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
2422
2423	HMSVM_ASSERT_SEG_GRANULARITY(cs);
2424	HMSVM_ASSERT_SEG_GRANULARITY(ss);
2425	HMSVM_ASSERT_SEG_GRANULARITY(ds);
2426	HMSVM_ASSERT_SEG_GRANULARITY(es);
2427	HMSVM_ASSERT_SEG_GRANULARITY(fs);
2428	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2429
2430	# undef HMSVM_ASSERT_SEL_GRANULARITY
2431	#endif
2432
2433	/*
2434	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2435	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2436	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2437	* See AMD spec. 15.5.1 "Basic operation".
2438	*/
2439	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2440	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2441
2442	/*
2443	* Guest TR.
2444	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2445	* between Intel and AMD. See @bugref{6208#c39}.
2446	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2447	*/
2448	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, TR, tr);
2449	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2450	{
2451	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2452	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
2453	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2454	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2455	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2456	}
2457
2458	/*
2459	* Guest Descriptor-Table registers.
2460	*/
2461	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, LDTR, ldtr);
2462	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2463	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2464
2465	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2466	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2467
2468	/*
2469	* Guest Debug registers.
2470	*/
2471	if (!pVCpu->hm.s.fUsingHyperDR7)
2472	{
2473	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2474	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2475	}
2476	else
2477	{
2478	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2479	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2480	}
2481
2482	/*
2483	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2484	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2485	*/
2486	if ( pVmcb->ctrl.NestedPaging.n.u1NestedPaging
2487	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2488	{
2489	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2490	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2491	}
2492
2493	Log4(("hmR0SvmSaveGuestState: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 CR4=%#RX32\n", pMixedCtx->cs.Sel,
2494	pMixedCtx->rip, pMixedCtx->eflags.u, pMixedCtx->cr0, pMixedCtx->cr3, pMixedCtx->cr4));
2495	}
2496
2497
2498	/**
2499	* Does the necessary state syncing before returning to ring-3 for any reason
2500	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2501	*
2502	* @param pVCpu The cross context virtual CPU structure.
2503	*
2504	* @remarks No-long-jmp zone!!!
2505	*/
2506	static void hmR0SvmLeave(PVMCPU pVCpu)
2507	{
2508	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2509	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2510	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2511
2512	/*
2513	* !!! IMPORTANT !!!
2514	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2515	*/
2516
2517	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2518	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2519	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0); /** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2520
2521	/*
2522	* Restore host debug registers if necessary and resync on next R0 reentry.
2523	*/
2524	#ifdef VBOX_STRICT
2525	if (CPUMIsHyperDebugStateActive(pVCpu))
2526	{
2527	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
2528	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2529	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2530	}
2531	#endif
2532	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2533	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);/** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2534
2535	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2536	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2537
2538	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2539	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2540	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2541	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2542	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2543
2544	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2545	}
2546
2547
2548	/**
2549	* Leaves the AMD-V session.
2550	*
2551	* @returns VBox status code.
2552	* @param pVCpu The cross context virtual CPU structure.
2553	*/
2554	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2555	{
2556	HM_DISABLE_PREEMPT();
2557	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2558	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2559
2560	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2561	and done this from the SVMR0ThreadCtxCallback(). */
2562	if (!pVCpu->hm.s.fLeaveDone)
2563	{
2564	hmR0SvmLeave(pVCpu);
2565	pVCpu->hm.s.fLeaveDone = true;
2566	}
2567
2568	/*
2569	* !!! IMPORTANT !!!
2570	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2571	*/
2572
2573	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2574	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2575	VMMR0ThreadCtxHookDisable(pVCpu);
2576
2577	/* Leave HM context. This takes care of local init (term). */
2578	int rc = HMR0LeaveCpu(pVCpu);
2579
2580	HM_RESTORE_PREEMPT();
2581	return rc;
2582	}
2583
2584
2585	/**
2586	* Does the necessary state syncing before doing a longjmp to ring-3.
2587	*
2588	* @returns VBox status code.
2589	* @param pVCpu The cross context virtual CPU structure.
2590	*
2591	* @remarks No-long-jmp zone!!!
2592	*/
2593	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2594	{
2595	return hmR0SvmLeaveSession(pVCpu);
2596	}
2597
2598
2599	/**
2600	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2601	* any remaining host state) before we longjump to ring-3 and possibly get
2602	* preempted.
2603	*
2604	* @param pVCpu The cross context virtual CPU structure.
2605	* @param enmOperation The operation causing the ring-3 longjump.
2606	* @param pvUser The user argument (pointer to the possibly
2607	* out-of-date guest-CPU context).
2608	*/
2609	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2610	{
2611	RT_NOREF_PV(pvUser);
2612
2613	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2614	{
2615	/*
2616	* !!! IMPORTANT !!!
2617	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2618	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2619	*/
2620	VMMRZCallRing3RemoveNotification(pVCpu);
2621	VMMRZCallRing3Disable(pVCpu);
2622	HM_DISABLE_PREEMPT();
2623
2624	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2625	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2626
2627	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2628	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2629
2630	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2631	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2632	VMMR0ThreadCtxHookDisable(pVCpu);
2633
2634	/* Leave HM context. This takes care of local init (term). */
2635	HMR0LeaveCpu(pVCpu);
2636
2637	HM_RESTORE_PREEMPT();
2638	return VINF_SUCCESS;
2639	}
2640
2641	Assert(pVCpu);
2642	Assert(pvUser);
2643	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2644	HMSVM_ASSERT_PREEMPT_SAFE();
2645
2646	VMMRZCallRing3Disable(pVCpu);
2647	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2648
2649	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2650	int rc = hmR0SvmLongJmpToRing3(pVCpu);
2651	AssertRCReturn(rc, rc);
2652
2653	VMMRZCallRing3Enable(pVCpu);
2654	return VINF_SUCCESS;
2655	}
2656
2657
2658	/**
2659	* Take necessary actions before going back to ring-3.
2660	*
2661	* An action requires us to go back to ring-3. This function does the necessary
2662	* steps before we can safely return to ring-3. This is not the same as longjmps
2663	* to ring-3, this is voluntary.
2664	*
2665	* @returns VBox status code.
2666	* @param pVM The cross context VM structure.
2667	* @param pVCpu The cross context virtual CPU structure.
2668	* @param pCtx Pointer to the guest-CPU context.
2669	* @param rcExit The reason for exiting to ring-3. Can be
2670	* VINF_VMM_UNKNOWN_RING3_CALL.
2671	*/
2672	static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2673	{
2674	Assert(pVM);
2675	Assert(pVCpu);
2676	Assert(pCtx);
2677	HMSVM_ASSERT_PREEMPT_SAFE();
2678
2679	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2680	VMMRZCallRing3Disable(pVCpu);
2681	Log4(("hmR0SvmExitToRing3: VCPU[%u]: rcExit=%d LocalFF=%#RX32 GlobalFF=%#RX32\n", pVCpu->idCpu, rcExit,
2682	pVCpu->fLocalForcedActions, pVM->fGlobalForcedActions));
2683
2684	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2685	if (pVCpu->hm.s.Event.fPending)
2686	{
2687	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2688	Assert(!pVCpu->hm.s.Event.fPending);
2689	}
2690
2691	/* Sync. the necessary state for going back to ring-3. */
2692	hmR0SvmLeaveSession(pVCpu);
2693	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2694
2695	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2696	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2697	\| CPUM_CHANGED_LDTR
2698	\| CPUM_CHANGED_GDTR
2699	\| CPUM_CHANGED_IDTR
2700	\| CPUM_CHANGED_TR
2701	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2702	if ( pVM->hm.s.fNestedPaging
2703	&& CPUMIsGuestPagingEnabledEx(pCtx))
2704	{
2705	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2706	}
2707
2708	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2709	if (rcExit != VINF_EM_RAW_INTERRUPT)
2710	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2711
2712	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2713
2714	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2715	VMMRZCallRing3RemoveNotification(pVCpu);
2716	VMMRZCallRing3Enable(pVCpu);
2717
2718	/*
2719	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2720	* and if we're injecting an event we should have a TRPM trap pending.
2721	*/
2722	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
2723	pVCpu->hm.s.u32HMError = rcExit,
2724	VERR_SVM_IPE_5);
2725	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
2726	pVCpu->hm.s.u32HMError = rcExit,
2727	VERR_SVM_IPE_4);
2728
2729	return rcExit;
2730	}
2731
2732
2733	/**
2734	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2735	* intercepts.
2736	*
2737	* @param pVM The cross context VM structure.
2738	* @param pVCpu The cross context virtual CPU structure.
2739	* @param pVmcb Pointer to the VM control block.
2740	*
2741	* @remarks No-long-jump zone!!!
2742	*/
2743	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu, PSVMVMCB pVmcb)
2744	{
2745	bool fParavirtTsc;
2746	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2747	if (fCanUseRealTsc)
2748	{
2749	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSC;
2750	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSCP;
2751	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2752	}
2753	else
2754	{
2755	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC;
2756	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSCP;
2757	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2758	}
2759	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2760
2761	/** @todo later optimize this to be done elsewhere and not before every
2762	* VM-entry. */
2763	if (fParavirtTsc)
2764	{
2765	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2766	information before every VM-entry, hence disable it for performance sake. */
2767	#if 0
2768	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
2769	AssertRC(rc);
2770	#endif
2771	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2772	}
2773	}
2774
2775
2776	/**
2777	* Sets an event as a pending event to be injected into the guest.
2778	*
2779	* @param pVCpu The cross context virtual CPU structure.
2780	* @param pEvent Pointer to the SVM event.
2781	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2782	* page-fault.
2783	*
2784	* @remarks Statistics counter assumes this is a guest event being reflected to
2785	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2786	*/
2787	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2788	{
2789	Assert(!pVCpu->hm.s.Event.fPending);
2790	Assert(pEvent->n.u1Valid);
2791
2792	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2793	pVCpu->hm.s.Event.fPending = true;
2794	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2795
2796	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2797	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2798	}
2799
2800
2801	/**
2802	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
2803	*
2804	* @param pVCpu The cross context virtual CPU structure.
2805	*/
2806	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
2807	{
2808	SVMEVENT Event;
2809	Event.u = 0;
2810	Event.n.u1Valid = 1;
2811	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2812	Event.n.u8Vector = X86_XCPT_UD;
2813	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2814	}
2815
2816
2817	/**
2818	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
2819	*
2820	* @param pVCpu The cross context virtual CPU structure.
2821	*/
2822	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
2823	{
2824	SVMEVENT Event;
2825	Event.u = 0;
2826	Event.n.u1Valid = 1;
2827	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2828	Event.n.u8Vector = X86_XCPT_DB;
2829	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2830	}
2831
2832
2833	/**
2834	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
2835	*
2836	* @param pVCpu The cross context virtual CPU structure.
2837	* @param pCtx Pointer to the guest-CPU context.
2838	* @param u32ErrCode The error-code for the page-fault.
2839	* @param uFaultAddress The page fault address (CR2).
2840	*
2841	* @remarks This updates the guest CR2 with @a uFaultAddress!
2842	*/
2843	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
2844	{
2845	SVMEVENT Event;
2846	Event.u = 0;
2847	Event.n.u1Valid = 1;
2848	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2849	Event.n.u8Vector = X86_XCPT_PF;
2850	Event.n.u1ErrorCodeValid = 1;
2851	Event.n.u32ErrorCode = u32ErrCode;
2852
2853	/* Update CR2 of the guest. */
2854	if (pCtx->cr2 != uFaultAddress)
2855	{
2856	pCtx->cr2 = uFaultAddress;
2857	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
2858	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
2859	}
2860
2861	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
2862	}
2863
2864
2865	/**
2866	* Sets a device-not-available (\#NM) exception as pending-for-injection into
2867	* the VM.
2868	*
2869	* @param pVCpu The cross context virtual CPU structure.
2870	*/
2871	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
2872	{
2873	SVMEVENT Event;
2874	Event.u = 0;
2875	Event.n.u1Valid = 1;
2876	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2877	Event.n.u8Vector = X86_XCPT_NM;
2878	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2879	}
2880
2881
2882	/**
2883	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
2884	*
2885	* @param pVCpu The cross context virtual CPU structure.
2886	*/
2887	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
2888	{
2889	SVMEVENT Event;
2890	Event.u = 0;
2891	Event.n.u1Valid = 1;
2892	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2893	Event.n.u8Vector = X86_XCPT_MF;
2894	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2895	}
2896
2897
2898	/**
2899	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
2900	*
2901	* @param pVCpu The cross context virtual CPU structure.
2902	*/
2903	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
2904	{
2905	SVMEVENT Event;
2906	Event.u = 0;
2907	Event.n.u1Valid = 1;
2908	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2909	Event.n.u8Vector = X86_XCPT_DF;
2910	Event.n.u1ErrorCodeValid = 1;
2911	Event.n.u32ErrorCode = 0;
2912	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2913	}
2914
2915
2916	/**
2917	* Injects an event into the guest upon VMRUN by updating the relevant field
2918	* in the VMCB.
2919	*
2920	* @param pVCpu The cross context virtual CPU structure.
2921	* @param pVmcb Pointer to the guest VM control block.
2922	* @param pCtx Pointer to the guest-CPU context.
2923	* @param pEvent Pointer to the event.
2924	*
2925	* @remarks No-long-jump zone!!!
2926	* @remarks Requires CR0!
2927	*/
2928	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2929	{
2930	NOREF(pVCpu); NOREF(pCtx);
2931
2932	pVmcb->ctrl.EventInject.u = pEvent->u;
2933	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2934
2935	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2936	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2937	}
2938
2939
2940
2941	/**
2942	* Converts any TRPM trap into a pending HM event. This is typically used when
2943	* entering from ring-3 (not longjmp returns).
2944	*
2945	* @param pVCpu The cross context virtual CPU structure.
2946	*/
2947	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2948	{
2949	Assert(TRPMHasTrap(pVCpu));
2950	Assert(!pVCpu->hm.s.Event.fPending);
2951
2952	uint8_t uVector;
2953	TRPMEVENT enmTrpmEvent;
2954	RTGCUINT uErrCode;
2955	RTGCUINTPTR GCPtrFaultAddress;
2956	uint8_t cbInstr;
2957
2958	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2959	AssertRC(rc);
2960
2961	SVMEVENT Event;
2962	Event.u = 0;
2963	Event.n.u1Valid = 1;
2964	Event.n.u8Vector = uVector;
2965
2966	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2967	if (enmTrpmEvent == TRPM_TRAP)
2968	{
2969	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2970	switch (uVector)
2971	{
2972	case X86_XCPT_NMI:
2973	{
2974	Event.n.u3Type = SVM_EVENT_NMI;
2975	break;
2976	}
2977
2978	case X86_XCPT_PF:
2979	case X86_XCPT_DF:
2980	case X86_XCPT_TS:
2981	case X86_XCPT_NP:
2982	case X86_XCPT_SS:
2983	case X86_XCPT_GP:
2984	case X86_XCPT_AC:
2985	{
2986	Event.n.u1ErrorCodeValid = 1;
2987	Event.n.u32ErrorCode = uErrCode;
2988	break;
2989	}
2990	}
2991	}
2992	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2993	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2994	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2995	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2996	else
2997	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2998
2999	rc = TRPMResetTrap(pVCpu);
3000	AssertRC(rc);
3001
3002	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3003	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3004
3005	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3006	}
3007
3008
3009	/**
3010	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3011	* AMD-V to execute any instruction.
3012	*
3013	* @param pVCpu The cross context virtual CPU structure.
3014	*/
3015	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
3016	{
3017	Assert(pVCpu->hm.s.Event.fPending);
3018	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3019
3020	SVMEVENT Event;
3021	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3022
3023	uint8_t uVector = Event.n.u8Vector;
3024	uint8_t uVectorType = Event.n.u3Type;
3025	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
3026
3027	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
3028
3029	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3030	AssertRC(rc);
3031
3032	if (Event.n.u1ErrorCodeValid)
3033	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3034
3035	if ( uVectorType == SVM_EVENT_EXCEPTION
3036	&& uVector == X86_XCPT_PF)
3037	{
3038	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3039	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3040	}
3041	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
3042	{
3043	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
3044	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
3045	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
3046	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3047	}
3048	pVCpu->hm.s.Event.fPending = false;
3049	}
3050
3051
3052	/**
3053	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3054	* now.
3055	*
3056	* @returns true if the interrupt shadow is active, false otherwise.
3057	* @param pVCpu The cross context virtual CPU structure.
3058	* @param pCtx Pointer to the guest-CPU context.
3059	*
3060	* @remarks No-long-jump zone!!!
3061	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3062	*/
3063	DECLINLINE(bool) hmR0SvmIsIntrShadowActive(PVMCPU pVCpu, PCPUMCTX pCtx)
3064	{
3065	/*
3066	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
3067	* inhibit interrupts or clear any existing interrupt-inhibition.
3068	*/
3069	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3070	{
3071	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
3072	{
3073	/*
3074	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
3075	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
3076	*/
3077	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3078	return false;
3079	}
3080	return true;
3081	}
3082	return false;
3083	}
3084
3085
3086	/**
3087	* Sets the virtual interrupt intercept control in the VMCB which
3088	* instructs AMD-V to cause a \#VMEXIT as soon as the guest is in a state to
3089	* receive interrupts.
3090	*
3091	* @param pVmcb Pointer to the VM control block.
3092	*/
3093	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
3094	{
3095	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3096	{
3097	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1; /* A virtual interrupt is pending. */
3098	pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0; /* Vector not necessary as we #VMEXIT for delivering the interrupt. */
3099	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VINTR;
3100	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3101
3102	Log4(("Setting VINTR intercept\n"));
3103	}
3104	}
3105
3106
3107	#if 0
3108	/**
3109	* Clears the virtual interrupt intercept control in the VMCB as
3110	* we are figured the guest is unable process any interrupts
3111	* at this point of time.
3112	*
3113	* @param pVmcb Pointer to the VM control block.
3114	*/
3115	DECLINLINE(void) hmR0SvmClearVirtIntrIntercept(PSVMVMCB pVmcb)
3116	{
3117	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3118	{
3119	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
3120	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3121	Log4(("Clearing VINTR intercept\n"));
3122	}
3123	}
3124	#endif
3125
3126
3127	/**
3128	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
3129	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
3130	* virtual NMIs.
3131	*
3132	* @param pVmcb Pointer to the VM control block.
3133	*/
3134	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
3135	{
3136	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET))
3137	{
3138	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_IRET;
3139	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3140
3141	Log4(("Setting IRET intercept\n"));
3142	}
3143	}
3144
3145
3146	/**
3147	* Clears the IRET intercept control in the VMCB.
3148	*
3149	* @param pVmcb Pointer to the VM control block.
3150	*/
3151	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
3152	{
3153	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
3154	{
3155	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
3156	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3157
3158	Log4(("Clearing IRET intercept\n"));
3159	}
3160	}
3161
3162	#ifdef VBOX_WITH_NESTED_HWVIRT
3163
3164
3165	/**
3166	* Evaluates the event to be delivered to the nested-guest and sets it as the
3167	* pending event.
3168	*
3169	* @returns VBox strict status code.
3170	* @param pVCpu The cross context virtual CPU structure.
3171	* @param pCtx Pointer to the guest-CPU context.
3172	*/
3173	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu, PCPUMCTX pCtx)
3174	{
3175	Log4Func(("\n"));
3176
3177	Assert(!pVCpu->hm.s.Event.fPending);
3178
3179	bool const fGif = pCtx->hwvirt.svm.fGif;
3180	if (fGif)
3181	{
3182	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3183
3184	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3185
3186	/*
3187	* Check if the nested-guest can receive NMIs.
3188	* NMIs are higher priority than regular interrupts.
3189	*/
3190	/** @todo SMI. SMIs take priority over NMIs. */
3191	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))
3192	{
3193	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3194	if (fBlockNmi)
3195	hmR0SvmSetIretIntercept(pVmcbNstGst);
3196	else if (fIntShadow)
3197	{
3198	/** @todo Figure this out, how we shall manage virt. intercept if the
3199	* nested-guest already has one set and/or if we really need it? */
3200	//hmR0SvmSetVirtIntrIntercept(pVmcbNstGst);
3201	}
3202	else
3203	{
3204	Log4(("Pending NMI\n"));
3205
3206	SVMEVENT Event;
3207	Event.u = 0;
3208	Event.n.u1Valid = 1;
3209	Event.n.u8Vector = X86_XCPT_NMI;
3210	Event.n.u3Type = SVM_EVENT_NMI;
3211
3212	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3213	hmR0SvmSetIretIntercept(pVmcbNstGst);
3214	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3215	return VINF_SUCCESS;
3216	}
3217	}
3218
3219	/*
3220	* Check if the nested-guest can receive external interrupts (generated by
3221	* the guest's PIC/APIC).
3222	*
3223	* External intercepts from the physical CPU are -always- intercepted when
3224	* executing using hardware-assisted SVM, see HMSVM_MANDATORY_NESTED_GUEST_CTRL_INTERCEPTS.
3225	*
3226	* External interrupts that are generated for the outer guest may be intercepted
3227	* depending on how the nested-guest VMCB was programmed by guest software.
3228	*
3229	* Physical interrupts always take priority over virtual interrupts,
3230	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3231	*/
3232	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3233	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3234	&& !fIntShadow
3235	&& !pVCpu->hm.s.fSingleInstruction
3236	&& CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx))
3237	{
3238	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INTR)
3239	{
3240	Log4(("Intercepting external interrupt -> #VMEXIT\n"));
3241	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3242	}
3243
3244	uint8_t u8Interrupt;
3245	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3246	if (RT_SUCCESS(rc))
3247	{
3248	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3249
3250	SVMEVENT Event;
3251	Event.u = 0;
3252	Event.n.u1Valid = 1;
3253	Event.n.u8Vector = u8Interrupt;
3254	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3255
3256	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3257	}
3258	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3259	{
3260	/*
3261	* AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
3262	* We just avoid delivering the TPR-masked interrupt here. TPR will be updated
3263	* always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
3264	*/
3265	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3266	}
3267	else
3268	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3269	}
3270
3271	/*
3272	* Check if the nested-guest can receive virtual (injected by VMRUN) interrupts.
3273	* We can safely call CPUMCanSvmNstGstTakeVirtIntr here as we don't cache/modify any
3274	* nested-guest VMCB interrupt control fields besides V_INTR_MASKING, see hmR0SvmVmRunCacheVmcb.
3275	*/
3276	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
3277	&& (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3278	&& CPUMCanSvmNstGstTakeVirtIntr(pCtx))
3279	{
3280	Log4(("Intercepting virtual interrupt -> #VMEXIT\n"));
3281	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_VINTR, 0, 0);
3282	}
3283	}
3284
3285	return VINF_SUCCESS;
3286	}
3287	#endif
3288
3289
3290	/**
3291	* Evaluates the event to be delivered to the guest and sets it as the pending
3292	* event.
3293	*
3294	* @param pVCpu The cross context virtual CPU structure.
3295	* @param pCtx Pointer to the guest-CPU context.
3296	*
3297	* @remarks Don't use this function when we are actively executing a
3298	* nested-guest, use hmR0SvmEvaluatePendingEventNested instead.
3299	*/
3300	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
3301	{
3302	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3303	Assert(!pVCpu->hm.s.Event.fPending);
3304
3305	#ifdef VBOX_WITH_NESTED_HWVIRT
3306	bool const fGif = pCtx->hwvirt.svm.fGif;
3307	#else
3308	bool const fGif = true;
3309	#endif
3310	Log4Func(("fGif=%RTbool\n", fGif));
3311
3312	/*
3313	* If the global interrupt flag (GIF) isn't set, even NMIs and other events are blocked.
3314	* See AMD spec. Table 15-10. "Effect of the GIF on Interrupt Handling".
3315	*/
3316	if (fGif)
3317	{
3318	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3319	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3320	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3321	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3322
3323	Log4Func(("fGif=%RTbool fBlockInt=%RTbool fIntShadow=%RTbool APIC/PIC_Pending=%RTbool\n", fGif, fBlockInt, fIntShadow,
3324	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
3325
3326	/** @todo SMI. SMIs take priority over NMIs. */
3327	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
3328	{
3329	if (fBlockNmi)
3330	hmR0SvmSetIretIntercept(pVmcb);
3331	else if (fIntShadow)
3332	hmR0SvmSetVirtIntrIntercept(pVmcb);
3333	else
3334	{
3335	Log4(("Pending NMI\n"));
3336
3337	SVMEVENT Event;
3338	Event.u = 0;
3339	Event.n.u1Valid = 1;
3340	Event.n.u8Vector = X86_XCPT_NMI;
3341	Event.n.u3Type = SVM_EVENT_NMI;
3342
3343	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3344	hmR0SvmSetIretIntercept(pVmcb);
3345	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3346	return;
3347	}
3348	}
3349	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3350	&& !pVCpu->hm.s.fSingleInstruction)
3351	{
3352	/*
3353	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
3354	* a valid interrupt we -must- deliver the interrupt. We can no longer re-request it from the APIC.
3355	*/
3356	if ( !fBlockInt
3357	&& !fIntShadow)
3358	{
3359	uint8_t u8Interrupt;
3360	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3361	if (RT_SUCCESS(rc))
3362	{
3363	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3364
3365	SVMEVENT Event;
3366	Event.u = 0;
3367	Event.n.u1Valid = 1;
3368	Event.n.u8Vector = u8Interrupt;
3369	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3370
3371	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3372	}
3373	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3374	{
3375	/*
3376	* AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
3377	* We just avoid delivering the TPR-masked interrupt here. TPR will be updated
3378	* always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
3379	*/
3380	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3381	}
3382	else
3383	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3384	}
3385	else
3386	hmR0SvmSetVirtIntrIntercept(pVmcb);
3387	}
3388	}
3389	}
3390
3391
3392	/**
3393	* Injects any pending events into the guest or nested-guest.
3394	*
3395	* @param pVCpu The cross context virtual CPU structure.
3396	* @param pCtx Pointer to the guest-CPU context.
3397	* @param pVmcb Pointer to the VM control block.
3398	*/
3399	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
3400	{
3401	Assert(!TRPMHasTrap(pVCpu));
3402	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3403
3404	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3405
3406	/*
3407	* When executing the nested-guest, we avoid assertions on whether the
3408	* event injection is valid purely based on EFLAGS, as V_INTR_MASKING
3409	* affects the interpretation of interruptibility (see CPUMCanSvmNstGstTakePhysIntr).
3410	*/
3411	#ifndef VBOX_WITH_NESTED_HWVIRT
3412	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3413	#endif
3414
3415	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
3416	{
3417	SVMEVENT Event;
3418	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3419	Assert(Event.n.u1Valid);
3420
3421	#ifndef VBOX_WITH_NESTED_HWVIRT
3422	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3423	{
3424	Assert(!fBlockInt);
3425	Assert(!fIntShadow);
3426	}
3427	else if (Event.n.u3Type == SVM_EVENT_NMI)
3428	Assert(!fIntShadow);
3429	NOREF(fBlockInt);
3430	#else
3431	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3432	#endif
3433
3434	Log4(("Injecting pending HM event\n"));
3435	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
3436	pVCpu->hm.s.Event.fPending = false;
3437
3438	#ifdef VBOX_WITH_STATISTICS
3439	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3440	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3441	else
3442	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3443	#endif
3444	}
3445
3446	/*
3447	* Update the guest interrupt shadow in the guest or nested-guest VMCB.
3448	*
3449	* For nested-guests: We need to update it too for the scenario where IEM executes
3450	* the nested-guest but execution later continues here with an interrupt shadow active.
3451	*/
3452	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
3453	}
3454
3455
3456	/**
3457	* Reports world-switch error and dumps some useful debug info.
3458	*
3459	* @param pVM The cross context VM structure.
3460	* @param pVCpu The cross context virtual CPU structure.
3461	* @param rcVMRun The return code from VMRUN (or
3462	* VERR_SVM_INVALID_GUEST_STATE for invalid
3463	* guest-state).
3464	* @param pCtx Pointer to the guest-CPU context.
3465	*/
3466	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
3467	{
3468	NOREF(pCtx);
3469	HMSVM_ASSERT_PREEMPT_SAFE();
3470	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3471	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3472
3473	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3474	{
3475	hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
3476	#ifdef VBOX_STRICT
3477	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
3478	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3479	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3480	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3481	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3482	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3483	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3484	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3485	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3486	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3487
3488	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3489	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3490	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3491
3492	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3493	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3494	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
3495	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3496	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3497	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3498	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3499	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
3500	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3501	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3502
3503	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
3504	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3505	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3506	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3507	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3508	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3509	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3510	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3511	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3512	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3513	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
3514	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3515	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3516	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3517	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3518	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3519	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3520
3521	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3522	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
3523
3524	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3525	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3526	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3527	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3528	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3529	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3530	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3531	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3532	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3533	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3534	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3535	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3536	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3537	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3538	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3539	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3540	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3541	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3542	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3543	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3544
3545	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3546	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3547
3548	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3549	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3550	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3551	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3552
3553	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3554	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3555
3556	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3557	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3558	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3559	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3560
3561	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3562	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3563	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3564	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3565	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3566	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3567	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3568
3569	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3570	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3571	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3572	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3573
3574	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3575	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3576	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3577
3578	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3579	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3580	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3581	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3582	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3583	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3584	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
3585	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3586	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3587	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3588	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3589	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3590	#endif /* VBOX_STRICT */
3591	}
3592	else
3593	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
3594
3595	NOREF(pVmcb);
3596	}
3597
3598
3599	/**
3600	* Check per-VM and per-VCPU force flag actions that require us to go back to
3601	* ring-3 for one reason or another.
3602	*
3603	* @returns VBox status code (information status code included).
3604	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3605	* ring-3.
3606	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3607	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3608	* interrupts)
3609	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3610	* all EMTs to be in ring-3.
3611	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3612	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3613	* to the EM loop.
3614	*
3615	* @param pVM The cross context VM structure.
3616	* @param pVCpu The cross context virtual CPU structure.
3617	* @param pCtx Pointer to the guest-CPU context.
3618	*/
3619	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3620	{
3621	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3622
3623	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
3624	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
3625	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3626
3627	/* Update pending interrupts into the APIC's IRR. */
3628	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3629	APICUpdatePendingInterrupts(pVCpu);
3630
3631	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
3632	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3633	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
3634	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3635	{
3636	/* Pending PGM C3 sync. */
3637	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3638	{
3639	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3640	if (rc != VINF_SUCCESS)
3641	{
3642	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
3643	return rc;
3644	}
3645	}
3646
3647	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
3648	/* -XXX- what was that about single stepping? */
3649	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
3650	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3651	{
3652	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3653	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
3654	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
3655	return rc;
3656	}
3657
3658	/* Pending VM request packets, such as hardware interrupts. */
3659	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
3660	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
3661	{
3662	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
3663	return VINF_EM_PENDING_REQUEST;
3664	}
3665
3666	/* Pending PGM pool flushes. */
3667	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
3668	{
3669	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
3670	return VINF_PGM_POOL_FLUSH_PENDING;
3671	}
3672
3673	/* Pending DMA requests. */
3674	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
3675	{
3676	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
3677	return VINF_EM_RAW_TO_R3;
3678	}
3679	}
3680
3681	return VINF_SUCCESS;
3682	}
3683
3684
3685	#ifdef VBOX_WITH_NESTED_HWVIRT
3686	/**
3687	* Does the preparations before executing nested-guest code in AMD-V.
3688	*
3689	* @returns VBox status code (informational status codes included).
3690	* @retval VINF_SUCCESS if we can proceed with running the guest.
3691	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3692	*
3693	* @param pVM The cross context VM structure.
3694	* @param pVCpu The cross context virtual CPU structure.
3695	* @param pCtx Pointer to the guest-CPU context.
3696	* @param pSvmTransient Pointer to the SVM transient structure.
3697	*
3698	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
3699	* @sa hmR0SvmPreRunGuest.
3700	*/
3701	static int hmR0SvmPreRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3702	{
3703	HMSVM_ASSERT_PREEMPT_SAFE();
3704
3705	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3706	{
3707	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
3708	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
3709	return VINF_EM_RESCHEDULE_REM;
3710	#endif
3711	}
3712	else
3713	return VINF_SVM_VMEXIT;
3714
3715	/* Check force flag actions that might require us to go back to ring-3. */
3716	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3717	if (rc != VINF_SUCCESS)
3718	return rc;
3719
3720	if (TRPMHasTrap(pVCpu))
3721	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3722	else if (!pVCpu->hm.s.Event.fPending)
3723	{
3724	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu, pCtx);
3725	if (rcStrict != VINF_SUCCESS)
3726	return VBOXSTRICTRC_VAL(rcStrict);
3727	}
3728
3729	/*
3730	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3731	* Just do it in software, see @bugref{8411}.
3732	* NB: If we could continue a task switch exit we wouldn't need to do this.
3733	*/
3734	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
3735	&& pVCpu->hm.s.Event.fPending
3736	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
3737	{
3738	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3739	}
3740
3741	/*
3742	* Load the nested-guest state.
3743	*/
3744	rc = hmR0SvmLoadGuestStateNested(pVCpu, pCtx);
3745	AssertRCReturn(rc, rc);
3746	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull); /** @todo Get new STAM counter for this? */
3747
3748	/* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware SVM. */
3749	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
3750
3751	/*
3752	* No longjmps to ring-3 from this point on!!!
3753	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3754	* This also disables flushing of the R0-logger instance (if any).
3755	*/
3756	VMMRZCallRing3Disable(pVCpu);
3757
3758	/*
3759	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3760	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3761	*
3762	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3763	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3764	*
3765	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3766	* executing guest code.
3767	*/
3768	pSvmTransient->fEFlags = ASMIntDisableFlags();
3769	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3770	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3771	{
3772	ASMSetFlags(pSvmTransient->fEFlags);
3773	VMMRZCallRing3Enable(pVCpu);
3774	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3775	return VINF_EM_RAW_TO_R3;
3776	}
3777	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3778	{
3779	ASMSetFlags(pSvmTransient->fEFlags);
3780	VMMRZCallRing3Enable(pVCpu);
3781	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3782	return VINF_EM_RAW_INTERRUPT;
3783	}
3784
3785	/*
3786	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3787	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3788	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3789	*
3790	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3791	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3792	*/
3793	if (pVCpu->hm.s.Event.fPending)
3794	{
3795	SVMEVENT Event;
3796	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3797	if ( Event.n.u1Valid
3798	&& Event.n.u3Type == SVM_EVENT_NMI
3799	&& Event.n.u8Vector == X86_XCPT_NMI
3800	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3801	{
3802	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3803	}
3804	}
3805
3806	return VINF_SUCCESS;
3807	}
3808	#endif
3809
3810
3811	/**
3812	* Does the preparations before executing guest code in AMD-V.
3813	*
3814	* This may cause longjmps to ring-3 and may even result in rescheduling to the
3815	* recompiler. We must be cautious what we do here regarding committing
3816	* guest-state information into the VMCB assuming we assuredly execute the guest
3817	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
3818	* clearing the common-state (TRPM/forceflags), we must undo those changes so
3819	* that the recompiler can (and should) use them when it resumes guest
3820	* execution. Otherwise such operations must be done when we can no longer
3821	* exit to ring-3.
3822	*
3823	* @returns VBox status code (informational status codes included).
3824	* @retval VINF_SUCCESS if we can proceed with running the guest.
3825	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3826	*
3827	* @param pVM The cross context VM structure.
3828	* @param pVCpu The cross context virtual CPU structure.
3829	* @param pCtx Pointer to the guest-CPU context.
3830	* @param pSvmTransient Pointer to the SVM transient structure.
3831	*/
3832	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3833	{
3834	HMSVM_ASSERT_PREEMPT_SAFE();
3835	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3836
3837	/* Check force flag actions that might require us to go back to ring-3. */
3838	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3839	if (rc != VINF_SUCCESS)
3840	return rc;
3841
3842	if (TRPMHasTrap(pVCpu))
3843	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3844	else if (!pVCpu->hm.s.Event.fPending)
3845	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
3846
3847	/*
3848	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3849	* Just do it in software, see @bugref{8411}.
3850	* NB: If we could continue a task switch exit we wouldn't need to do this.
3851	*/
3852	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
3853	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
3854	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3855
3856	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
3857	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3858	#endif
3859
3860	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
3861	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
3862	AssertRCReturn(rc, rc);
3863	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
3864
3865	/*
3866	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
3867	* so we can update it on the way back if the guest changed the TPR.
3868	*/
3869	if (pVCpu->hm.s.svm.fSyncVTpr)
3870	{
3871	if (pVM->hm.s.fTPRPatchingActive)
3872	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
3873	else
3874	{
3875	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3876	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
3877	}
3878	}
3879
3880	/*
3881	* No longjmps to ring-3 from this point on!!!
3882	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3883	* This also disables flushing of the R0-logger instance (if any).
3884	*/
3885	VMMRZCallRing3Disable(pVCpu);
3886
3887	/*
3888	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3889	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3890	*
3891	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3892	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3893	*
3894	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3895	* executing guest code.
3896	*/
3897	pSvmTransient->fEFlags = ASMIntDisableFlags();
3898	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3899	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3900	{
3901	ASMSetFlags(pSvmTransient->fEFlags);
3902	VMMRZCallRing3Enable(pVCpu);
3903	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3904	return VINF_EM_RAW_TO_R3;
3905	}
3906	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3907	{
3908	ASMSetFlags(pSvmTransient->fEFlags);
3909	VMMRZCallRing3Enable(pVCpu);
3910	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3911	return VINF_EM_RAW_INTERRUPT;
3912	}
3913
3914	/*
3915	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3916	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3917	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3918	*
3919	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3920	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3921	*/
3922	if (pVCpu->hm.s.Event.fPending)
3923	{
3924	SVMEVENT Event;
3925	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3926	if ( Event.n.u1Valid
3927	&& Event.n.u3Type == SVM_EVENT_NMI
3928	&& Event.n.u8Vector == X86_XCPT_NMI
3929	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3930	{
3931	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3932	}
3933	}
3934
3935	return VINF_SUCCESS;
3936	}
3937
3938
3939	#ifdef VBOX_WITH_NESTED_HWVIRT
3940	/**
3941	* Prepares to run nested-guest code in AMD-V and we've committed to doing so. This
3942	* means there is no backing out to ring-3 or anywhere else at this point.
3943	*
3944	* @param pVM The cross context VM structure.
3945	* @param pVCpu The cross context virtual CPU structure.
3946	* @param pCtx Pointer to the guest-CPU context.
3947	* @param pSvmTransient Pointer to the SVM transient structure.
3948	*
3949	* @remarks Called with preemption disabled.
3950	* @remarks No-long-jump zone!!!
3951	*/
3952	static void hmR0SvmPreRunGuestCommittedNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3953	{
3954	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3955	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3956	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3957	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
3958
3959	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3960	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3961
3962	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3963	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcbNstGst);
3964
3965	if ( pVCpu->hm.s.fPreloadGuestFpu
3966	&& !CPUMIsGuestFPUStateActive(pVCpu))
3967	{
3968	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
3969	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3970	}
3971
3972	/* Load the state shared between host and nested-guest (FPU, debug). */
3973	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3974	hmR0SvmLoadSharedState(pVCpu, pVmcbNstGst, pCtx);
3975
3976	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3977	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3978
3979	/* Setup TSC offsetting. */
3980	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
3981	if ( pSvmTransient->fUpdateTscOffsetting
3982	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
3983	{
3984	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcbNstGst);
3985	pSvmTransient->fUpdateTscOffsetting = false;
3986	}
3987
3988	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3989	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3990	pVmcbNstGst->ctrl.u64VmcbCleanBits = 0;
3991
3992	/* Store status of the shared guest-host state at the time of VMRUN. */
3993	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
3994	if (CPUMIsGuestInLongModeEx(pCtx))
3995	{
3996	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3997	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3998	}
3999	else
4000	#endif
4001	{
4002	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4003	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4004	}
4005	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
4006
4007	/* The TLB flushing would've already been setup by the nested-hypervisor. */
4008	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4009	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcbNstGst);
4010	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
4011
4012	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4013
4014	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4015	to start executing. */
4016
4017	/*
4018	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4019	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4020	*
4021	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4022	*/
4023	uint8_t pbMsrBitmap = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4024	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4025	&& !(pVmcbNstGst->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4026	{
4027	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4028	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4029	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4030	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4031	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4032	pSvmTransient->fRestoreTscAuxMsr = true;
4033	}
4034	else
4035	{
4036	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4037	pSvmTransient->fRestoreTscAuxMsr = false;
4038	}
4039
4040	/*
4041	* If VMCB Clean bits isn't supported by the CPU or exposed by the guest,
4042	* mark all state-bits as dirty indicating to the CPU to re-load from VMCB.
4043	*/
4044	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
4045	if (!fSupportsVmcbCleanBits)
4046	pVmcbNstGst->ctrl.u64VmcbCleanBits = 0;
4047	}
4048	#endif
4049
4050
4051	/**
4052	* Prepares to run guest code in AMD-V and we've committed to doing so. This
4053	* means there is no backing out to ring-3 or anywhere else at this
4054	* point.
4055	*
4056	* @param pVM The cross context VM structure.
4057	* @param pVCpu The cross context virtual CPU structure.
4058	* @param pCtx Pointer to the guest-CPU context.
4059	* @param pSvmTransient Pointer to the SVM transient structure.
4060	*
4061	* @remarks Called with preemption disabled.
4062	* @remarks No-long-jump zone!!!
4063	*/
4064	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4065	{
4066	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4067	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4068	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4069	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
4070
4071	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4072	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4073
4074	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4075	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcb);
4076
4077	if ( pVCpu->hm.s.fPreloadGuestFpu
4078	&& !CPUMIsGuestFPUStateActive(pVCpu))
4079	{
4080	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4081	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4082	}
4083
4084	/* Load the state shared between host and guest (FPU, debug). */
4085	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
4086	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
4087
4088	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
4089	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
4090
4091	/* Setup TSC offsetting. */
4092	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
4093	if ( pSvmTransient->fUpdateTscOffsetting
4094	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
4095	{
4096	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcb);
4097	pSvmTransient->fUpdateTscOffsetting = false;
4098	}
4099
4100	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4101	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
4102	pVmcb->ctrl.u64VmcbCleanBits = 0;
4103
4104	/* Store status of the shared guest-host state at the time of VMRUN. */
4105	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4106	if (CPUMIsGuestInLongModeEx(pCtx))
4107	{
4108	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4109	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4110	}
4111	else
4112	#endif
4113	{
4114	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4115	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4116	}
4117	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
4118
4119	/* Flush the appropriate tagged-TLB entries. */
4120	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4121	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcb);
4122	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
4123
4124	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4125
4126	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4127	to start executing. */
4128
4129	/*
4130	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4131	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4132	*
4133	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4134	*/
4135	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4136	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4137	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4138	{
4139	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4140	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4141	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4142	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4143	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4144	pSvmTransient->fRestoreTscAuxMsr = true;
4145	}
4146	else
4147	{
4148	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4149	pSvmTransient->fRestoreTscAuxMsr = false;
4150	}
4151
4152	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
4153	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
4154	if (!fSupportsVmcbCleanBits)
4155	pVmcb->ctrl.u64VmcbCleanBits = 0;
4156	}
4157
4158
4159	/**
4160	* Wrapper for running the guest code in AMD-V.
4161	*
4162	* @returns VBox strict status code.
4163	* @param pVM The cross context VM structure.
4164	* @param pVCpu The cross context virtual CPU structure.
4165	* @param pCtx Pointer to the guest-CPU context.
4166	*
4167	* @remarks No-long-jump zone!!!
4168	*/
4169	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4170	{
4171	/*
4172	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4173	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4174	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4175	*/
4176	#ifdef VBOX_WITH_KERNEL_USING_XMM
4177	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4178	pVCpu->hm.s.svm.pfnVMRun);
4179	#else
4180	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4181	#endif
4182	}
4183
4184
4185	#ifdef VBOX_WITH_NESTED_HWVIRT
4186	/**
4187	* Wrapper for running the nested-guest code in AMD-V.
4188	*
4189	* @returns VBox strict status code.
4190	* @param pVM The cross context VM structure.
4191	* @param pVCpu The cross context virtual CPU structure.
4192	* @param pCtx Pointer to the guest-CPU context.
4193	*
4194	* @remarks No-long-jump zone!!!
4195	*/
4196	DECLINLINE(int) hmR0SvmRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4197	{
4198	/*
4199	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4200	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4201	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4202	*/
4203	#ifdef VBOX_WITH_KERNEL_USING_XMM
4204	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4205	pVCpu->hm.s.svm.pfnVMRun);
4206	#else
4207	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4208	#endif
4209	}
4210
4211
4212	/**
4213	* Performs some essential restoration of state after running nested-guest code in
4214	* AMD-V.
4215	*
4216	* @param pVM The cross context VM structure.
4217	* @param pVCpu The cross context virtual CPU structure.
4218	* @param pMixedCtx Pointer to the nested-guest-CPU context. The data maybe
4219	* out-of-sync. Make sure to update the required fields
4220	* before using them.
4221	* @param pSvmTransient Pointer to the SVM transient structure.
4222	* @param rcVMRun Return code of VMRUN.
4223	*
4224	* @remarks Called with interrupts disabled.
4225	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4226	* unconditionally when it is safe to do so.
4227	*/
4228	static void hmR0SvmPostRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4229	{
4230	RT_NOREF(pVM);
4231	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4232
4233	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4234	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4235
4236	/* TSC read must be done early for maximum accuracy. */
4237	PSVMVMCB pVmcbNstGst = pMixedCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4238	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4239	if (!(pVmcbNstGstCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4240	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcbNstGstCtrl->u64TSCOffset);
4241
4242	if (pSvmTransient->fRestoreTscAuxMsr)
4243	{
4244	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4245	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4246	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4247	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4248	}
4249
4250	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4251	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4252	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4253
4254	Assert(!(ASMGetFlags() & X86_EFL_IF));
4255	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4256	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4257
4258	/* Mark the VMCB-state cache as unmodified by VMM. */
4259	pVmcbNstGstCtrl->u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;
4260
4261	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4262	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4263	{
4264	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4265	return;
4266	}
4267
4268	pSvmTransient->u64ExitCode = pVmcbNstGstCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4269	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcbNstGstCtrl->u64ExitCode);/* Update the #VMEXIT history array. */
4270	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4271	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4272
4273	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
4274	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcbNstGst); /* Save the nested-guest state from the VMCB to the
4275	guest-CPU context. */
4276	}
4277	#endif
4278
4279	/**
4280	* Performs some essential restoration of state after running guest code in
4281	* AMD-V.
4282	*
4283	* @param pVM The cross context VM structure.
4284	* @param pVCpu The cross context virtual CPU structure.
4285	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
4286	* out-of-sync. Make sure to update the required fields
4287	* before using them.
4288	* @param pSvmTransient Pointer to the SVM transient structure.
4289	* @param rcVMRun Return code of VMRUN.
4290	*
4291	* @remarks Called with interrupts disabled.
4292	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4293	* unconditionally when it is safe to do so.
4294	*/
4295	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4296	{
4297	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4298
4299	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4300	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4301
4302	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4303	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4304
4305	/* TSC read must be done early for maximum accuracy. */
4306	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4307	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
4308
4309	if (pSvmTransient->fRestoreTscAuxMsr)
4310	{
4311	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4312	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4313	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4314	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4315	}
4316
4317	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4318	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4319	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4320
4321	Assert(!(ASMGetFlags() & X86_EFL_IF));
4322	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4323	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4324
4325	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4326	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4327	{
4328	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4329	return;
4330	}
4331
4332	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
4333	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
4334	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4335	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4336
4337	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcb); /* Save the guest state from the VMCB to the guest-CPU context. */
4338
4339	if (RT_LIKELY(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID))
4340	{
4341	if (pVCpu->hm.s.svm.fSyncVTpr)
4342	{
4343	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4344	if ( pVM->hm.s.fTPRPatchingActive
4345	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4346	{
4347	int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
4348	AssertRC(rc);
4349	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4350	}
4351	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
4352	{
4353	int rc = APICSetTpr(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
4354	AssertRC(rc);
4355	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4356	}
4357	}
4358	}
4359	}
4360
4361
4362	/**
4363	* Runs the guest code using AMD-V.
4364	*
4365	* @returns VBox status code.
4366	* @param pVM The cross context VM structure.
4367	* @param pVCpu The cross context virtual CPU structure.
4368	* @param pCtx Pointer to the guest-CPU context.
4369	* @param pcLoops Pointer to the number of executed loops.
4370	*/
4371	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4372	{
4373	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4374	Assert(pcLoops);
4375	Assert(*pcLoops <= cMaxResumeLoops);
4376
4377	SVMTRANSIENT SvmTransient;
4378	SvmTransient.fUpdateTscOffsetting = true;
4379
4380	int rc = VERR_INTERNAL_ERROR_5;
4381	for (;;)
4382	{
4383	Assert(!HMR0SuspendPending());
4384	HMSVM_ASSERT_CPU_SAFE();
4385
4386	/* Preparatory work for running guest code, this may force us to return
4387	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4388	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4389	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4390	if (rc != VINF_SUCCESS)
4391	break;
4392
4393	/*
4394	* No longjmps to ring-3 from this point on!!!
4395	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4396	* This also disables flushing of the R0-logger instance (if any).
4397	*/
4398	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4399	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4400
4401	/* Restore any residual host-state and save any bits shared between host
4402	and guest into the guest-CPU state. Re-enables interrupts! */
4403	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4404
4405	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4406	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4407	{
4408	if (rc == VINF_SUCCESS)
4409	rc = VERR_SVM_INVALID_GUEST_STATE;
4410	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4411	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4412	break;
4413	}
4414
4415	/* Handle the #VMEXIT. */
4416	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4417	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4418	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4419	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4420	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4421	if (rc != VINF_SUCCESS)
4422	break;
4423	if (++(*pcLoops) >= cMaxResumeLoops)
4424	{
4425	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4426	rc = VINF_EM_RAW_INTERRUPT;
4427	break;
4428	}
4429	}
4430
4431	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4432	return rc;
4433	}
4434
4435
4436	/**
4437	* Runs the guest code using AMD-V in single step mode.
4438	*
4439	* @returns VBox status code.
4440	* @param pVM The cross context VM structure.
4441	* @param pVCpu The cross context virtual CPU structure.
4442	* @param pCtx Pointer to the guest-CPU context.
4443	* @param pcLoops Pointer to the number of executed loops.
4444	*/
4445	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4446	{
4447	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4448	Assert(pcLoops);
4449	Assert(*pcLoops <= cMaxResumeLoops);
4450
4451	SVMTRANSIENT SvmTransient;
4452	SvmTransient.fUpdateTscOffsetting = true;
4453
4454	uint16_t uCsStart = pCtx->cs.Sel;
4455	uint64_t uRipStart = pCtx->rip;
4456
4457	int rc = VERR_INTERNAL_ERROR_5;
4458	for (;;)
4459	{
4460	Assert(!HMR0SuspendPending());
4461	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4462	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4463	(unsigned)RTMpCpuId(), *pcLoops));
4464
4465	/* Preparatory work for running guest code, this may force us to return
4466	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4467	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4468	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4469	if (rc != VINF_SUCCESS)
4470	break;
4471
4472	/*
4473	* No longjmps to ring-3 from this point on!!!
4474	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4475	* This also disables flushing of the R0-logger instance (if any).
4476	*/
4477	VMMRZCallRing3Disable(pVCpu);
4478	VMMRZCallRing3RemoveNotification(pVCpu);
4479	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4480
4481	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4482
4483	/*
4484	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
4485	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
4486	*/
4487	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4488	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4489	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4490	{
4491	if (rc == VINF_SUCCESS)
4492	rc = VERR_SVM_INVALID_GUEST_STATE;
4493	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4494	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4495	return rc;
4496	}
4497
4498	/* Handle the #VMEXIT. */
4499	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4500	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4501	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4502	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4503	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4504	if (rc != VINF_SUCCESS)
4505	break;
4506	if (++(*pcLoops) >= cMaxResumeLoops)
4507	{
4508	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4509	rc = VINF_EM_RAW_INTERRUPT;
4510	break;
4511	}
4512
4513	/*
4514	* Did the RIP change, if so, consider it a single step.
4515	* Otherwise, make sure one of the TFs gets set.
4516	*/
4517	if ( pCtx->rip != uRipStart
4518	\|\| pCtx->cs.Sel != uCsStart)
4519	{
4520	rc = VINF_EM_DBG_STEPPED;
4521	break;
4522	}
4523	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4524	}
4525
4526	/*
4527	* Clear the X86_EFL_TF if necessary.
4528	*/
4529	if (pVCpu->hm.s.fClearTrapFlag)
4530	{
4531	pVCpu->hm.s.fClearTrapFlag = false;
4532	pCtx->eflags.Bits.u1TF = 0;
4533	}
4534
4535	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4536	return rc;
4537	}
4538
4539	#ifdef VBOX_WITH_NESTED_HWVIRT
4540	/**
4541	* Runs the nested-guest code using AMD-V.
4542	*
4543	* @returns VBox status code.
4544	* @param pVM The cross context VM structure.
4545	* @param pVCpu The cross context virtual CPU structure.
4546	* @param pCtx Pointer to the guest-CPU context.
4547	* @param pcLoops Pointer to the number of executed loops. If we're switching
4548	* from the guest-code execution loop to this nested-guest
4549	* execution loop pass the remainder value, else pass 0.
4550	*/
4551	static int hmR0SvmRunGuestCodeNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4552	{
4553	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4554	Assert(pcLoops);
4555	Assert(*pcLoops <= pVM->hm.s.cMaxResumeLoops);
4556
4557	SVMTRANSIENT SvmTransient;
4558	SvmTransient.fUpdateTscOffsetting = true;
4559
4560	int rc = VERR_INTERNAL_ERROR_4;
4561	for (;;)
4562	{
4563	Assert(!HMR0SuspendPending());
4564	HMSVM_ASSERT_CPU_SAFE();
4565
4566	/* Preparatory work for running nested-guest code, this may force us to return
4567	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4568	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4569	rc = hmR0SvmPreRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient);
4570	if (rc != VINF_SUCCESS)
4571	break;
4572
4573	/*
4574	* No longjmps to ring-3 from this point on!!!
4575	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4576	* This also disables flushing of the R0-logger instance (if any).
4577	*/
4578	hmR0SvmPreRunGuestCommittedNested(pVM, pVCpu, pCtx, &SvmTransient);
4579
4580	rc = hmR0SvmRunGuestNested(pVM, pVCpu, pCtx);
4581
4582	/* Restore any residual host-state and save any bits shared between host
4583	and guest into the guest-CPU state. Re-enables interrupts! */
4584	hmR0SvmPostRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient, rc);
4585
4586	/** @todo This needs some work... we probably should cause a \#VMEXIT on
4587	* SVM_EXIT_INVALID and handle rc != VINF_SUCCESS differently. */
4588	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4589	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4590	{
4591	if (rc == VINF_SUCCESS)
4592	rc = VERR_SVM_INVALID_GUEST_STATE;
4593	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4594	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4595	break;
4596	}
4597
4598	/* Handle the #VMEXIT. */
4599	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4600	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4601	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4602	rc = hmR0SvmHandleExitNested(pVCpu, pCtx, &SvmTransient);
4603	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4604	if (rc != VINF_SUCCESS)
4605	break;
4606	if (++(*pcLoops) >= pVM->hm.s.cMaxResumeLoops)
4607	{
4608	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4609	rc = VINF_EM_RAW_INTERRUPT;
4610	break;
4611	}
4612
4613	/** @todo handle single-stepping */
4614	}
4615
4616	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4617	return rc;
4618	}
4619	#endif
4620
4621
4622	/**
4623	* Runs the guest code using AMD-V.
4624	*
4625	* @returns Strict VBox status code.
4626	* @param pVM The cross context VM structure.
4627	* @param pVCpu The cross context virtual CPU structure.
4628	* @param pCtx Pointer to the guest-CPU context.
4629	*/
4630	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4631	{
4632	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4633	HMSVM_ASSERT_PREEMPT_SAFE();
4634	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
4635
4636	uint32_t cLoops = 0;
4637	int rc;
4638	#ifdef VBOX_WITH_NESTED_HWVIRT
4639	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4640	#endif
4641	{
4642	if (!pVCpu->hm.s.fSingleInstruction)
4643	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx, &cLoops);
4644	else
4645	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx, &cLoops);
4646	}
4647	#ifdef VBOX_WITH_NESTED_HWVIRT
4648	else
4649	{
4650	rc = VINF_SVM_VMRUN;
4651	}
4652
4653	/* Re-check the nested-guest condition here as we may be transitioning from the normal
4654	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
4655	if (rc == VINF_SVM_VMRUN)
4656	{
4657	rc = hmR0SvmRunGuestCodeNested(pVM, pVCpu, pCtx, &cLoops);
4658	if (rc == VINF_SVM_VMEXIT)
4659	rc = VINF_SUCCESS;
4660	}
4661	#endif
4662
4663	/* Fixup error codes. */
4664	if (rc == VERR_EM_INTERPRETER)
4665	rc = VINF_EM_RAW_EMULATE_INSTR;
4666	else if (rc == VINF_EM_RESET)
4667	rc = VINF_EM_TRIPLE_FAULT;
4668
4669	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4670	rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
4671	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4672	return rc;
4673	}
4674
4675
4676	#ifdef VBOX_WITH_NESTED_HWVIRT
4677	/**
4678	* Determines whether an IOIO intercept is active for the nested-guest or not.
4679	*
4680	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4681	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4682	*/
4683	static bool hmR0SvmIsIoInterceptActive(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4684	{
4685	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4686	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4687	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4688	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4689	const uint8_t iEffSeg = pIoExitInfo->n.u3SEG;
4690	const bool fRep = pIoExitInfo->n.u1REP;
4691	const bool fStrIo = pIoExitInfo->n.u1STR;
4692
4693	return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4694	NULL /* pIoExitInfo */);
4695	}
4696
4697
4698	/**
4699	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4700	* SVM_EXIT_INVALID).
4701	*
4702	* @returns VBox status code (informational status codes included).
4703	* @param pVCpu The cross context virtual CPU structure.
4704	* @param pCtx Pointer to the guest-CPU context.
4705	* @param pSvmTransient Pointer to the SVM transient structure.
4706	*/
4707	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4708	{
4709	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4710	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4711	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4712
4713	#define HM_SVM_VMEXIT_NESTED(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4714	VBOXSTRICTRC_TODO(IEMExecSvmVmexit(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2))
4715
4716	/*
4717	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected
4718	* by the nested-guest. If it isn't, it should be handled by the (outer) guest.
4719	*/
4720	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4721	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4722	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
4723	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
4724	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
4725
4726	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
4727	switch (uExitCode)
4728	{
4729	case SVM_EXIT_CPUID:
4730	{
4731	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
4732	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4733	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
4734	}
4735
4736	case SVM_EXIT_RDTSC:
4737	{
4738	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
4739	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4740	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
4741	}
4742
4743	case SVM_EXIT_RDTSCP:
4744	{
4745	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
4746	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4747	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
4748	}
4749
4750
4751	case SVM_EXIT_MONITOR:
4752	{
4753	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
4754	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4755	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
4756	}
4757
4758	case SVM_EXIT_MWAIT:
4759	{
4760	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
4761	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4762	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
4763	}
4764
4765	case SVM_EXIT_HLT:
4766	{
4767	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
4768	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4769	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
4770	}
4771
4772	case SVM_EXIT_MSR:
4773	{
4774	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
4775	{
4776	uint32_t const idMsr = pCtx->ecx;
4777	uint16_t offMsrpm;
4778	uint32_t uMsrpmBit;
4779	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
4780	if (RT_SUCCESS(rc))
4781	{
4782	void const *pvMsrBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4783	bool const fInterceptRead = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit);
4784	bool const fInterceptWrite = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit + 1);
4785
4786	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4787	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
4788	{
4789	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4790	}
4791	}
4792	else
4793	{
4794	/*
4795	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
4796	* See AMD-V spec. "15.11 MSR Intercepts".
4797	*/
4798	Assert(rc == VERR_OUT_OF_RANGE);
4799	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4800	}
4801	}
4802	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
4803	}
4804
4805	case SVM_EXIT_IOIO:
4806	{
4807	/*
4808	* Figure out if the IO port access is intercepted by the nested-guest.
4809	*/
4810	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
4811	{
4812	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
4813	SVMIOIOEXITINFO IoExitInfo;
4814	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
4815	bool const fIntercept = hmR0SvmIsIoInterceptActive(pvIoBitmap, &IoExitInfo);
4816	if (fIntercept)
4817	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4818	}
4819	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
4820	}
4821
4822	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
4823	{
4824	PVM pVM = pVCpu->CTX_SUFF(pVM);
4825	if (pVM->hm.s.fNestedPaging)
4826	{
4827	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
4828	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
4829
4830	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
4831	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
4832	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
4833
4834	/* If the nested-guest is not intercepting #PFs, forward the #PF to the nested-guest. */
4835	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4836	return VINF_SUCCESS;
4837	}
4838	return hmR0SvmExitXcptPFNested(pVCpu, pCtx,pSvmTransient);
4839	}
4840
4841	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
4842	{
4843	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_NM))
4844	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4845	hmR0SvmSetPendingXcptNM(pVCpu);
4846	return VINF_SUCCESS;
4847	}
4848
4849	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
4850	{
4851	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
4852	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4853	hmR0SvmSetPendingXcptUD(pVCpu);
4854	return VINF_SUCCESS;
4855	}
4856
4857	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
4858	{
4859	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
4860	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4861	hmR0SvmSetPendingXcptMF(pVCpu);
4862	return VINF_SUCCESS;
4863	}
4864
4865	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
4866	{
4867	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
4868	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4869	return hmR0SvmNestedExitXcptDB(pVCpu, pCtx, pSvmTransient);
4870	}
4871
4872	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
4873	{
4874	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
4875	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4876	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
4877	}
4878
4879	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
4880	{
4881	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
4882	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4883	return hmR0SvmNestedExitXcptBP(pVCpu, pCtx, pSvmTransient);
4884	}
4885
4886	case SVM_EXIT_READ_CR0:
4887	case SVM_EXIT_READ_CR3:
4888	case SVM_EXIT_READ_CR4:
4889	{
4890	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
4891	if (HMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
4892	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4893	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
4894	}
4895
4896	case SVM_EXIT_WRITE_CR0:
4897	case SVM_EXIT_WRITE_CR3:
4898	case SVM_EXIT_WRITE_CR4:
4899	case SVM_EXIT_WRITE_CR8: /** @todo Shouldn't writes to CR8 go to V_TPR instead since we run with V_INTR_MASKING set?? */
4900	{
4901	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
4902	Log4(("hmR0SvmHandleExitNested: Write CRx: u16InterceptWrCRx=%#x u64ExitCode=%#RX64 %#x\n",
4903	pVmcbNstGstCtrl->u16InterceptWrCRx, pSvmTransient->u64ExitCode, uCr));
4904
4905	if (HMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
4906	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4907	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
4908	}
4909
4910	case SVM_EXIT_PAUSE:
4911	{
4912	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
4913	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4914	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
4915	}
4916
4917	case SVM_EXIT_VINTR:
4918	{
4919	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
4920	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4921	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
4922	}
4923
4924	case SVM_EXIT_INTR:
4925	{
4926	/* We shouldn't direct physical interrupts to the nested-guest. */
4927	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
4928	}
4929
4930	case SVM_EXIT_FERR_FREEZE:
4931	{
4932	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
4933	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4934	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
4935	}
4936
4937	case SVM_EXIT_NMI:
4938	{
4939	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
4940	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4941	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
4942	}
4943
4944	case SVM_EXIT_INVLPG:
4945	{
4946	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
4947	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4948	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
4949	}
4950
4951	case SVM_EXIT_WBINVD:
4952	{
4953	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
4954	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4955	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
4956	}
4957
4958	case SVM_EXIT_INVD:
4959	{
4960	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
4961	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4962	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
4963	}
4964
4965	case SVM_EXIT_RDPMC:
4966	{
4967	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
4968	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4969	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
4970	}
4971
4972	default:
4973	{
4974	switch (uExitCode)
4975	{
4976	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
4977	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
4978	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
4979	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
4980	{
4981	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
4982	if (HMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
4983	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4984	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4985	}
4986
4987	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
4988	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
4989	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
4990	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
4991	{
4992	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
4993	if (HMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
4994	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4995	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
4996	}
4997
4998	/* The exceptions not handled here are already handled individually above (as they occur more frequently). */
4999	case SVM_EXIT_EXCEPTION_0: /case SVM_EXIT_EXCEPTION_1:/ case SVM_EXIT_EXCEPTION_2:
5000	/case SVM_EXIT_EXCEPTION_3:/ case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5:
5001	/case SVM_EXIT_EXCEPTION_6:/ /case SVM_EXIT_EXCEPTION_7:/ case SVM_EXIT_EXCEPTION_8:
5002	case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
5003	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: /case SVM_EXIT_EXCEPTION_14:/
5004	case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: /case SVM_EXIT_EXCEPTION_17:/
5005	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_20:
5006	case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
5007	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26:
5008	case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29:
5009	case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5010	{
5011	uint8_t const uVector = uExitCode - SVM_EXIT_EXCEPTION_0;
5012	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5013	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5014	/** @todo Write hmR0SvmExitXcptGeneric! */
5015	return VERR_NOT_IMPLEMENTED;
5016	}
5017
5018	case SVM_EXIT_XSETBV:
5019	{
5020	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5021	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5022	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5023	}
5024
5025	case SVM_EXIT_TASK_SWITCH:
5026	{
5027	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5028	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5029	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5030	}
5031
5032	case SVM_EXIT_IRET:
5033	{
5034	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5035	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5036	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5037	}
5038
5039	case SVM_EXIT_SHUTDOWN:
5040	{
5041	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5042	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5043	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5044	}
5045
5046	case SVM_EXIT_SMI:
5047	{
5048	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SMI))
5049	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5050	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5051	}
5052
5053	case SVM_EXIT_INIT:
5054	{
5055	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INIT))
5056	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5057	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5058	}
5059
5060	case SVM_EXIT_VMMCALL:
5061	{
5062	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5063	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5064	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5065	}
5066
5067	case SVM_EXIT_CLGI:
5068	{
5069	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5070	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5071	return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5072	}
5073
5074	case SVM_EXIT_STGI:
5075	{
5076	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5077	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5078	return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5079	}
5080
5081	case SVM_EXIT_VMLOAD:
5082	{
5083	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5084	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5085	return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5086	}
5087
5088	case SVM_EXIT_VMSAVE:
5089	{
5090	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5091	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5092	return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5093	}
5094
5095	case SVM_EXIT_INVLPGA:
5096	{
5097	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5098	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5099	return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5100	}
5101
5102	case SVM_EXIT_VMRUN:
5103	{
5104	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5105	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5106	return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5107	}
5108
5109	case SVM_EXIT_RSM:
5110	{
5111	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5112	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5113	hmR0SvmSetPendingXcptUD(pVCpu);
5114	return VINF_SUCCESS;
5115	}
5116
5117	case SVM_EXIT_SKINIT:
5118	{
5119	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5120	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5121	hmR0SvmSetPendingXcptUD(pVCpu);
5122	return VINF_SUCCESS;
5123	}
5124
5125	case SVM_EXIT_NPF:
5126	{
5127	/* We don't yet support nested-paging for nested-guests, so this should never really happen. */
5128	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5129	}
5130
5131	default:
5132	{
5133	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5134	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5135	return VERR_SVM_UNKNOWN_EXIT;
5136	}
5137	}
5138	}
5139	}
5140	/* not reached */
5141
5142	#undef HM_SVM_VMEXIT_NESTED
5143	}
5144	#endif
5145
5146
5147	/**
5148	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5149	*
5150	* @returns VBox status code (informational status codes included).
5151	* @param pVCpu The cross context virtual CPU structure.
5152	* @param pCtx Pointer to the guest-CPU context.
5153	* @param pSvmTransient Pointer to the SVM transient structure.
5154	*/
5155	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5156	{
5157	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5158	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5159
5160	/*
5161	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
5162	* normal workloads (for some definition of "normal").
5163	*/
5164	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
5165	switch (pSvmTransient->u64ExitCode)
5166	{
5167	case SVM_EXIT_NPF:
5168	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
5169
5170	case SVM_EXIT_IOIO:
5171	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5172
5173	case SVM_EXIT_RDTSC:
5174	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5175
5176	case SVM_EXIT_RDTSCP:
5177	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5178
5179	case SVM_EXIT_CPUID:
5180	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5181
5182	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
5183	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
5184
5185	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
5186	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
5187
5188	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
5189	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
5190
5191	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
5192	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
5193
5194	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
5195	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
5196
5197	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
5198	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5199
5200	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
5201	return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient);
5202
5203	case SVM_EXIT_MONITOR:
5204	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5205
5206	case SVM_EXIT_MWAIT:
5207	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5208
5209	case SVM_EXIT_HLT:
5210	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5211
5212	case SVM_EXIT_READ_CR0:
5213	case SVM_EXIT_READ_CR3:
5214	case SVM_EXIT_READ_CR4:
5215	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5216
5217	case SVM_EXIT_WRITE_CR0:
5218	case SVM_EXIT_WRITE_CR3:
5219	case SVM_EXIT_WRITE_CR4:
5220	case SVM_EXIT_WRITE_CR8:
5221	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5222
5223	case SVM_EXIT_PAUSE:
5224	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5225
5226	case SVM_EXIT_VMMCALL:
5227	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5228
5229	case SVM_EXIT_VINTR:
5230	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
5231
5232	case SVM_EXIT_INTR:
5233	case SVM_EXIT_FERR_FREEZE:
5234	case SVM_EXIT_NMI:
5235	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5236
5237	case SVM_EXIT_MSR:
5238	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5239
5240	case SVM_EXIT_INVLPG:
5241	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5242
5243	case SVM_EXIT_WBINVD:
5244	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5245
5246	case SVM_EXIT_INVD:
5247	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5248
5249	case SVM_EXIT_RDPMC:
5250	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5251
5252	default:
5253	{
5254	switch (pSvmTransient->u64ExitCode)
5255	{
5256	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5257	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5258	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5259	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5260	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5261
5262	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5263	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5264	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5265	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5266	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5267
5268	case SVM_EXIT_XSETBV:
5269	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5270
5271	case SVM_EXIT_TASK_SWITCH:
5272	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5273
5274	case SVM_EXIT_IRET:
5275	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5276
5277	case SVM_EXIT_SHUTDOWN:
5278	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5279
5280	case SVM_EXIT_SMI:
5281	case SVM_EXIT_INIT:
5282	{
5283	/*
5284	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5285	* If it ever does, we want to know about it so log the exit code and bail.
5286	*/
5287	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5288	}
5289
5290	#ifdef VBOX_WITH_NESTED_HWVIRT
5291	case SVM_EXIT_CLGI: return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5292	case SVM_EXIT_STGI: return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5293	case SVM_EXIT_VMLOAD: return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5294	case SVM_EXIT_VMSAVE: return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5295	case SVM_EXIT_INVLPGA: return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5296	case SVM_EXIT_VMRUN: return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5297	#else
5298	case SVM_EXIT_CLGI:
5299	case SVM_EXIT_STGI:
5300	case SVM_EXIT_VMLOAD:
5301	case SVM_EXIT_VMSAVE:
5302	case SVM_EXIT_INVLPGA:
5303	case SVM_EXIT_VMRUN:
5304	#endif
5305	case SVM_EXIT_RSM:
5306	case SVM_EXIT_SKINIT:
5307	{
5308	hmR0SvmSetPendingXcptUD(pVCpu);
5309	return VINF_SUCCESS;
5310	}
5311
5312	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5313	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
5314	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
5315	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
5316	/* SVM_EXIT_EXCEPTION_3: / / X86_XCPT_BP - Handled above. */
5317	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
5318	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
5319	/* SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
5320	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
5321	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
5322	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
5323	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_TS */
5324	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_NP */
5325	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_SS */
5326	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_GP */
5327	/* SVM_EXIT_EXCEPTION_14: / / X86_XCPT_PF - Handled above. */
5328	case SVM_EXIT_EXCEPTION_15: /* Reserved. */
5329	/* SVM_EXIT_EXCEPTION_16: / / X86_XCPT_MF - Handled above. */
5330	/* SVM_EXIT_EXCEPTION_17: / / X86_XCPT_AC - Handled above. */
5331	case SVM_EXIT_EXCEPTION_18: /* X86_XCPT_MC */
5332	case SVM_EXIT_EXCEPTION_19: /* X86_XCPT_XF */
5333	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22:
5334	case SVM_EXIT_EXCEPTION_23: case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25:
5335	case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28:
5336	case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5337	{
5338	/** @todo r=ramshankar; We should be doing
5339	* HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY here! */
5340	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5341	SVMEVENT Event;
5342	Event.u = 0;
5343	Event.n.u1Valid = 1;
5344	Event.n.u3Type = SVM_EVENT_EXCEPTION;
5345	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
5346
5347	switch (Event.n.u8Vector)
5348	{
5349	case X86_XCPT_DE:
5350	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
5351	break;
5352
5353	case X86_XCPT_NP:
5354	Event.n.u1ErrorCodeValid = 1;
5355	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
5356	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
5357	break;
5358
5359	case X86_XCPT_SS:
5360	Event.n.u1ErrorCodeValid = 1;
5361	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
5362	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
5363	break;
5364
5365	case X86_XCPT_GP:
5366	Event.n.u1ErrorCodeValid = 1;
5367	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
5368	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
5369	break;
5370
5371	default:
5372	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
5373	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
5374	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
5375	}
5376
5377	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
5378	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
5379	return VINF_SUCCESS;
5380	}
5381	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5382
5383	default:
5384	{
5385	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
5386	pVCpu->hm.s.u32HMError = u32ExitCode;
5387	return VERR_SVM_UNKNOWN_EXIT;
5388	}
5389	}
5390	}
5391	}
5392	/* not reached */
5393	}
5394
5395
5396	#ifdef DEBUG
5397	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5398	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5399	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5400
5401	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5402	do \
5403	{ \
5404	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5405	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5406	} while (0)
5407
5408	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
5409	do { \
5410	AssertPtr(pVCpu); \
5411	AssertPtr(pCtx); \
5412	AssertPtr(pSvmTransient); \
5413	Assert(ASMIntAreEnabled()); \
5414	HMSVM_ASSERT_PREEMPT_SAFE(); \
5415	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5416	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
5417	HMSVM_ASSERT_PREEMPT_SAFE(); \
5418	if (VMMR0IsLogFlushDisabled(pVCpu)) \
5419	HMSVM_ASSERT_PREEMPT_CPUID(); \
5420	} while (0)
5421	#else /* Release builds */
5422	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
5423	#endif
5424
5425
5426	/**
5427	* Worker for hmR0SvmInterpretInvlpg().
5428	*
5429	* @return VBox status code.
5430	* @param pVCpu The cross context virtual CPU structure.
5431	* @param pCpu Pointer to the disassembler state.
5432	* @param pCtx The guest CPU context.
5433	*/
5434	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
5435	{
5436	DISQPVPARAMVAL Param1;
5437	RTGCPTR GCPtrPage;
5438
5439	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
5440	if (RT_FAILURE(rc))
5441	return VERR_EM_INTERPRETER;
5442
5443	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
5444	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
5445	{
5446	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
5447	return VERR_EM_INTERPRETER;
5448
5449	GCPtrPage = Param1.val.val64;
5450	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
5451	rc = VBOXSTRICTRC_VAL(rc2);
5452	}
5453	else
5454	{
5455	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
5456	rc = VERR_EM_INTERPRETER;
5457	}
5458
5459	return rc;
5460	}
5461
5462
5463	/**
5464	* Interprets INVLPG.
5465	*
5466	* @returns VBox status code.
5467	* @retval VINF_* Scheduling instructions.
5468	* @retval VERR_EM_INTERPRETER Something we can't cope with.
5469	* @retval VERR_* Fatal errors.
5470	*
5471	* @param pVM The cross context VM structure.
5472	* @param pVCpu The cross context virtual CPU structure.
5473	* @param pCtx The guest CPU context.
5474	*
5475	* @remarks Updates the RIP if the instruction was executed successfully.
5476	*/
5477	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
5478	{
5479	/* Only allow 32 & 64 bit code. */
5480	if (CPUMGetGuestCodeBits(pVCpu) != 16)
5481	{
5482	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5483	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
5484	if ( RT_SUCCESS(rc)
5485	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
5486	{
5487	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
5488	if (RT_SUCCESS(rc))
5489	pCtx->rip += pDis->cbInstr;
5490	return rc;
5491	}
5492	else
5493	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5494	}
5495	return VERR_EM_INTERPRETER;
5496	}
5497
5498
5499	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5500	/**
5501	* Gets the IEM exception flags for the specified SVM event.
5502	*
5503	* @returns The IEM exception flags.
5504	* @param pEvent Pointer to the SVM event.
5505	*
5506	* @remarks This function currently only constructs flags required for
5507	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5508	* and CR2 aspects of an exception are not included).
5509	*/
5510	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5511	{
5512	uint8_t const uEventType = pEvent->n.u3Type;
5513	uint32_t fIemXcptFlags;
5514	switch (uEventType)
5515	{
5516	case SVM_EVENT_EXCEPTION:
5517	/*
5518	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5519	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5520	*/
5521	if (pEvent->n.u8Vector == X86_XCPT_BP)
5522	{
5523	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5524	break;
5525	}
5526	if (pEvent->n.u8Vector == X86_XCPT_OF)
5527	{
5528	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5529	break;
5530	}
5531	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5532	RT_FALL_THRU();
5533	case SVM_EVENT_NMI:
5534	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5535	break;
5536
5537	case SVM_EVENT_EXTERNAL_IRQ:
5538	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5539	break;
5540
5541	case SVM_EVENT_SOFTWARE_INT:
5542	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5543	break;
5544
5545	default:
5546	fIemXcptFlags = 0;
5547	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5548	break;
5549	}
5550	return fIemXcptFlags;
5551	}
5552
5553	#else
5554	/**
5555	* Determines if an exception is a contributory exception.
5556	*
5557	* Contributory exceptions are ones which can cause double-faults unless the
5558	* original exception was a benign exception. Page-fault is intentionally not
5559	* included here as it's a conditional contributory exception.
5560	*
5561	* @returns true if the exception is contributory, false otherwise.
5562	* @param uVector The exception vector.
5563	*/
5564	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
5565	{
5566	switch (uVector)
5567	{
5568	case X86_XCPT_GP:
5569	case X86_XCPT_SS:
5570	case X86_XCPT_NP:
5571	case X86_XCPT_TS:
5572	case X86_XCPT_DE:
5573	return true;
5574	default:
5575	break;
5576	}
5577	return false;
5578	}
5579	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5580
5581
5582	/**
5583	* Handle a condition that occurred while delivering an event through the guest
5584	* IDT.
5585	*
5586	* @returns VBox status code (informational error codes included).
5587	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5588	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5589	* continue execution of the guest which will delivery the \#DF.
5590	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5591	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5592	*
5593	* @param pVCpu The cross context virtual CPU structure.
5594	* @param pCtx Pointer to the guest-CPU context.
5595	* @param pSvmTransient Pointer to the SVM transient structure.
5596	*
5597	* @remarks No-long-jump zone!!!
5598	*/
5599	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5600	{
5601	int rc = VINF_SUCCESS;
5602	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
5603
5604	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5605	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5606	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5607
5608	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
5609	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
5610	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5611	{
5612	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5613	IEMXCPTRAISE enmRaise;
5614	IEMXCPTRAISEINFO fRaiseInfo;
5615	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31;
5616	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5617	if (fExitIsHwXcpt)
5618	{
5619	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
5620	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5621	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5622	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5623	}
5624	else
5625	{
5626	/*
5627	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF) then we
5628	* end up here.
5629	*
5630	* If the event was:
5631	* - a software interrupt, we can re-execute the instruction which will regenerate
5632	* the event.
5633	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5634	* - a hardware exception or external interrupt, we re-inject it.
5635	*/
5636	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5637	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5638	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5639	else
5640	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5641	}
5642
5643	switch (enmRaise)
5644	{
5645	case IEMXCPTRAISE_CURRENT_XCPT:
5646	case IEMXCPTRAISE_PREV_EVENT:
5647	{
5648	/* For software interrupts, we shall re-execute the instruction. */
5649	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5650	{
5651	RTGCUINTPTR GCPtrFaultAddress = 0;
5652
5653	/* If we are re-injecting an NMI, clear NMI blocking. */
5654	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5655	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5656
5657	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5658	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5659	pSvmTransient->fVectoringPF = true;
5660	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5661	&& uIdtVector == X86_XCPT_PF)
5662	{
5663	/*
5664	* If the previous exception was a #PF, we need to recover the CR2 value.
5665	* This can't happen with shadow paging.
5666	*/
5667	GCPtrFaultAddress = pCtx->cr2;
5668	}
5669
5670	/*
5671	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5672	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5673	*/
5674	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5675	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5676	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5677
5678	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5679	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5680	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5681	}
5682	break;
5683	}
5684
5685	case IEMXCPTRAISE_REEXEC_INSTR:
5686	{
5687	Assert(rc == VINF_SUCCESS);
5688	break;
5689	}
5690
5691	case IEMXCPTRAISE_DOUBLE_FAULT:
5692	{
5693	/*
5694	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
5695	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
5696	*/
5697	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5698	{
5699	pSvmTransient->fVectoringDoublePF = true;
5700	Assert(rc == VINF_SUCCESS);
5701	}
5702	else
5703	{
5704	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5705	hmR0SvmSetPendingXcptDF(pVCpu);
5706	rc = VINF_HM_DOUBLE_FAULT;
5707	}
5708	break;
5709	}
5710
5711	case IEMXCPTRAISE_TRIPLE_FAULT:
5712	{
5713	rc = VINF_EM_RESET;
5714	break;
5715	}
5716
5717	case IEMXCPTRAISE_CPU_HANG:
5718	{
5719	rc = VERR_EM_GUEST_CPU_HANG;
5720	break;
5721	}
5722
5723	default:
5724	{
5725	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
5726	rc = VERR_SVM_IPE_2;
5727	break;
5728	}
5729	}
5730	#else
5731	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5732
5733	typedef enum
5734	{
5735	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
5736	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
5737	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
5738	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
5739	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
5740	} SVMREFLECTXCPT;
5741
5742	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
5743	bool fReflectingNmi = false;
5744	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
5745	{
5746	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5747	{
5748	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5749
5750	#ifdef VBOX_STRICT
5751	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
5752	&& uExitVector == X86_XCPT_PF)
5753	{
5754	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
5755	}
5756	#endif
5757
5758	if ( uIdtVector == X86_XCPT_BP
5759	\|\| uIdtVector == X86_XCPT_OF)
5760	{
5761	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
5762	}
5763	else if ( uExitVector == X86_XCPT_PF
5764	&& uIdtVector == X86_XCPT_PF)
5765	{
5766	pSvmTransient->fVectoringDoublePF = true;
5767	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
5768	}
5769	else if ( uExitVector == X86_XCPT_AC
5770	&& uIdtVector == X86_XCPT_AC)
5771	{
5772	enmReflect = SVMREFLECTXCPT_HANG;
5773	Log4(("IDT: Nested #AC - Bad guest\n"));
5774	}
5775	else if ( (pVmcb->ctrl.u32InterceptXcpt & HMSVM_CONTRIBUTORY_XCPT_MASK)
5776	&& hmR0SvmIsContributoryXcpt(uExitVector)
5777	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
5778	\|\| uIdtVector == X86_XCPT_PF))
5779	{
5780	enmReflect = SVMREFLECTXCPT_DF;
5781	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
5782	uIdtVector, uExitVector));
5783	}
5784	else if (uIdtVector == X86_XCPT_DF)
5785	{
5786	enmReflect = SVMREFLECTXCPT_TF;
5787	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
5788	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
5789	}
5790	else
5791	enmReflect = SVMREFLECTXCPT_XCPT;
5792	}
5793	else
5794	{
5795	/*
5796	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
5797	* exception to the guest after handling the #VMEXIT.
5798	*/
5799	enmReflect = SVMREFLECTXCPT_XCPT;
5800	}
5801	}
5802	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
5803	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5804	{
5805	enmReflect = SVMREFLECTXCPT_XCPT;
5806	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
5807
5808	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5809	{
5810	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5811	if (uExitVector == X86_XCPT_PF)
5812	{
5813	pSvmTransient->fVectoringPF = true;
5814	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
5815	}
5816	}
5817	}
5818	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
5819
5820	switch (enmReflect)
5821	{
5822	case SVMREFLECTXCPT_XCPT:
5823	{
5824	/* If we are re-injecting the NMI, clear NMI blocking. */
5825	if (fReflectingNmi)
5826	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5827
5828	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5829	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5830	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
5831
5832	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
5833	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
5834	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
5835	break;
5836	}
5837
5838	case SVMREFLECTXCPT_DF:
5839	{
5840	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5841	hmR0SvmSetPendingXcptDF(pVCpu);
5842	rc = VINF_HM_DOUBLE_FAULT;
5843	break;
5844	}
5845
5846	case SVMREFLECTXCPT_TF:
5847	{
5848	rc = VINF_EM_RESET;
5849	break;
5850	}
5851
5852	case SVMREFLECTXCPT_HANG:
5853	{
5854	rc = VERR_EM_GUEST_CPU_HANG;
5855	break;
5856	}
5857
5858	default:
5859	Assert(rc == VINF_SUCCESS);
5860	break;
5861	}
5862	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5863	}
5864	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
5865	NOREF(pCtx);
5866	return rc;
5867	}
5868
5869
5870	/**
5871	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
5872	* supported, otherwise advances the RIP by the number of bytes specified in
5873	* @a cb.
5874	*
5875	* @param pVCpu The cross context virtual CPU structure.
5876	* @param pCtx Pointer to the guest-CPU context.
5877	* @param cb RIP increment value in bytes.
5878	*
5879	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
5880	* when NRIP_SAVE is supported by the CPU, otherwise use
5881	* hmR0SvmAdvanceRipDumb!
5882	*/
5883	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
5884	{
5885	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
5886	if (fSupportsNextRipSave)
5887	{
5888	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
5889	Assert(pVmcb->ctrl.u64NextRIP);
5890	AssertRelease(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb); /* temporary, remove later */
5891	pCtx->rip = pVmcb->ctrl.u64NextRIP;
5892	}
5893	else
5894	pCtx->rip += cb;
5895
5896	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
5897	}
5898
5899
5900	#ifdef VBOX_WITH_NESTED_HWVIRT
5901	/**
5902	* Gets the length of the current instruction if the CPU supports the NRIP_SAVE
5903	* feature. Otherwise, returns the value in @a cbLikely.
5904	*
5905	* @param pVCpu The cross context virtual CPU structure.
5906	* @param pCtx Pointer to the guest-CPU context.
5907	* @param cbLikely The likely instruction length.
5908	*/
5909	DECLINLINE(uint8_t) hmR0SvmGetInstrLengthHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbLikely)
5910	{
5911	Assert(cbLikely <= 15); /* See Intel spec. 2.3.11 "AVX Instruction Length" */
5912	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
5913	if (fSupportsNextRipSave)
5914	{
5915	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
5916	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
5917	Assert(cbInstr == cbLikely);
5918	return cbInstr;
5919	}
5920	return cbLikely;
5921	}
5922	#endif
5923
5924
5925	/**
5926	* Advances the guest RIP by the number of bytes specified in @a cb. This does
5927	* not make use of any hardware features to determine the instruction length.
5928	*
5929	* @param pVCpu The cross context virtual CPU structure.
5930	* @param pCtx Pointer to the guest-CPU context.
5931	* @param cb RIP increment value in bytes.
5932	*/
5933	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
5934	{
5935	pCtx->rip += cb;
5936	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
5937	}
5938	#undef HMSVM_UPDATE_INTR_SHADOW
5939
5940
5941	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5942	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
5943	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5944
5945	/** @name \#VMEXIT handlers.
5946	* @{
5947	*/
5948
5949	/**
5950	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
5951	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
5952	*/
5953	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5954	{
5955	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5956
5957	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
5958	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
5959	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
5960	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
5961
5962	/*
5963	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
5964	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
5965	* interrupt it is until the host actually take the interrupt.
5966	*
5967	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
5968	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
5969	*/
5970	Log4(("hmR0SvmExitIntr: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 CR4=%#RX32\n", pCtx->cs.Sel, pCtx->rip,
5971	pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pCtx->cr4));
5972	Log4(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
5973	"eip=%08x esp=%08x ebp=%08x\n"
5974	"cs=%04x ss=%04x ds=%04x es=%04x fs=%04x gs=%04x efl=%08x\n",
5975	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
5976	pCtx->eip, pCtx->esp, pCtx->ebp,
5977	pCtx->cs.Sel, pCtx->ss.Sel, pCtx->ds.Sel, pCtx->es.Sel, pCtx->fs.Sel, pCtx->gs.Sel, pCtx->eflags.u32));
5978	return VINF_EM_RAW_INTERRUPT;
5979	}
5980
5981
5982	/**
5983	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
5984	*/
5985	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5986	{
5987	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5988
5989	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5990	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
5991	int rc = VINF_SUCCESS;
5992	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5993	return rc;
5994	}
5995
5996
5997	/**
5998	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
5999	*/
6000	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6001	{
6002	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6003
6004	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6005	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
6006	int rc = VINF_SUCCESS;
6007	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6008	return rc;
6009	}
6010
6011
6012	/**
6013	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
6014	*/
6015	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6016	{
6017	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6018	PVM pVM = pVCpu->CTX_SUFF(pVM);
6019	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6020	if (RT_LIKELY(rc == VINF_SUCCESS))
6021	{
6022	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6023	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6024	}
6025	else
6026	{
6027	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
6028	rc = VERR_EM_INTERPRETER;
6029	}
6030	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
6031	return rc;
6032	}
6033
6034
6035	/**
6036	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
6037	*/
6038	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6039	{
6040	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6041	PVM pVM = pVCpu->CTX_SUFF(pVM);
6042	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6043	if (RT_LIKELY(rc == VINF_SUCCESS))
6044	{
6045	pSvmTransient->fUpdateTscOffsetting = true;
6046	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6047	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6048	}
6049	else
6050	{
6051	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
6052	rc = VERR_EM_INTERPRETER;
6053	}
6054	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
6055	return rc;
6056	}
6057
6058
6059	/**
6060	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
6061	*/
6062	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6063	{
6064	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6065	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
6066	if (RT_LIKELY(rc == VINF_SUCCESS))
6067	{
6068	pSvmTransient->fUpdateTscOffsetting = true;
6069	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6070	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6071	}
6072	else
6073	{
6074	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
6075	rc = VERR_EM_INTERPRETER;
6076	}
6077	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
6078	return rc;
6079	}
6080
6081
6082	/**
6083	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
6084	*/
6085	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6086	{
6087	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6088	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6089	if (RT_LIKELY(rc == VINF_SUCCESS))
6090	{
6091	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6092	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6093	}
6094	else
6095	{
6096	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
6097	rc = VERR_EM_INTERPRETER;
6098	}
6099	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
6100	return rc;
6101	}
6102
6103
6104	/**
6105	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
6106	*/
6107	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6108	{
6109	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6110	PVM pVM = pVCpu->CTX_SUFF(pVM);
6111	Assert(!pVM->hm.s.fNestedPaging);
6112	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
6113
6114	bool const fSupportsDecodeAssist = hmR0SvmSupportsDecodeAssist(pVCpu, pCtx);
6115	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6116	if ( fSupportsDecodeAssist
6117	&& fSupportsNextRipSave)
6118	{
6119	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6120	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6121	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6122	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6123	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6124	return VBOXSTRICTRC_VAL(rcStrict);
6125	}
6126
6127	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
6128	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
6129	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6130	return rc;
6131	}
6132
6133
6134	/**
6135	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6136	*/
6137	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6138	{
6139	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6140
6141	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
6142	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6143	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6144	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
6145	if (rc != VINF_SUCCESS)
6146	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6147	return rc;
6148	}
6149
6150
6151	/**
6152	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6153	*/
6154	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6155	{
6156	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6157	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6158	if (RT_LIKELY(rc == VINF_SUCCESS))
6159	{
6160	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6161	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6162	}
6163	else
6164	{
6165	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
6166	rc = VERR_EM_INTERPRETER;
6167	}
6168	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
6169	return rc;
6170	}
6171
6172
6173	/**
6174	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6175	*/
6176	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6177	{
6178	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6179	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6180	int rc = VBOXSTRICTRC_VAL(rc2);
6181	if ( rc == VINF_EM_HALT
6182	\|\| rc == VINF_SUCCESS)
6183	{
6184	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6185
6186	if ( rc == VINF_EM_HALT
6187	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
6188	{
6189	rc = VINF_SUCCESS;
6190	}
6191	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6192	}
6193	else
6194	{
6195	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
6196	rc = VERR_EM_INTERPRETER;
6197	}
6198	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
6199	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
6200	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
6201	return rc;
6202	}
6203
6204
6205	/**
6206	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6207	* \#VMEXIT.
6208	*/
6209	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6210	{
6211	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6212	return VINF_EM_RESET;
6213	}
6214
6215
6216	/**
6217	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6218	*/
6219	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6220	{
6221	RT_NOREF(pCtx);
6222	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64\n", pSvmTransient->u64ExitCode));
6223	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6224	return VERR_SVM_UNEXPECTED_EXIT;
6225	}
6226
6227
6228	/**
6229	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6230	*/
6231	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6232	{
6233	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6234
6235	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6236	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
6237
6238	bool const fSupportsDecodeAssist = hmR0SvmSupportsDecodeAssist(pVCpu, pCtx);
6239	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6240	if ( fSupportsDecodeAssist
6241	&& fSupportsNextRipSave)
6242	{
6243	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6244	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6245	if (fMovCRx)
6246	{
6247	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6248	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6249	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6250	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6251	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6252	return VBOXSTRICTRC_VAL(rcStrict);
6253	}
6254	/* else: SMSW instruction, fall back below to IEM for this. */
6255	}
6256
6257	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6258	int rc = VBOXSTRICTRC_VAL(rc2);
6259	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
6260	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
6261	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6262	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6263	return rc;
6264	}
6265
6266
6267	/**
6268	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6269	*/
6270	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6271	{
6272	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6273
6274	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0;
6275	Assert(iCrReg <= 15);
6276
6277	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6278	bool fDecodedInstr = false;
6279	bool const fSupportsDecodeAssist = hmR0SvmSupportsDecodeAssist(pVCpu, pCtx);
6280	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6281	if ( fSupportsDecodeAssist
6282	&& fSupportsNextRipSave)
6283	{
6284	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6285	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6286	if (fMovCRx)
6287	{
6288	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6289	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6290	Log4(("hmR0SvmExitWriteCRx: Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6291	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6292	fDecodedInstr = true;
6293	}
6294	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6295	}
6296
6297	if (!fDecodedInstr)
6298	{
6299	Log4(("hmR0SvmExitWriteCRx: iCrReg=%#x\n", iCrReg));
6300	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
6301	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6302	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6303	rcStrict = VERR_EM_INTERPRETER;
6304	}
6305
6306	if (rcStrict == VINF_SUCCESS)
6307	{
6308	switch (iCrReg)
6309	{
6310	case 0: /* CR0. */
6311	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
6312	break;
6313
6314	case 3: /* CR3. */
6315	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
6316	break;
6317
6318	case 4: /* CR4. */
6319	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
6320	break;
6321
6322	case 8: /* CR8 (TPR). */
6323	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6324	break;
6325
6326	default:
6327	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6328	pSvmTransient->u64ExitCode, iCrReg));
6329	break;
6330	}
6331	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6332	}
6333	else
6334	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
6335	return VBOXSTRICTRC_TODO(rcStrict);
6336	}
6337
6338
6339	/**
6340	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6341	* \#VMEXIT.
6342	*/
6343	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6344	{
6345	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6346	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6347	PVM pVM = pVCpu->CTX_SUFF(pVM);
6348
6349	int rc;
6350	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
6351	{
6352	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6353	Log4(("MSR Write: idMsr=%#RX32\n", pCtx->ecx));
6354
6355	/* Handle TPR patching; intercepted LSTAR write. */
6356	if ( pVM->hm.s.fTPRPatchingActive
6357	&& pCtx->ecx == MSR_K8_LSTAR)
6358	{
6359	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6360	{
6361	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6362	int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6363	AssertRC(rc2);
6364	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6365	}
6366	rc = VINF_SUCCESS;
6367	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6368	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6369	return rc;
6370	}
6371
6372	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6373	if (fSupportsNextRipSave)
6374	{
6375	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6376	if (RT_LIKELY(rc == VINF_SUCCESS))
6377	{
6378	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6379	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6380	}
6381	else
6382	AssertMsg( rc == VERR_EM_INTERPRETER
6383	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
6384	}
6385	else
6386	{
6387	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
6388	if (RT_LIKELY(rc == VINF_SUCCESS))
6389	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
6390	else
6391	AssertMsg( rc == VERR_EM_INTERPRETER
6392	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6393	}
6394
6395	if (rc == VINF_SUCCESS)
6396	{
6397	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
6398	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
6399	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
6400	{
6401	/*
6402	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
6403	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
6404	* EMInterpretWrmsr() changes it.
6405	*/
6406	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6407	}
6408	else if (pCtx->ecx == MSR_K6_EFER)
6409	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
6410	else if (pCtx->ecx == MSR_IA32_TSC)
6411	pSvmTransient->fUpdateTscOffsetting = true;
6412	}
6413	}
6414	else
6415	{
6416	/* MSR Read access. */
6417	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6418	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
6419	Log4(("MSR Read: idMsr=%#RX32\n", pCtx->ecx));
6420
6421	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6422	if (fSupportsNextRipSave)
6423	{
6424	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6425	if (RT_LIKELY(rc == VINF_SUCCESS))
6426	{
6427	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6428	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6429	}
6430	else
6431	AssertMsg( rc == VERR_EM_INTERPRETER
6432	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
6433	}
6434	else
6435	{
6436	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
6437	if (RT_UNLIKELY(rc != VINF_SUCCESS))
6438	{
6439	AssertMsg( rc == VERR_EM_INTERPRETER
6440	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6441	}
6442	/* RIP updated by EMInterpretInstruction(). */
6443	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6444	}
6445	}
6446
6447	/* RIP has been updated by EMInterpret[Rd\|Wr]msr() or EMInterpretInstruction(). */
6448	return rc;
6449	}
6450
6451
6452	/**
6453	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6454	*/
6455	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6456	{
6457	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6458	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6459
6460	/** @todo Stepping with nested-guest. */
6461	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6462	{
6463	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6464	if (pSvmTransient->fWasGuestDebugStateActive)
6465	{
6466	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6467	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6468	return VERR_SVM_UNEXPECTED_EXIT;
6469	}
6470
6471	/*
6472	* Lazy DR0-3 loading.
6473	*/
6474	if (!pSvmTransient->fWasHyperDebugStateActive)
6475	{
6476	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6477	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6478
6479	/* Don't intercept DRx read and writes. */
6480	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6481	pVmcb->ctrl.u16InterceptRdDRx = 0;
6482	pVmcb->ctrl.u16InterceptWrDRx = 0;
6483	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6484
6485	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6486	VMMRZCallRing3Disable(pVCpu);
6487	HM_DISABLE_PREEMPT();
6488
6489	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6490	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6491	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6492
6493	HM_RESTORE_PREEMPT();
6494	VMMRZCallRing3Enable(pVCpu);
6495
6496	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6497	return VINF_SUCCESS;
6498	}
6499	}
6500
6501	/*
6502	* Interpret the read/writing of DRx.
6503	*/
6504	/** @todo Decode assist. */
6505	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6506	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6507	if (RT_LIKELY(rc == VINF_SUCCESS))
6508	{
6509	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6510	/** @todo CPUM should set this flag! */
6511	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
6512	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6513	}
6514	else
6515	Assert(rc == VERR_EM_INTERPRETER);
6516	return VBOXSTRICTRC_TODO(rc);
6517	}
6518
6519
6520	/**
6521	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6522	*/
6523	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6524	{
6525	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6526	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6527	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
6528	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6529	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6530	return rc;
6531	}
6532
6533
6534	/**
6535	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6536	*/
6537	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6538	{
6539	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6540
6541	/** @todo decode assists... */
6542	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6543	if (rcStrict == VINF_IEM_RAISED_XCPT)
6544	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6545
6546	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6547	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
6548	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
6549
6550	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6551	return VBOXSTRICTRC_TODO(rcStrict);
6552	}
6553
6554
6555	/**
6556	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6557	*/
6558	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6559	{
6560	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6561
6562	/* I/O operation lookup arrays. */
6563	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6564	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6565	the result (in AL/AX/EAX). */
6566	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6567
6568	PVM pVM = pVCpu->CTX_SUFF(pVM);
6569	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6570
6571	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6572	SVMIOIOEXITINFO IoExitInfo;
6573	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6574	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6575	uint32_t cbValue = s_aIOSize[uIOWidth];
6576	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6577
6578	if (RT_UNLIKELY(!cbValue))
6579	{
6580	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6581	return VERR_EM_INTERPRETER;
6582	}
6583
6584	VBOXSTRICTRC rcStrict;
6585	bool fUpdateRipAlready = false;
6586	if (IoExitInfo.n.u1STR)
6587	{
6588	#ifdef VBOX_WITH_2ND_IEM_STEP
6589	/* INS/OUTS - I/O String instruction. */
6590	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6591	* in EXITINFO1? Investigate once this thing is up and running. */
6592	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6593	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6594	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6595	static IEMMODE const s_aenmAddrMode[8] =
6596	{
6597	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6598	};
6599	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6600	if (enmAddrMode != (IEMMODE)-1)
6601	{
6602	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6603	if (cbInstr <= 15 && cbInstr >= 1)
6604	{
6605	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
6606	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6607	{
6608	/* Don't know exactly how to detect whether u3SEG is valid, currently
6609	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6610	2384 Opterons when only checking NRIP. */
6611	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6612	if ( fSupportsNextRipSave
6613	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6614	{
6615	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
6616	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
6617	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6618	IoExitInfo.n.u3SEG, true /fIoChecked/);
6619	}
6620	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
6621	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6622	X86_SREG_DS, true /fIoChecked/);
6623	else
6624	rcStrict = IEMExecOne(pVCpu);
6625	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6626	}
6627	else
6628	{
6629	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
6630	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6631	true /fIoChecked/);
6632	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6633	}
6634	}
6635	else
6636	{
6637	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6638	rcStrict = IEMExecOne(pVCpu);
6639	}
6640	}
6641	else
6642	{
6643	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6644	rcStrict = IEMExecOne(pVCpu);
6645	}
6646	fUpdateRipAlready = true;
6647
6648	#else
6649	/* INS/OUTS - I/O String instruction. */
6650	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6651
6652	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6653	* in EXITINFO1? Investigate once this thing is up and running. */
6654
6655	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
6656	if (rcStrict == VINF_SUCCESS)
6657	{
6658	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6659	{
6660	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6661	(DISCPUMODE)pDis->uAddrMode, cbValue);
6662	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6663	}
6664	else
6665	{
6666	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6667	(DISCPUMODE)pDis->uAddrMode, cbValue);
6668	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6669	}
6670	}
6671	else
6672	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
6673	#endif
6674	}
6675	else
6676	{
6677	/* IN/OUT - I/O instruction. */
6678	Assert(!IoExitInfo.n.u1REP);
6679
6680	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6681	{
6682	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6683	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6684	}
6685	else
6686	{
6687	uint32_t u32Val = 0;
6688	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6689	if (IOM_SUCCESS(rcStrict))
6690	{
6691	/* Save result of I/O IN instr. in AL/AX/EAX. */
6692	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6693	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6694	}
6695	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6696	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
6697
6698	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6699	}
6700	}
6701
6702	if (IOM_SUCCESS(rcStrict))
6703	{
6704	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6705	if (!fUpdateRipAlready)
6706	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6707
6708	/*
6709	* If any I/O breakpoints are armed, we need to check if one triggered
6710	* and take appropriate action.
6711	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6712	*/
6713	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6714	* execution engines about whether hyper BPs and such are pending. */
6715	uint32_t const uDr7 = pCtx->dr[7];
6716	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6717	&& X86_DR7_ANY_RW_IO(uDr7)
6718	&& (pCtx->cr4 & X86_CR4_DE))
6719	\|\| DBGFBpIsHwIoArmed(pVM)))
6720	{
6721	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6722	VMMRZCallRing3Disable(pVCpu);
6723	HM_DISABLE_PREEMPT();
6724
6725	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6726	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6727
6728	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
6729	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6730	{
6731	/* Raise #DB. */
6732	pVmcb->guest.u64DR6 = pCtx->dr[6];
6733	pVmcb->guest.u64DR7 = pCtx->dr[7];
6734	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6735	hmR0SvmSetPendingXcptDB(pVCpu);
6736	}
6737	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6738	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6739	else if ( rcStrict2 != VINF_SUCCESS
6740	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6741	rcStrict = rcStrict2;
6742	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6743
6744	HM_RESTORE_PREEMPT();
6745	VMMRZCallRing3Enable(pVCpu);
6746	}
6747
6748	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6749	}
6750
6751	#ifdef VBOX_STRICT
6752	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6753	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6754	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
6755	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6756	else
6757	{
6758	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6759	* statuses, that the VMM device and some others may return. See
6760	* IOM_SUCCESS() for guidance. */
6761	AssertMsg( RT_FAILURE(rcStrict)
6762	\|\| rcStrict == VINF_SUCCESS
6763	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6764	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6765	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6766	\|\| rcStrict == VINF_EM_RAW_TO_R3
6767	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6768	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6769	}
6770	#endif
6771	return VBOXSTRICTRC_TODO(rcStrict);
6772	}
6773
6774
6775	/**
6776	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6777	*/
6778	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6779	{
6780	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6781	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
6782
6783	PVM pVM = pVCpu->CTX_SUFF(pVM);
6784	Assert(pVM->hm.s.fNestedPaging);
6785
6786	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6787
6788	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
6789	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6790	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
6791	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
6792
6793	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
6794
6795	#ifdef VBOX_HM_WITH_GUEST_PATCHING
6796	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
6797	if ( pVM->hm.s.fTprPatchingAllowed
6798	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
6799	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
6800	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
6801	&& !CPUMIsGuestInLongModeEx(pCtx)
6802	&& !CPUMGetGuestCPL(pVCpu)
6803	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6804	{
6805	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6806	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6807
6808	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
6809	{
6810	/* Only attempt to patch the instruction once. */
6811	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6812	if (!pPatch)
6813	return VINF_EM_HM_PATCH_TPR_INSTR;
6814	}
6815	}
6816	#endif
6817
6818	/*
6819	* Determine the nested paging mode.
6820	*/
6821	PGMMODE enmNestedPagingMode;
6822	#if HC_ARCH_BITS == 32
6823	if (CPUMIsGuestInLongModeEx(pCtx))
6824	enmNestedPagingMode = PGMMODE_AMD64_NX;
6825	else
6826	#endif
6827	enmNestedPagingMode = PGMGetHostMode(pVM);
6828
6829	/*
6830	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
6831	*/
6832	int rc;
6833	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
6834	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
6835	{
6836	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
6837	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
6838	if (pVCpu->hm.s.Event.fPending)
6839	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6840
6841	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
6842	u32ErrCode);
6843	rc = VBOXSTRICTRC_VAL(rc2);
6844
6845	/*
6846	* If we succeed, resume guest execution.
6847	* If we fail in interpreting the instruction because we couldn't get the guest physical address
6848	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
6849	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
6850	* weird case. See @bugref{6043}.
6851	*/
6852	if ( rc == VINF_SUCCESS
6853	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6854	\|\| rc == VERR_PAGE_NOT_PRESENT)
6855	{
6856	/* Successfully handled MMIO operation. */
6857	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6858	rc = VINF_SUCCESS;
6859	}
6860	return rc;
6861	}
6862
6863	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
6864	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
6865	TRPMResetTrap(pVCpu);
6866
6867	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
6868
6869	/*
6870	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
6871	*/
6872	if ( rc == VINF_SUCCESS
6873	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6874	\|\| rc == VERR_PAGE_NOT_PRESENT)
6875	{
6876	/* We've successfully synced our shadow page tables. */
6877	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6878	rc = VINF_SUCCESS;
6879	}
6880
6881	return rc;
6882	}
6883
6884
6885	/**
6886	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
6887	* \#VMEXIT.
6888	*/
6889	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6890	{
6891	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6892	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
6893
6894	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6895	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0; /* No virtual interrupts pending, we'll inject the current one/NMI before reentry. */
6896	pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0;
6897
6898	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive interrupts/NMIs, it is now ready. */
6899	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
6900	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
6901
6902	/* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6903	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
6904	return VINF_SUCCESS;
6905	}
6906
6907
6908	/**
6909	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
6910	* \#VMEXIT.
6911	*/
6912	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6913	{
6914	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6915
6916	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6917
6918	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
6919	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
6920	#endif
6921
6922	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
6923	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
6924	{
6925	/*
6926	* AMD-V provides us with the exception which caused the TS; we collect
6927	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
6928	*/
6929	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
6930	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6931	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6932	}
6933
6934	/** @todo Emulate task switch someday, currently just going back to ring-3 for
6935	* emulation. */
6936	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6937	return VERR_EM_INTERPRETER;
6938	}
6939
6940
6941	/**
6942	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
6943	*/
6944	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6945	{
6946	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6947	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
6948
6949	bool fRipUpdated;
6950	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fRipUpdated);
6951	if (RT_SUCCESS(rcStrict))
6952	{
6953	/* Only update the RIP if we're continuing guest execution and not
6954	in the case of say VINF_GIM_R3_HYPERCALL. */
6955	if ( rcStrict == VINF_SUCCESS
6956	&& !fRipUpdated)
6957	{
6958	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
6959	}
6960
6961	/* If the hypercall or TPR patching changes anything other than guest's general-purpose registers,
6962	we would need to reload the guest changed bits here before VM-entry. */
6963	return VBOXSTRICTRC_VAL(rcStrict);
6964	}
6965
6966	hmR0SvmSetPendingXcptUD(pVCpu);
6967	return VINF_SUCCESS;
6968	}
6969
6970
6971	/**
6972	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
6973	*/
6974	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6975	{
6976	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6977	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
6978	return VINF_EM_RAW_INTERRUPT;
6979	}
6980
6981
6982	/**
6983	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
6984	*/
6985	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6986	{
6987	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6988
6989	/* Clear NMI blocking. */
6990	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6991
6992	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
6993	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6994	hmR0SvmClearIretIntercept(pVmcb);
6995
6996	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6997	return VINF_SUCCESS;
6998	}
6999
7000
7001	/**
7002	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_14).
7003	* Conditional \#VMEXIT.
7004	*/
7005	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7006	{
7007	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7008	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7009
7010	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7011
7012	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7013	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7014	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7015	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7016	PVM pVM = pVCpu->CTX_SUFF(pVM);
7017
7018	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7019	if (pVM->hm.s.fNestedPaging)
7020	{
7021	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7022	if (!pSvmTransient->fVectoringDoublePF)
7023	{
7024	/* A genuine guest #PF, reflect it to the guest. */
7025	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7026	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7027	uFaultAddress, u32ErrCode));
7028	}
7029	else
7030	{
7031	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7032	hmR0SvmSetPendingXcptDF(pVCpu);
7033	Log4(("Pending #DF due to vectoring #PF. NP\n"));
7034	}
7035	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7036	return VINF_SUCCESS;
7037	}
7038	#endif
7039
7040	Assert(!pVM->hm.s.fNestedPaging);
7041
7042	#ifdef VBOX_HM_WITH_GUEST_PATCHING
7043	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
7044	if ( pVM->hm.s.fTprPatchingAllowed
7045	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7046	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
7047	&& !CPUMIsGuestInLongModeEx(pCtx)
7048	&& !CPUMGetGuestCPL(pVCpu)
7049	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7050	{
7051	RTGCPHYS GCPhysApicBase;
7052	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7053	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7054
7055	/* Check if the page at the fault-address is the APIC base. */
7056	RTGCPHYS GCPhysPage;
7057	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7058	if ( rc2 == VINF_SUCCESS
7059	&& GCPhysPage == GCPhysApicBase)
7060	{
7061	/* Only attempt to patch the instruction once. */
7062	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7063	if (!pPatch)
7064	return VINF_EM_HM_PATCH_TPR_INSTR;
7065	}
7066	}
7067	#endif
7068
7069	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7070	pCtx->rip, u32ErrCode, pCtx->cr3));
7071
7072	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7073	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7074	if (pSvmTransient->fVectoringPF)
7075	{
7076	Assert(pVCpu->hm.s.Event.fPending);
7077	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7078	}
7079
7080	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7081	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7082
7083	Log4(("#PF rc=%Rrc\n", rc));
7084
7085	if (rc == VINF_SUCCESS)
7086	{
7087	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7088	TRPMResetTrap(pVCpu);
7089	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7090	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7091	return rc;
7092	}
7093	else if (rc == VINF_EM_RAW_GUEST_TRAP)
7094	{
7095	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7096
7097	if (!pSvmTransient->fVectoringDoublePF)
7098	{
7099	/* It's a guest page fault and needs to be reflected to the guest. */
7100	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7101	TRPMResetTrap(pVCpu);
7102	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7103	}
7104	else
7105	{
7106	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7107	TRPMResetTrap(pVCpu);
7108	hmR0SvmSetPendingXcptDF(pVCpu);
7109	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7110	}
7111
7112	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7113	return VINF_SUCCESS;
7114	}
7115
7116	TRPMResetTrap(pVCpu);
7117	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7118	return rc;
7119	}
7120
7121
7122	/**
7123	* \#VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
7124	* Conditional \#VMEXIT.
7125	*/
7126	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7127	{
7128	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7129
7130	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7131	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7132	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7133
7134	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
7135	VMMRZCallRing3Disable(pVCpu);
7136	HM_DISABLE_PREEMPT();
7137
7138	int rc;
7139	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
7140	if (pSvmTransient->fWasGuestFPUStateActive)
7141	{
7142	rc = VINF_EM_RAW_GUEST_TRAP;
7143	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
7144	}
7145	else
7146	{
7147	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
7148	Assert(!pSvmTransient->fWasGuestFPUStateActive);
7149	#endif
7150	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu); /* (No need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
7151	Assert( rc == VINF_EM_RAW_GUEST_TRAP
7152	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
7153	}
7154
7155	HM_RESTORE_PREEMPT();
7156	VMMRZCallRing3Enable(pVCpu);
7157
7158	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
7159	{
7160	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
7161	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
7162	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
7163	pVCpu->hm.s.fPreloadGuestFpu = true;
7164	}
7165	else
7166	{
7167	/* Forward #NM to the guest. */
7168	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
7169	hmR0SvmSetPendingXcptNM(pVCpu);
7170	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
7171	}
7172	return VINF_SUCCESS;
7173	}
7174
7175
7176	/**
7177	* \#VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
7178	* Conditional \#VMEXIT.
7179	*/
7180	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7181	{
7182	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7183
7184	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7185	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7186	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7187
7188	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7189	if (pVCpu->hm.s.fGIMTrapXcptUD)
7190	{
7191	uint8_t cbInstr = 0;
7192	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
7193	if (rcStrict == VINF_SUCCESS)
7194	{
7195	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7196	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
7197	rc = VINF_SUCCESS;
7198	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7199	}
7200	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7201	rc = VINF_SUCCESS;
7202	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7203	rc = VINF_GIM_R3_HYPERCALL;
7204	else
7205	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7206	}
7207
7208	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7209	if (RT_FAILURE(rc))
7210	{
7211	hmR0SvmSetPendingXcptUD(pVCpu);
7212	rc = VINF_SUCCESS;
7213	}
7214
7215	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7216	return rc;
7217	}
7218
7219
7220	/**
7221	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_16).
7222	* Conditional \#VMEXIT.
7223	*/
7224	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7225	{
7226	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7227
7228	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7229	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7230	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7231
7232	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7233
7234	if (!(pCtx->cr0 & X86_CR0_NE))
7235	{
7236	PVM pVM = pVCpu->CTX_SUFF(pVM);
7237	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7238	unsigned cbOp;
7239	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
7240	if (RT_SUCCESS(rc))
7241	{
7242	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7243	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
7244	if (RT_SUCCESS(rc))
7245	pCtx->rip += cbOp;
7246	}
7247	else
7248	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7249	return rc;
7250	}
7251
7252	hmR0SvmSetPendingXcptMF(pVCpu);
7253	return VINF_SUCCESS;
7254	}
7255
7256
7257	/**
7258	* \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
7259	* \#VMEXIT.
7260	*/
7261	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7262	{
7263	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7264
7265	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7266	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7267	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7268	{
7269	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7270	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7271	}
7272
7273	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7274
7275	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
7276	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
7277	PVM pVM = pVCpu->CTX_SUFF(pVM);
7278	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7279	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7280	if (rc == VINF_EM_RAW_GUEST_TRAP)
7281	{
7282	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7283	if (CPUMIsHyperDebugStateActive(pVCpu))
7284	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7285
7286	/* Reflect the exception back to the guest. */
7287	hmR0SvmSetPendingXcptDB(pVCpu);
7288	rc = VINF_SUCCESS;
7289	}
7290
7291	/*
7292	* Update DR6.
7293	*/
7294	if (CPUMIsHyperDebugStateActive(pVCpu))
7295	{
7296	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7297	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7298	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7299	}
7300	else
7301	{
7302	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7303	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7304	}
7305
7306	return rc;
7307	}
7308
7309
7310	/**
7311	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_17).
7312	* Conditional \#VMEXIT.
7313	*/
7314	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7315	{
7316	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7317
7318	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7319	* shutdown VMEXIT. */
7320	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7321
7322	SVMEVENT Event;
7323	Event.u = 0;
7324	Event.n.u1Valid = 1;
7325	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7326	Event.n.u8Vector = X86_XCPT_AC;
7327	Event.n.u1ErrorCodeValid = 1;
7328	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7329	return VINF_SUCCESS;
7330	}
7331
7332
7333	/**
7334	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7335	* Conditional \#VMEXIT.
7336	*/
7337	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7338	{
7339	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7340
7341	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7342
7343	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7344	if (rc == VINF_EM_RAW_GUEST_TRAP)
7345	{
7346	SVMEVENT Event;
7347	Event.u = 0;
7348	Event.n.u1Valid = 1;
7349	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7350	Event.n.u8Vector = X86_XCPT_BP;
7351	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7352	}
7353
7354	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7355	return rc;
7356	}
7357
7358
7359	#ifdef VBOX_WITH_NESTED_HWVIRT
7360	/**
7361	* \#VMEXIT handler for #PF occuring while in nested-guest execution
7362	* (SVM_EXIT_EXCEPTION_14). Conditional \#VMEXIT.
7363	*/
7364	HMSVM_EXIT_DECL hmR0SvmExitXcptPFNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7365	{
7366	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7367
7368	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7369
7370	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7371	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7372	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7373	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7374
7375	Log4(("#PFNested: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode=%#RX32 CR3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7376	pCtx->rip, u32ErrCode, pCtx->cr3));
7377
7378	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7379	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7380	if (pSvmTransient->fVectoringPF)
7381	{
7382	Assert(pVCpu->hm.s.Event.fPending);
7383	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7384	}
7385
7386	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7387
7388	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7389	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7390
7391	Log4(("#PFNested: rc=%Rrc\n", rc));
7392
7393	if (rc == VINF_SUCCESS)
7394	{
7395	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7396	TRPMResetTrap(pVCpu);
7397	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7398	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7399	return rc;
7400	}
7401
7402	if (rc == VINF_EM_RAW_GUEST_TRAP)
7403	{
7404	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7405
7406	if (!pSvmTransient->fVectoringDoublePF)
7407	{
7408	/* It's a nested-guest page fault and needs to be reflected to the nested-guest. */
7409	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7410	TRPMResetTrap(pVCpu);
7411	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7412	}
7413	else
7414	{
7415	/* A nested-guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7416	TRPMResetTrap(pVCpu);
7417	hmR0SvmSetPendingXcptDF(pVCpu);
7418	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7419	}
7420
7421	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7422	return VINF_SUCCESS;
7423	}
7424
7425	TRPMResetTrap(pVCpu);
7426	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7427	return rc;
7428	}
7429
7430
7431	/**
7432	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7433	*/
7434	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7435	{
7436	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7437
7438	/** @todo Stat. */
7439	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClgi); */
7440	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7441	VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7442	return VBOXSTRICTRC_VAL(rcStrict);
7443	}
7444
7445
7446	/**
7447	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7448	*/
7449	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7450	{
7451	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7452
7453	/** @todo Stat. */
7454	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitStgi); */
7455	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7456	VBOXSTRICTRC rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7457	return VBOXSTRICTRC_VAL(rcStrict);
7458	}
7459
7460
7461	/**
7462	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7463	*/
7464	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7465	{
7466	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7467
7468	/** @todo Stat. */
7469	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmload); */
7470	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7471	VBOXSTRICTRC rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7472	if (rcStrict == VINF_SUCCESS)
7473	{
7474	/* We skip flagging changes made to LSTAR, STAR, SFMASK and other MSRs as they are always re-loaded. */
7475	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS
7476	\| HM_CHANGED_GUEST_TR
7477	\| HM_CHANGED_GUEST_LDTR);
7478	}
7479	return VBOXSTRICTRC_VAL(rcStrict);
7480	}
7481
7482
7483	/**
7484	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7485	*/
7486	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7487	{
7488	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7489
7490	/** @todo Stat. */
7491	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmsave); */
7492	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7493	VBOXSTRICTRC rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7494	return VBOXSTRICTRC_VAL(rcStrict);
7495	}
7496
7497
7498	/**
7499	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7500	*/
7501	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7502	{
7503	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7504	/** @todo Stat. */
7505	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpga); */
7506	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7507	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7508	return VBOXSTRICTRC_VAL(rcStrict);
7509	}
7510
7511
7512	/**
7513	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7514	*/
7515	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7516	{
7517	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7518	/** @todo Stat. */
7519	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmrun); */
7520	#if 0
7521	VBOXSTRICTRC rcStrict;
7522	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7523	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7524	Log4(("IEMExecDecodedVmrun: returned %d\n", VBOXSTRICTRC_VAL(rcStrict)));
7525	if (rcStrict == VINF_SUCCESS)
7526	{
7527	rcStrict = VINF_SVM_VMRUN;
7528	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7529	}
7530	return VBOXSTRICTRC_VAL(rcStrict);
7531	#endif
7532	return VERR_EM_INTERPRETER;
7533	}
7534
7535
7536	/**
7537	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1).
7538	* Unconditional \#VMEXIT.
7539	*/
7540	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7541	{
7542	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7543
7544	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7545	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7546	* shutdown VMEXIT. */
7547	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7548	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7549	{
7550	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7551	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7552	}
7553
7554	hmR0SvmSetPendingXcptDB(pVCpu);
7555	return VINF_SUCCESS;
7556	}
7557
7558
7559	/**
7560	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7561	* Conditional \#VMEXIT.
7562	*/
7563	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7564	{
7565	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7566
7567	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7568	* shutdown VMEXIT. */
7569	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7570
7571	SVMEVENT Event;
7572	Event.u = 0;
7573	Event.n.u1Valid = 1;
7574	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7575	Event.n.u8Vector = X86_XCPT_BP;
7576	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7577	return VINF_SUCCESS;
7578	}
7579
7580	#endif /* VBOX_WITH_NESTED_HWVIRT */
7581
7582
7583	/** @} */
7584

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 70000

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