Changeset 70000 in vbox for trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
- Timestamp:
- Dec 8, 2017 5:57:18 AM (7 years ago)
- svn:sync-xref-src-repo-rev:
- 119524
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r69975 r70000 21 21 *********************************************************************************************************************************/ 22 22 #define LOG_GROUP LOG_GROUP_HM 23 #define VMCPU_INCL_CPUM_GST_CTX 23 24 #include <iprt/asm-amd64-x86.h> 24 25 #include <iprt/thread.h> … … 2198 2199 static void hmR0SvmVmRunSetupVmcb(PVMCPU pVCpu, PCPUMCTX pCtx) 2199 2200 { 2200 RT_NOREF(pVCpu);2201 2201 PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb); 2202 2202 PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl; … … 2253 2253 Assert(pVmcbNstGst); 2254 2254 2255 hmR0SvmVmRunSetupVmcb(pVCpu, pCtx); 2255 2256 hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx); 2256 2257 hmR0SvmLoadGuestMsrs(pVCpu, pVmcbNstGst, pCtx); … … 2709 2710 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST); 2710 2711 2711 #ifdef VBOX_WITH_NESTED_HWVIRT2712 /*2713 * We may inspect the nested-guest VMCB state in ring-3 (e.g. for injecting interrupts)2714 * and thus we need to restore any modifications we may have made to it here if we're2715 * still executing the nested-guest.2716 */2717 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))2718 HMSvmNstGstVmExitNotify(pVCpu, pCtx);2719 #endif2720 2721 2712 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3); 2722 2713 … … 3170 3161 3171 3162 #ifdef VBOX_WITH_NESTED_HWVIRT 3172 /**3173 * Checks whether the SVM nested-guest is in a state to receive physical (APIC)3174 * interrupts.3175 *3176 * @returns true if it's ready, false otherwise.3177 * @param pCtx The guest-CPU context.3178 *3179 * @remarks This function looks at the VMCB cache rather than directly at the3180 * nested-guest VMCB which may have been suitably modified for executing3181 * using hardware-assisted SVM.3182 *3183 * @sa CPUMCanSvmNstGstTakePhysIntr.3184 */3185 static bool hmR0SvmCanNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)3186 {3187 Assert(pCtx->hwvirt.svm.fHMCachedVmcb);3188 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;3189 X86EFLAGS fEFlags;3190 if (pVmcbNstGstCache->fVIntrMasking)3191 fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;3192 else3193 fEFlags.u = pCtx->eflags.u;3194 3195 return fEFlags.Bits.u1IF;3196 }3197 3163 3198 3164 … … 3265 3231 */ 3266 3232 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache; 3267 Assert(pCtx->hwvirt.svm.fHMCachedVmcb);3268 3233 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC) 3269 3234 && !fIntShadow 3270 3235 && !pVCpu->hm.s.fSingleInstruction 3271 && hmR0SvmCanNstGstTakePhysIntr(pVCpu, pCtx))3236 && CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx)) 3272 3237 { 3273 3238 if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INTR) … … 3753 3718 return rc; 3754 3719 3755 hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);3756 3757 3720 if (TRPMHasTrap(pVCpu)) 3758 3721 hmR0SvmTrpmTrapToPendingEvent(pVCpu); … … 3781 3744 rc = hmR0SvmLoadGuestStateNested(pVCpu, pCtx); 3782 3745 AssertRCReturn(rc, rc); 3783 /** @todo Get new STAM counter for this? */3784 STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull); 3785 3746 STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull); /** @todo Get new STAM counter for this? */ 3747 3748 /* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware SVM. */ 3786 3749 Assert(pCtx->hwvirt.svm.fHMCachedVmcb); 3787 3750 … … 4311 4274 hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcbNstGst); /* Save the nested-guest state from the VMCB to the 4312 4275 guest-CPU context. */ 4313 4314 HMSvmNstGstVmExitNotify(pVCpu, pMixedCtx); /* Restore modified VMCB fields for now, see @bugref{7243#c52} .*/4315 4276 } 4316 4277 #endif … … 4752 4713 #define HM_SVM_VMEXIT_NESTED(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \ 4753 4714 VBOXSTRICTRC_TODO(IEMExecSvmVmexit(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2)) 4754 #define HM_SVM_IS_CTRL_INTERCEPT_SET(a_pCtx, a_Intercept) CPUMIsGuestSvmCtrlInterceptSet(a_pCtx, (a_Intercept))4755 #define HM_SVM_IS_XCPT_INTERCEPT_SET(a_pCtx, a_Xcpt) CPUMIsGuestSvmXcptInterceptSet(a_pCtx, (a_Xcpt))4756 #define HM_SVM_IS_READ_CR_INTERCEPT_SET(a_pCtx, a_uCr) CPUMIsGuestSvmReadCRxInterceptSet(a_pCtx, (a_uCr))4757 #define HM_SVM_IS_READ_DR_INTERCEPT_SET(a_pCtx, a_uDr) CPUMIsGuestSvmReadDRxInterceptSet(a_pCtx, (a_uDr))4758 #define HM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pCtx, a_uCr) CPUMIsGuestSvmWriteCRxInterceptSet(a_pCtx, (a_uCr))4759 #define HM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pCtx, a_uDr) CPUMIsGuestSvmWriteDRxInterceptSet(a_pCtx, (a_uDr))4760 4715 4761 4716 /* … … 4774 4729 case SVM_EXIT_CPUID: 4775 4730 { 4776 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_CPUID))4731 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID)) 4777 4732 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4778 4733 return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient); … … 4781 4736 case SVM_EXIT_RDTSC: 4782 4737 { 4783 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_RDTSC))4738 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC)) 4784 4739 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4785 4740 return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient); … … 4788 4743 case SVM_EXIT_RDTSCP: 4789 4744 { 4790 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_RDTSCP))4745 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP)) 4791 4746 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4792 4747 return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient); … … 4796 4751 case SVM_EXIT_MONITOR: 4797 4752 { 4798 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_MONITOR))4753 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR)) 4799 4754 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4800 4755 return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient); … … 4803 4758 case SVM_EXIT_MWAIT: 4804 4759 { 4805 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_MWAIT))4760 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT)) 4806 4761 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4807 4762 return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient); … … 4810 4765 case SVM_EXIT_HLT: 4811 4766 { 4812 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_HLT))4767 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT)) 4813 4768 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4814 4769 return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient); … … 4817 4772 case SVM_EXIT_MSR: 4818 4773 { 4819 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))4774 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT)) 4820 4775 { 4821 4776 uint32_t const idMsr = pCtx->ecx; … … 4853 4808 * Figure out if the IO port access is intercepted by the nested-guest. 4854 4809 */ 4855 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))4810 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT)) 4856 4811 { 4857 4812 void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap); … … 4874 4829 4875 4830 /* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */ 4876 if (HM _SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_PF))4831 if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF)) 4877 4832 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, u32ErrCode, uFaultAddress); 4878 4833 … … 4886 4841 case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */ 4887 4842 { 4888 if (HM _SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_NM))4843 if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_NM)) 4889 4844 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4890 4845 hmR0SvmSetPendingXcptNM(pVCpu); … … 4894 4849 case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */ 4895 4850 { 4896 if (HM _SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_UD))4851 if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD)) 4897 4852 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4898 4853 hmR0SvmSetPendingXcptUD(pVCpu); … … 4902 4857 case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */ 4903 4858 { 4904 if (HM _SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_MF))4859 if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF)) 4905 4860 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4906 4861 hmR0SvmSetPendingXcptMF(pVCpu); … … 4910 4865 case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */ 4911 4866 { 4912 if (HM _SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_DB))4867 if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB)) 4913 4868 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4914 4869 return hmR0SvmNestedExitXcptDB(pVCpu, pCtx, pSvmTransient); … … 4917 4872 case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */ 4918 4873 { 4919 if (HM _SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_AC))4874 if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC)) 4920 4875 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4921 4876 return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient); … … 4924 4879 case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */ 4925 4880 { 4926 if (HM _SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_BP))4881 if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP)) 4927 4882 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4928 4883 return hmR0SvmNestedExitXcptBP(pVCpu, pCtx, pSvmTransient); … … 4933 4888 case SVM_EXIT_READ_CR4: 4934 4889 { 4935 if (HM_SVM_IS_READ_CR_INTERCEPT_SET(pCtx, (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0)))) 4890 uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0; 4891 if (HMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr)) 4936 4892 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4937 4893 return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient); … … 4943 4899 case SVM_EXIT_WRITE_CR8: /** @todo Shouldn't writes to CR8 go to V_TPR instead since we run with V_INTR_MASKING set?? */ 4944 4900 { 4901 uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0; 4945 4902 Log4(("hmR0SvmHandleExitNested: Write CRx: u16InterceptWrCRx=%#x u64ExitCode=%#RX64 %#x\n", 4946 pVmcbNstGstCtrl->u16InterceptWrCRx, pSvmTransient->u64ExitCode, 4947 (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)))); 4948 4949 if (HM_SVM_IS_WRITE_CR_INTERCEPT_SET(pCtx, (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)))) 4903 pVmcbNstGstCtrl->u16InterceptWrCRx, pSvmTransient->u64ExitCode, uCr)); 4904 4905 if (HMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr)) 4950 4906 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4951 4907 return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient); … … 4954 4910 case SVM_EXIT_PAUSE: 4955 4911 { 4956 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_PAUSE))4912 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE)) 4957 4913 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4958 4914 return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient); … … 4961 4917 case SVM_EXIT_VINTR: 4962 4918 { 4963 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_VINTR))4919 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR)) 4964 4920 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4965 4921 return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient); … … 4974 4930 case SVM_EXIT_FERR_FREEZE: 4975 4931 { 4976 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))4932 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE)) 4977 4933 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4978 4934 return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient); … … 4981 4937 case SVM_EXIT_NMI: 4982 4938 { 4983 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_NMI))4939 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI)) 4984 4940 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4985 4941 return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient); … … 4988 4944 case SVM_EXIT_INVLPG: 4989 4945 { 4990 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_INVLPG))4946 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG)) 4991 4947 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4992 4948 return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient); … … 4995 4951 case SVM_EXIT_WBINVD: 4996 4952 { 4997 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_WBINVD))4953 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD)) 4998 4954 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 4999 4955 return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient); … … 5002 4958 case SVM_EXIT_INVD: 5003 4959 { 5004 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_INVD))4960 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD)) 5005 4961 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5006 4962 return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient); … … 5009 4965 case SVM_EXIT_RDPMC: 5010 4966 { 5011 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_RDPMC))4967 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC)) 5012 4968 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5013 4969 return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient); … … 5023 4979 case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15: 5024 4980 { 5025 if (HM_SVM_IS_READ_DR_INTERCEPT_SET(pCtx, (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_READ_DR0)))) 4981 uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0; 4982 if (HMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr)) 5026 4983 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5027 4984 return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient); … … 5033 4990 case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15: 5034 4991 { 5035 if (HM_SVM_IS_WRITE_DR_INTERCEPT_SET(pCtx, (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_DR0)))) 4992 uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0; 4993 if (HMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr)) 5036 4994 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5037 4995 return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient); … … 5051 5009 case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31: 5052 5010 { 5053 if (HM_SVM_IS_XCPT_INTERCEPT_SET(pCtx, (uint32_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0))) 5011 uint8_t const uVector = uExitCode - SVM_EXIT_EXCEPTION_0; 5012 if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector)) 5054 5013 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5055 5014 /** @todo Write hmR0SvmExitXcptGeneric! */ … … 5059 5018 case SVM_EXIT_XSETBV: 5060 5019 { 5061 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_XSETBV))5020 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV)) 5062 5021 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5063 5022 return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient); … … 5066 5025 case SVM_EXIT_TASK_SWITCH: 5067 5026 { 5068 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))5027 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH)) 5069 5028 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5070 5029 return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient); … … 5073 5032 case SVM_EXIT_IRET: 5074 5033 { 5075 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_IRET))5034 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET)) 5076 5035 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5077 5036 return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient); … … 5080 5039 case SVM_EXIT_SHUTDOWN: 5081 5040 { 5082 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))5041 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) 5083 5042 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5084 5043 return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient); … … 5087 5046 case SVM_EXIT_SMI: 5088 5047 { 5089 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_SMI))5048 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SMI)) 5090 5049 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5091 5050 return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient); … … 5094 5053 case SVM_EXIT_INIT: 5095 5054 { 5096 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_INIT))5055 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INIT)) 5097 5056 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5098 5057 return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient); … … 5101 5060 case SVM_EXIT_VMMCALL: 5102 5061 { 5103 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_VMMCALL))5062 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL)) 5104 5063 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5105 5064 return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient); … … 5108 5067 case SVM_EXIT_CLGI: 5109 5068 { 5110 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_CLGI))5069 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI)) 5111 5070 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5112 5071 return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient); … … 5115 5074 case SVM_EXIT_STGI: 5116 5075 { 5117 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_STGI))5076 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI)) 5118 5077 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5119 5078 return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient); … … 5122 5081 case SVM_EXIT_VMLOAD: 5123 5082 { 5124 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_VMLOAD))5083 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD)) 5125 5084 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5126 5085 return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient); … … 5129 5088 case SVM_EXIT_VMSAVE: 5130 5089 { 5131 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_VMSAVE))5090 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE)) 5132 5091 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5133 5092 return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient); … … 5136 5095 case SVM_EXIT_INVLPGA: 5137 5096 { 5138 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_INVLPGA))5097 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA)) 5139 5098 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5140 5099 return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient); … … 5143 5102 case SVM_EXIT_VMRUN: 5144 5103 { 5145 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_VMRUN))5104 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN)) 5146 5105 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5147 5106 return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient); … … 5150 5109 case SVM_EXIT_RSM: 5151 5110 { 5152 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_RSM))5111 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM)) 5153 5112 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5154 5113 hmR0SvmSetPendingXcptUD(pVCpu); … … 5158 5117 case SVM_EXIT_SKINIT: 5159 5118 { 5160 if (HM _SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_SKINIT))5119 if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT)) 5161 5120 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2); 5162 5121 hmR0SvmSetPendingXcptUD(pVCpu); … … 5182 5141 5183 5142 #undef HM_SVM_VMEXIT_NESTED 5184 #undef HM_SVM_IS_CTRL_INTERCEPT_SET5185 #undef HM_SVM_IS_XCPT_INTERCEPT_SET5186 #undef HM_SVM_IS_READ_CR_INTERCEPT_SET5187 #undef HM_SVM_IS_READ_DR_INTERCEPT_SET5188 #undef HM_SVM_IS_WRITE_CR_INTERCEPT_SET5189 #undef HM_SVM_IS_WRITE_DR_INTERCEPT_SET5190 5143 } 5191 5144 #endif
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