Changeset 70000 in vbox

Timestamp:

Dec 8, 2017 5:57:18 AM (7 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

119524

Message:

VMM: Nested Hw.virt: Make SVM intercept functions smarter. Avoids swapping of modified VMCB state in a lot of
tricky to detect situations and makes it a lot cleaner that the VMCB is only finally restored before the
#VMEXIT is done.

Location:

trunk

Files:

• include/VBox/vmm/cpum.h (modified) (7 diffs)
• include/VBox/vmm/hm_svm.h (modified) (1 diff)
• src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (modified) (1 diff)
• src/VBox/VMM/VMMAll/HMSVMAll.cpp (modified) (1 diff)
• src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (54 diffs)
• src/VBox/VMM/VMMR3/EM.cpp (modified) (3 diffs)

trunk/include/VBox/vmm/cpum.h

@@ -1203 +1203 @@
 /** @name Nested Hardware-Virtualization Helpers.
  * @{  */
-VMM_INT_DECL(bool)      CPUMCanSvmNstGstTakePhysIntr(PCCPUMCTX pCtx);
+VMM_INT_DECL(bool)      CPUMCanSvmNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx);
 VMM_INT_DECL(bool)      CPUMCanSvmNstGstTakeVirtIntr(PCCPUMCTX pCtx);
 VMM_INT_DECL(uint8_t)   CPUMGetSvmNstGstInterrupt(PCCPUMCTX pCtx);
@@ -1327 +1327 @@
  *
  * @returns @c true if in intercept is set, @c false otherwise.
- * @param   pCtx          Pointer to the context.
- * @param   fIntercept    The SVM control/instruction intercept,
- *                        see SVM_CTRL_INTERCEPT_*.
- */
-DECLINLINE(bool) CPUMIsGuestSvmCtrlInterceptSet(PCCPUMCTX pCtx, uint64_t fIntercept)
-{
-    Assert(!pCtx->hwvirt.svm.fHMCachedVmcb);
+ * @param   pVCpu       The cross context virtual CPU structure of the calling EMT.
+ * @param   pCtx        Pointer to the context.
+ * @param   fIntercept  The SVM control/instruction intercept, see
+ *                      SVM_CTRL_INTERCEPT_*.
+ */
+DECLINLINE(bool) CPUMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fIntercept)
+{
     PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
-    return pVmcb && (pVmcb->ctrl.u64InterceptCtrl & fIntercept);
+    if (!pVmcb)
+        return false;
+    if (!pCtx->hwvirt.svm.fHMCachedVmcb)
+        return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fIntercept);
+    return HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, fIntercept);
 }
 
 /**
- * Checks if the guest VMCB has the specified CR read intercept
- * active.
+ * Checks if the guest VMCB has the specified CR read intercept active.
  *
  * @returns @c true if in intercept is set, @c false otherwise.
- * @param   pCtx          Pointer to the context.
- * @param   uCr           The CR register number (0 to 15).
- */
-DECLINLINE(bool) CPUMIsGuestSvmReadCRxInterceptSet(PCCPUMCTX pCtx, uint8_t uCr)
-{
-    Assert(!pCtx->hwvirt.svm.fHMCachedVmcb);
+ * @param   pVCpu   The cross context virtual CPU structure of the calling EMT.
+ * @param   pCtx    Pointer to the context.
+ * @param   uCr     The CR register number (0 to 15).
+ */
+DECLINLINE(bool) CPUMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
+{
+    Assert(uCr < 16);
     PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
-    return pVmcb && (pVmcb->ctrl.u16InterceptRdCRx & (1 << uCr));
+    if (!pVmcb)
+        return false;
+    if (!pCtx->hwvirt.svm.fHMCachedVmcb)
+        return RT_BOOL(pVmcb->ctrl.u16InterceptRdCRx & (UINT16_C(1) << uCr));
+    return HMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr);
 }
 
 /**
- * Checks if the guest VMCB has the specified CR write intercept
- * active.
+ * Checks if the guest VMCB has the specified CR write intercept active.
  *
  * @returns @c true if in intercept is set, @c false otherwise.
- * @param   pCtx          Pointer to the context.
- * @param   uCr           The CR register number (0 to 15).
- */
-DECLINLINE(bool) CPUMIsGuestSvmWriteCRxInterceptSet(PCCPUMCTX pCtx, uint8_t uCr)
-{
-    Assert(!pCtx->hwvirt.svm.fHMCachedVmcb);
+ * @param   pVCpu   The cross context virtual CPU structure of the calling EMT.
+ * @param   pCtx    Pointer to the context.
+ * @param   uCr     The CR register number (0 to 15).
+ */
+DECLINLINE(bool) CPUMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
+{
+    Assert(uCr < 16);
     PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
-    return pVmcb && (pVmcb->ctrl.u16InterceptWrCRx & (1 << uCr));
+    if (!pVmcb)
+        return false;
+    if (!pCtx->hwvirt.svm.fHMCachedVmcb)
+        return RT_BOOL(pVmcb->ctrl.u16InterceptWrCRx & (UINT16_C(1) << uCr));
+    return HMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr);
 }
 
 /**
- * Checks if the guest VMCB has the specified DR read intercept
- * active.
+ * Checks if the guest VMCB has the specified DR read intercept active.
  *
  * @returns @c true if in intercept is set, @c false otherwise.
+ * @param   pVCpu   The cross context virtual CPU structure of the calling EMT.
  * @param   pCtx    Pointer to the context.
  * @param   uDr     The DR register number (0 to 15).
  */
-DECLINLINE(bool) CPUMIsGuestSvmReadDRxInterceptSet(PCCPUMCTX pCtx, uint8_t uDr)
-{
-    Assert(!pCtx->hwvirt.svm.fHMCachedVmcb);
+DECLINLINE(bool) CPUMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
+{
+    Assert(uDr < 16);
     PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
-    return pVmcb && (pVmcb->ctrl.u16InterceptRdDRx & (1 << uDr));
+    if (!pVmcb)
+        return false;
+    if (!pCtx->hwvirt.svm.fHMCachedVmcb)
+        return RT_BOOL(pVmcb->ctrl.u16InterceptRdDRx & (UINT16_C(1) << uDr));
+    return HMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr);
 }
 
 /**
- * Checks if the guest VMCB has the specified DR write intercept
- * active.
+ * Checks if the guest VMCB has the specified DR write intercept active.
  *
  * @returns @c true if in intercept is set, @c false otherwise.
+ * @param   pVCpu   The cross context virtual CPU structure of the calling EMT.
  * @param   pCtx    Pointer to the context.
  * @param   uDr     The DR register number (0 to 15).
  */
-DECLINLINE(bool) CPUMIsGuestSvmWriteDRxInterceptSet(PCCPUMCTX pCtx, uint8_t uDr)
-{
-    Assert(!pCtx->hwvirt.svm.fHMCachedVmcb);
+DECLINLINE(bool) CPUMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
+{
+    Assert(uDr < 16);
     PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
-    return pVmcb && (pVmcb->ctrl.u16InterceptWrDRx & (1 << uDr));
+    if (!pVmcb)
+        return false;
+    if (!pCtx->hwvirt.svm.fHMCachedVmcb)
+        return RT_BOOL(pVmcb->ctrl.u16InterceptWrDRx & (UINT16_C(1) << uDr));
+    return HMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr);
 }
 
 /**
- * Checks if the guest VMCB has the specified exception
- * intercept active.
- *
- * @returns true if in intercept is active, false otherwise.
+ * Checks if the guest VMCB has the specified exception intercept active.
+ *
+ * @returns @c true if in intercept is active, @c false otherwise.
+ * @param   pVCpu   The cross context virtual CPU structure of the calling EMT.
  * @param   pCtx        Pointer to the context.
  * @param   uVector     The exception / interrupt vector.
  */
-DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PCCPUMCTX pCtx, uint8_t uVector)
-{
-    Assert(!pCtx->hwvirt.svm.fHMCachedVmcb);
+DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
+{
     Assert(uVector < 32);
     PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
-    return pVmcb && (pVmcb->ctrl.u32InterceptXcpt & (UINT32_C(1) << uVector));
+    if (!pVmcb)
+        return false;
+    if (!pCtx->hwvirt.svm.fHMCachedVmcb)
+        return RT_BOOL(pVmcb->ctrl.u32InterceptXcpt & (UINT32_C(1) << uVector));
+    return HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector);
 }
 #endif /* !IN_RC */
@@ -1418 +1441 @@
  * Checks if we are executing inside an SVM nested hardware-virtualized guest.
  *
- * @returns true if in SVM nested-guest mode, false otherwise.
+ * @returns @c true if in SVM nested-guest mode, @c false otherwise.
  * @param   pCtx        Pointer to the context.
  */
@@ -1431 +1454 @@
     return pVmcb && (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN);
 #else
-    RT_NOREF(pCtx);
+    NOREF(pCtx);
     return false;
 #endif
@@ -1439 +1462 @@
  * Checks if we are executing inside a VMX nested hardware-virtualized guest.
  *
- * @returns true if in VMX nested-guest mode, false otherwise.
+ * @returns @c true if in VMX nested-guest mode, @c false otherwise.
  * @param   pCtx        Pointer to the context.
  */
@@ -1445 +1468 @@
 {
     /** @todo Intel. */
-    RT_NOREF(pCtx);
+    NOREF(pCtx);
     return false;
 }
@@ -1452 +1475 @@
  * Checks if we are executing inside a nested hardware-virtualized guest.
  *
- * @returns true if in SVM/VMX nested-guest mode, false otherwise.
+ * @returns @c true if in SVM/VMX nested-guest mode, @c false otherwise.
  * @param   pCtx        Pointer to the context.
  */

trunk/include/VBox/vmm/hm_svm.h

@@ -1085 +1085 @@
     } while (0)
 
+VMM_INT_DECL(bool) HMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fIntercept);
+VMM_INT_DECL(bool) HMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr);
+VMM_INT_DECL(bool) HMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr);
+VMM_INT_DECL(bool) HMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr);
+VMM_INT_DECL(bool) HMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr);
+VMM_INT_DECL(bool) HMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector);
+VMM_INT_DECL(bool) HMCanSvmNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx);
 
 /** @} */

trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

@@ -2551 +2551 @@
  * @retval  true if it's ready, false otherwise.
  *
- * @param   pCtx        The guest-CPU context.
+ * @param   pVCpu   The cross context virtual CPU structure of the calling EMT.
+ * @param   pCtx    The guest-CPU context.
  *
  * @sa      hmR0SvmCanNstGstTakePhysIntr.
  */
-VMM_INT_DECL(bool) CPUMCanSvmNstGstTakePhysIntr(PCCPUMCTX pCtx)
+VMM_INT_DECL(bool) CPUMCanSvmNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
 {
 #ifdef IN_RC
-    RT_NOREF(pCtx);
+    RT_NOREF2(pVCpu, pCtx);
     AssertReleaseFailedReturn(false);
 #else
     Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
     Assert(pCtx->hwvirt.svm.fGif);
-    Assert(!pCtx->hwvirt.svm.fHMCachedVmcb);
-
-    PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
-    X86EFLAGS fEFlags;
-    if (pVmcbCtrl->IntCtrl.n.u1VIntrMasking)
-        fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
-    else
-        fEFlags.u = pCtx->eflags.u;
-
-    return fEFlags.Bits.u1IF;
+
+    if (!pCtx->hwvirt.svm.fHMCachedVmcb)
+    {
+        PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
+        X86EFLAGS fEFlags;
+        if (pVmcbCtrl->IntCtrl.n.u1VIntrMasking)
+            fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
+        else
+            fEFlags.u = pCtx->eflags.u;
+
+        return fEFlags.Bits.u1IF;
+    }
+
+    return HMCanSvmNstGstTakePhysIntr(pVCpu, pCtx);
 #endif
 }

trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp

@@ -374 +374 @@
 #endif
 
+
+/**
+ * Checks if the guest VMCB has the specified ctrl/instruction intercept active.
+ *
+ * @returns @c true if in intercept is set, @c false otherwise.
+ * @param   pVCpu       The cross context virtual CPU structure of the calling EMT.
+ * @param   pCtx        Pointer to the context.
+ * @param   fIntercept  The SVM control/instruction intercept, see
+ *                      SVM_CTRL_INTERCEPT_*.
+ */
+VMM_INT_DECL(bool) HMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fIntercept)
+{
+    Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
+    PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
+    return RT_BOOL(pVmcbNstGstCache->u64InterceptCtrl & fIntercept);
+}
+
+
+/**
+ * Checks if the guest VMCB has the specified CR read intercept active.
+ *
+ * @returns @c true if in intercept is set, @c false otherwise.
+ * @param   pVCpu   The cross context virtual CPU structure of the calling EMT.
+ * @param   pCtx    Pointer to the context.
+ * @param   uCr     The CR register number (0 to 15).
+ */
+VMM_INT_DECL(bool) HMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
+{
+    Assert(uCr < 16);
+    Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
+    PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
+    return RT_BOOL(pVmcbNstGstCache->u16InterceptRdCRx & (1 << uCr));
+}
+
+
+/**
+ * Checks if the guest VMCB has the specified CR write intercept
+ * active.
+ *
+ * @returns @c true if in intercept is set, @c false otherwise.
+ * @param   pVCpu   The cross context virtual CPU structure of the calling EMT.
+ * @param   pCtx    Pointer to the context.
+ * @param   uCr     The CR register number (0 to 15).
+ */
+VMM_INT_DECL(bool) HMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
+{
+    Assert(uCr < 16);
+    Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
+    PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
+    return RT_BOOL(pVmcbNstGstCache->u16InterceptWrCRx & (1 << uCr));
+}
+
+
+/**
+ * Checks if the guest VMCB has the specified DR read intercept
+ * active.
+ *
+ * @returns @c true if in intercept is set, @c false otherwise.
+ * @param   pVCpu   The cross context virtual CPU structure of the calling EMT.
+ * @param   pCtx    Pointer to the context.
+ * @param   uDr     The DR register number (0 to 15).
+ */
+VMM_INT_DECL(bool) HMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
+{
+    Assert(uDr < 16);
+    Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
+    PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
+    return RT_BOOL(pVmcbNstGstCache->u16InterceptRdDRx & (1 << uDr));
+}
+
+
+/**
+ * Checks if the guest VMCB has the specified DR write intercept active.
+ *
+ * @returns @c true if in intercept is set, @c false otherwise.
+ * @param   pVCpu   The cross context virtual CPU structure of the calling EMT.
+ * @param   pCtx    Pointer to the context.
+ * @param   uDr     The DR register number (0 to 15).
+ */
+VMM_INT_DECL(bool) HMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
+{
+    Assert(uDr < 16);
+    Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
+    PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
+    return RT_BOOL(pVmcbNstGstCache->u16InterceptWrDRx & (1 << uDr));
+}
+
+
+/**
+ * Checks if the guest VMCB has the specified exception intercept active.
+ *
+ * @returns true if in intercept is active, false otherwise.
+ * @param   pVCpu       The cross context virtual CPU structure of the calling EMT.
+ * @param   pCtx        Pointer to the context.
+ * @param   uVector     The exception / interrupt vector.
+ */
+VMM_INT_DECL(bool) HMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
+{
+    Assert(uVector < 32);
+    Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
+    PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
+    return RT_BOOL(pVmcbNstGstCache->u32InterceptXcpt & (1 << uVector));
+}
+
+
+/**
+ * Checks whether the SVM nested-guest is in a state to receive physical (APIC)
+ * interrupts.
+ *
+ * @returns true if it's ready, false otherwise.
+ * @param   pCtx        The guest-CPU context.
+ *
+ * @remarks This function looks at the VMCB cache rather than directly at the
+ *          nested-guest VMCB which may have been suitably modified for executing
+ *          using hardware-assisted SVM.
+ *
+ * @sa      CPUMCanSvmNstGstTakePhysIntr.
+ */
+VMM_INT_DECL(bool) HMCanSvmNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
+{
+    Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
+    PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
+    X86EFLAGS fEFlags;
+    if (pVmcbNstGstCache->fVIntrMasking)
+        fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
+    else
+        fEFlags.u = pCtx->eflags.u;
+
+    return fEFlags.Bits.u1IF;
+}
+

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -21 +21 @@
 *********************************************************************************************************************************/
 #define LOG_GROUP LOG_GROUP_HM
+#define VMCPU_INCL_CPUM_GST_CTX
 #include <iprt/asm-amd64-x86.h>
 #include <iprt/thread.h>
@@ -2198 +2199 @@
 static void hmR0SvmVmRunSetupVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
 {
-    RT_NOREF(pVCpu);
     PSVMVMCB     pVmcbNstGst     = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
     PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
@@ -2253 +2253 @@
     Assert(pVmcbNstGst);
 
+    hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
     hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx);
     hmR0SvmLoadGuestMsrs(pVCpu, pVmcbNstGst, pCtx);
@@ -2709 +2710 @@
         HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
 
-#ifdef VBOX_WITH_NESTED_HWVIRT
-    /*
-     * We may inspect the nested-guest VMCB state in ring-3 (e.g. for injecting interrupts)
-     * and thus we need to restore any modifications we may have made to it here if we're
-     * still executing the nested-guest.
-     */
-    if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
-        HMSvmNstGstVmExitNotify(pVCpu, pCtx);
-#endif
-
     STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
 
@@ -3170 +3161 @@
 
 #ifdef VBOX_WITH_NESTED_HWVIRT
-/**
- * Checks whether the SVM nested-guest is in a state to receive physical (APIC)
- * interrupts.
- *
- * @returns true if it's ready, false otherwise.
- * @param   pCtx        The guest-CPU context.
- *
- * @remarks This function looks at the VMCB cache rather than directly at the
- *          nested-guest VMCB which may have been suitably modified for executing
- *          using hardware-assisted SVM.
- *
- * @sa      CPUMCanSvmNstGstTakePhysIntr.
- */
-static bool hmR0SvmCanNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
-{
-    Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
-    PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
-    X86EFLAGS fEFlags;
-    if (pVmcbNstGstCache->fVIntrMasking)
-        fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
-    else
-        fEFlags.u = pCtx->eflags.u;
-
-    return fEFlags.Bits.u1IF;
-}
 
 
@@ -3265 +3231 @@
          */
         PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
-        Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
         if (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)
             && !fIntShadow
             && !pVCpu->hm.s.fSingleInstruction
-            && hmR0SvmCanNstGstTakePhysIntr(pVCpu, pCtx))
+            && CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx))
         {
             if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INTR)
@@ -3753 +3718 @@
         return rc;
 
-    hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
-
     if (TRPMHasTrap(pVCpu))
         hmR0SvmTrpmTrapToPendingEvent(pVCpu);
@@ -3781 +3744 @@
     rc = hmR0SvmLoadGuestStateNested(pVCpu, pCtx);
     AssertRCReturn(rc, rc);
-    /** @todo Get new STAM counter for this? */
-    STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
-
+    STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);    /** @todo Get new STAM counter for this? */
+
+    /* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware SVM. */
     Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
 
@@ -4311 +4274 @@
     hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcbNstGst);       /* Save the nested-guest state from the VMCB to the
                                                                    guest-CPU context. */
-
-    HMSvmNstGstVmExitNotify(pVCpu, pMixedCtx);                  /* Restore modified VMCB fields for now, see @bugref{7243#c52} .*/
 }
 #endif
@@ -4752 +4713 @@
 #define HM_SVM_VMEXIT_NESTED(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
             VBOXSTRICTRC_TODO(IEMExecSvmVmexit(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2))
-#define HM_SVM_IS_CTRL_INTERCEPT_SET(a_pCtx, a_Intercept)       CPUMIsGuestSvmCtrlInterceptSet(a_pCtx, (a_Intercept))
-#define HM_SVM_IS_XCPT_INTERCEPT_SET(a_pCtx, a_Xcpt)            CPUMIsGuestSvmXcptInterceptSet(a_pCtx, (a_Xcpt))
-#define HM_SVM_IS_READ_CR_INTERCEPT_SET(a_pCtx, a_uCr)          CPUMIsGuestSvmReadCRxInterceptSet(a_pCtx, (a_uCr))
-#define HM_SVM_IS_READ_DR_INTERCEPT_SET(a_pCtx, a_uDr)          CPUMIsGuestSvmReadDRxInterceptSet(a_pCtx, (a_uDr))
-#define HM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pCtx, a_uCr)         CPUMIsGuestSvmWriteCRxInterceptSet(a_pCtx, (a_uCr))
-#define HM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pCtx, a_uDr)         CPUMIsGuestSvmWriteDRxInterceptSet(a_pCtx, (a_uDr))
 
     /*
@@ -4774 +4729 @@
         case SVM_EXIT_CPUID:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_CPUID))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
@@ -4781 +4736 @@
         case SVM_EXIT_RDTSC:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_RDTSC))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
@@ -4788 +4743 @@
         case SVM_EXIT_RDTSCP:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
@@ -4796 +4751 @@
         case SVM_EXIT_MONITOR:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_MONITOR))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
@@ -4803 +4758 @@
         case SVM_EXIT_MWAIT:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_MWAIT))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
@@ -4810 +4765 @@
         case SVM_EXIT_HLT:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_HLT))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
@@ -4817 +4772 @@
         case SVM_EXIT_MSR:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
             {
                 uint32_t const idMsr = pCtx->ecx;
@@ -4853 +4808 @@
              * Figure out if the IO port access is intercepted by the nested-guest.
              */
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
             {
                 void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
@@ -4874 +4829 @@
 
                 /* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
-                if (HM_SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_PF))
+                if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
                     return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
 
@@ -4886 +4841 @@
         case SVM_EXIT_EXCEPTION_7:   /* X86_XCPT_NM */
         {
-            if (HM_SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_NM))
+            if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_NM))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             hmR0SvmSetPendingXcptNM(pVCpu);
@@ -4894 +4849 @@
         case SVM_EXIT_EXCEPTION_6:   /* X86_XCPT_UD */
         {
-            if (HM_SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_UD))
+            if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             hmR0SvmSetPendingXcptUD(pVCpu);
@@ -4902 +4857 @@
         case SVM_EXIT_EXCEPTION_16:  /* X86_XCPT_MF */
         {
-            if (HM_SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_MF))
+            if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             hmR0SvmSetPendingXcptMF(pVCpu);
@@ -4910 +4865 @@
         case SVM_EXIT_EXCEPTION_1:   /* X86_XCPT_DB */
         {
-            if (HM_SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_DB))
+            if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmNestedExitXcptDB(pVCpu, pCtx, pSvmTransient);
@@ -4917 +4872 @@
         case SVM_EXIT_EXCEPTION_17:  /* X86_XCPT_AC */
         {
-            if (HM_SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_AC))
+            if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
@@ -4924 +4879 @@
         case SVM_EXIT_EXCEPTION_3:   /* X86_XCPT_BP */
         {
-            if (HM_SVM_IS_XCPT_INTERCEPT_SET(pCtx, X86_XCPT_BP))
+            if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmNestedExitXcptBP(pVCpu, pCtx, pSvmTransient);
@@ -4933 +4888 @@
         case SVM_EXIT_READ_CR4:
         {
-            if (HM_SVM_IS_READ_CR_INTERCEPT_SET(pCtx, (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0))))
+            uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
+            if (HMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
@@ -4943 +4899 @@
         case SVM_EXIT_WRITE_CR8:   /** @todo Shouldn't writes to CR8 go to V_TPR instead since we run with V_INTR_MASKING set?? */
         {
+            uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
             Log4(("hmR0SvmHandleExitNested: Write CRx: u16InterceptWrCRx=%#x u64ExitCode=%#RX64 %#x\n",
-                  pVmcbNstGstCtrl->u16InterceptWrCRx, pSvmTransient->u64ExitCode,
-                  (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0))));
-
-            if (HM_SVM_IS_WRITE_CR_INTERCEPT_SET(pCtx, (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0))))
+                  pVmcbNstGstCtrl->u16InterceptWrCRx, pSvmTransient->u64ExitCode, uCr));
+
+            if (HMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
@@ -4954 +4910 @@
         case SVM_EXIT_PAUSE:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_PAUSE))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
@@ -4961 +4917 @@
         case SVM_EXIT_VINTR:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_VINTR))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
@@ -4974 +4930 @@
         case SVM_EXIT_FERR_FREEZE:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
@@ -4981 +4937 @@
         case SVM_EXIT_NMI:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_NMI))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
@@ -4988 +4944 @@
         case SVM_EXIT_INVLPG:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_INVLPG))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
@@ -4995 +4951 @@
         case SVM_EXIT_WBINVD:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_WBINVD))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
@@ -5002 +4958 @@
         case SVM_EXIT_INVD:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_INVD))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
@@ -5009 +4965 @@
         case SVM_EXIT_RDPMC:
         {
-            if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_RDPMC))
+            if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
                 return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
             return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
@@ -5023 +4979 @@
                 case SVM_EXIT_READ_DR14:    case SVM_EXIT_READ_DR15:
                 {
-                    if (HM_SVM_IS_READ_DR_INTERCEPT_SET(pCtx, (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_READ_DR0))))
+                    uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
+                    if (HMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
@@ -5033 +4990 @@
                 case SVM_EXIT_WRITE_DR14:   case SVM_EXIT_WRITE_DR15:
                 {
-                    if (HM_SVM_IS_WRITE_DR_INTERCEPT_SET(pCtx, (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_DR0))))
+                    uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
+                    if (HMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
@@ -5051 +5009 @@
                 case SVM_EXIT_EXCEPTION_30:      case SVM_EXIT_EXCEPTION_31:
                 {
-                    if (HM_SVM_IS_XCPT_INTERCEPT_SET(pCtx, (uint32_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0)))
+                    uint8_t const uVector = uExitCode - SVM_EXIT_EXCEPTION_0;
+                    if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     /** @todo Write hmR0SvmExitXcptGeneric! */
@@ -5059 +5018 @@
                 case SVM_EXIT_XSETBV:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_XSETBV))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
@@ -5066 +5025 @@
                 case SVM_EXIT_TASK_SWITCH:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
@@ -5073 +5032 @@
                 case SVM_EXIT_IRET:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_IRET))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
@@ -5080 +5039 @@
                 case SVM_EXIT_SHUTDOWN:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
@@ -5087 +5046 @@
                 case SVM_EXIT_SMI:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_SMI))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SMI))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
@@ -5094 +5053 @@
                 case SVM_EXIT_INIT:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_INIT))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INIT))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
@@ -5101 +5060 @@
                 case SVM_EXIT_VMMCALL:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
@@ -5108 +5067 @@
                 case SVM_EXIT_CLGI:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_CLGI))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                      return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
@@ -5115 +5074 @@
                 case SVM_EXIT_STGI:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_STGI))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                      return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
@@ -5122 +5081 @@
                 case SVM_EXIT_VMLOAD:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
@@ -5129 +5088 @@
                 case SVM_EXIT_VMSAVE:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
@@ -5136 +5095 @@
                 case SVM_EXIT_INVLPGA:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
@@ -5143 +5102 @@
                 case SVM_EXIT_VMRUN:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_VMRUN))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
@@ -5150 +5109 @@
                 case SVM_EXIT_RSM:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_RSM))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     hmR0SvmSetPendingXcptUD(pVCpu);
@@ -5158 +5117 @@
                 case SVM_EXIT_SKINIT:
                 {
-                    if (HM_SVM_IS_CTRL_INTERCEPT_SET(pCtx, SVM_CTRL_INTERCEPT_SKINIT))
+                    if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
                         return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
                     hmR0SvmSetPendingXcptUD(pVCpu);
@@ -5182 +5141 @@
 
 #undef HM_SVM_VMEXIT_NESTED
-#undef HM_SVM_IS_CTRL_INTERCEPT_SET
-#undef HM_SVM_IS_XCPT_INTERCEPT_SET
-#undef HM_SVM_IS_READ_CR_INTERCEPT_SET
-#undef HM_SVM_IS_READ_DR_INTERCEPT_SET
-#undef HM_SVM_IS_WRITE_CR_INTERCEPT_SET
-#undef HM_SVM_IS_WRITE_DR_INTERCEPT_SET
 }
 #endif

trunk/src/VBox/VMM/VMMR3/EM.cpp

@@ -1973 +1973 @@
                 {
                     if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
-                        fIntrEnabled = CPUMCanSvmNstGstTakePhysIntr(pCtx);
+                        fIntrEnabled = CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx);
                     else
                         fIntrEnabled = pCtx->eflags.Bits.u1IF;
@@ -1987 +1987 @@
                     {
 #ifdef VBOX_WITH_NESTED_HWVIRT
-                        if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_INTR))
+                        if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
                         {
                             VBOXSTRICTRC rcStrict = IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
@@ -2027 +2027 @@
                         if (CPUMCanSvmNstGstTakeVirtIntr(pCtx))
                         {
-                            if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_VINTR))
+                            if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
                             {
                                 VBOXSTRICTRC rcStrict = IEMExecSvmVmexit(pVCpu, SVM_EXIT_VINTR, 0, 0);