Changeset 104725 in vbox for trunk/src/VBox/VMM/VMMR3/NEMR3NativeTemplate-linux.cpp.h
- Timestamp:
- May 20, 2024 3:31:01 PM (8 months ago)
- File:
-
- 1 copied
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trunk/src/VBox/VMM/VMMR3/NEMR3NativeTemplate-linux.cpp.h (copied) (copied from trunk/src/VBox/VMM/VMMR3/NEMR3Native-linux.cpp ) (18 diffs)
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trunk/src/VBox/VMM/VMMR3/NEMR3NativeTemplate-linux.cpp.h
r104693 r104725 1 1 /* $Id$ */ 2 2 /** @file 3 * NEM - Native execution manager, native ring-3 Linux backend .3 * NEM - Native execution manager, native ring-3 Linux backend, common bits for x86 and arm64. 4 4 */ 5 5 6 6 /* 7 * Copyright (C) 2021-202 3Oracle and/or its affiliates.7 * Copyright (C) 2021-2024 Oracle and/or its affiliates. 8 8 * 9 9 * This file is part of VirtualBox base platform packages, as … … 25 25 * SPDX-License-Identifier: GPL-3.0-only 26 26 */ 27 28 29 /*********************************************************************************************************************************30 * Header Files *31 *********************************************************************************************************************************/32 #define LOG_GROUP LOG_GROUP_NEM33 #define VMCPU_INCL_CPUM_GST_CTX34 #include <VBox/vmm/nem.h>35 #include <VBox/vmm/iem.h>36 #include <VBox/vmm/em.h>37 #include <VBox/vmm/apic.h>38 #include <VBox/vmm/pdm.h>39 #include <VBox/vmm/trpm.h>40 #include "NEMInternal.h"41 #include <VBox/vmm/vmcc.h>42 43 #include <iprt/alloca.h>44 #include <iprt/string.h>45 #include <iprt/system.h>46 #include <iprt/x86.h>47 48 #include <errno.h>49 #include <unistd.h>50 #include <sys/ioctl.h>51 #include <sys/fcntl.h>52 #include <sys/mman.h>53 #include <linux/kvm.h>54 27 55 28 /* … … 71 44 static int nemR3LnxInitCheckCapabilities(PVM pVM, PRTERRINFO pErrInfo) 72 45 { 73 AssertReturn(pVM->nem.s.fd Vm != -1, RTErrInfoSet(pErrInfo, VERR_WRONG_ORDER, "Wrong initalization order"));46 AssertReturn(pVM->nem.s.fdKvm != -1, RTErrInfoSet(pErrInfo, VERR_WRONG_ORDER, "Wrong initalization order")); 74 47 75 48 /* … … 93 66 94 67 CAP_ENTRY__L(KVM_CAP_IRQCHIP), /* 0 */ 68 #ifdef VBOX_VMM_TARGET_ARMV8 69 CAP_ENTRY__L(KVM_CAP_HLT), 70 #else 95 71 CAP_ENTRY_ML(KVM_CAP_HLT), 72 #endif 96 73 CAP_ENTRY__L(KVM_CAP_MMU_SHADOW_CACHE_CONTROL), 97 74 CAP_ENTRY_ML(KVM_CAP_USER_MEMORY), … … 143 120 CAP_ENTRY__L(KVM_CAP_XEN_HVM), 144 121 #endif 122 #ifdef VBOX_VMM_TARGET_ARMV8 123 CAP_ENTRY__L(KVM_CAP_ADJUST_CLOCK), 124 #else 145 125 CAP_ENTRY_ML(KVM_CAP_ADJUST_CLOCK), 126 #endif 146 127 CAP_ENTRY__L(KVM_CAP_INTERNAL_ERROR_DATA), /* 40 */ 147 128 #ifdef __KVM_HAVE_VCPU_EVENTS 148 129 CAP_ENTRY_ML(KVM_CAP_VCPU_EVENTS), 149 130 #else 150 CAP_ENTRY_ MU(41),131 CAP_ENTRY__U(41), 151 132 #endif 152 133 CAP_ENTRY__L(KVM_CAP_S390_PSW), … … 161 142 CAP_ENTRY__L(KVM_CAP_DEBUGREGS), /* 50 */ 162 143 #endif 144 #ifdef VBOX_VMM_TARGET_ARMV8 145 CAP_ENTRY__L(KVM_CAP_X86_ROBUST_SINGLESTEP), 146 #else 163 147 CAP_ENTRY__S(KVM_CAP_X86_ROBUST_SINGLESTEP, fRobustSingleStep), 148 #endif 164 149 CAP_ENTRY__L(KVM_CAP_PPC_OSI), 165 150 CAP_ENTRY__L(KVM_CAP_PPC_UNSET_IRQ), … … 168 153 CAP_ENTRY_ML(KVM_CAP_XSAVE), 169 154 #else 170 CAP_ENTRY_ MU(55),155 CAP_ENTRY__U(55), 171 156 #endif 172 157 #ifdef __KVM_HAVE_XCRS 173 158 CAP_ENTRY_ML(KVM_CAP_XCRS), 174 159 #else 175 CAP_ENTRY_ MU(56),160 CAP_ENTRY__U(56), 176 161 #endif 177 162 CAP_ENTRY__L(KVM_CAP_PPC_GET_PVINFO), … … 205 190 CAP_ENTRY__L(KVM_CAP_S390_CSS_SUPPORT), 206 191 CAP_ENTRY__L(KVM_CAP_PPC_EPR), 192 #ifdef VBOX_VMM_TARGET_ARMV8 193 CAP_ENTRY_ML(KVM_CAP_ARM_PSCI), 194 CAP_ENTRY_ML(KVM_CAP_ARM_SET_DEVICE_ADDR), 195 CAP_ENTRY_ML(KVM_CAP_DEVICE_CTRL), 196 #else 207 197 CAP_ENTRY__L(KVM_CAP_ARM_PSCI), 208 198 CAP_ENTRY__L(KVM_CAP_ARM_SET_DEVICE_ADDR), 209 199 CAP_ENTRY__L(KVM_CAP_DEVICE_CTRL), 200 #endif 210 201 CAP_ENTRY__L(KVM_CAP_IRQ_MPIC), /* 90 */ 211 202 CAP_ENTRY__L(KVM_CAP_PPC_RTAS), … … 220 211 CAP_ENTRY__L(KVM_CAP_IOEVENTFD_NO_LENGTH), /* 100 */ 221 212 CAP_ENTRY__L(KVM_CAP_VM_ATTRIBUTES), 213 #ifdef VBOX_VMM_TARGET_ARMV8 214 CAP_ENTRY_ML(KVM_CAP_ARM_PSCI_0_2), 215 #else 222 216 CAP_ENTRY__L(KVM_CAP_ARM_PSCI_0_2), 217 #endif 223 218 CAP_ENTRY__L(KVM_CAP_PPC_FIXUP_HCALL), 224 219 CAP_ENTRY__L(KVM_CAP_PPC_ENABLE_HCALL), … … 283 278 CAP_ENTRY__L(KVM_CAP_HYPERV_ENLIGHTENED_VMCS), 284 279 CAP_ENTRY__L(KVM_CAP_EXCEPTION_PAYLOAD), 280 #ifdef VBOX_VMM_TARGET_ARMV8 281 CAP_ENTRY_MS(KVM_CAP_ARM_VM_IPA_SIZE, cIpaBits), 282 #else 285 283 CAP_ENTRY__L(KVM_CAP_ARM_VM_IPA_SIZE), 284 #endif 286 285 CAP_ENTRY__L(KVM_CAP_MANUAL_DIRTY_LOG_PROTECT), 287 286 CAP_ENTRY__L(KVM_CAP_HYPERV_CPUID), … … 306 305 CAP_ENTRY__L(KVM_CAP_S390_DIAG318), 307 306 CAP_ENTRY__L(KVM_CAP_STEAL_TIME), 307 #ifdef VBOX_VMM_TARGET_ARMV8 308 CAP_ENTRY__L(KVM_CAP_X86_USER_SPACE_MSR), /* (since 5.10) */ 309 CAP_ENTRY__L(KVM_CAP_X86_MSR_FILTER), 310 #else 308 311 CAP_ENTRY_ML(KVM_CAP_X86_USER_SPACE_MSR), /* (since 5.10) */ 309 312 CAP_ENTRY_ML(KVM_CAP_X86_MSR_FILTER), 313 #endif 310 314 CAP_ENTRY__L(KVM_CAP_ENFORCE_PV_FEATURE_CPUID), /* 190 */ 311 315 CAP_ENTRY__L(KVM_CAP_SYS_HYPERV_CPUID), … … 341 345 for (unsigned i = 0; i < RT_ELEMENTS(s_aCaps); i++) 342 346 { 343 int rc = ioctl(pVM->nem.s.fd Vm, KVM_CHECK_EXTENSION, s_aCaps[i].iCap);347 int rc = ioctl(pVM->nem.s.fdKvm, KVM_CHECK_EXTENSION, s_aCaps[i].iCap); 344 348 if (rc >= 10) 345 349 LogRel(("NEM: %36s: %#x (%d)\n", s_aCaps[i].pszName, rc, rc)); … … 416 420 417 421 418 /**419 * Does the early setup of a KVM VM.420 *421 * @returns VBox status code.422 * @param pVM The cross context VM structure.423 * @param pErrInfo Where to always return error info.424 */425 static int nemR3LnxInitSetupVm(PVM pVM, PRTERRINFO pErrInfo)426 {427 AssertReturn(pVM->nem.s.fdVm != -1, RTErrInfoSet(pErrInfo, VERR_WRONG_ORDER, "Wrong initalization order"));428 429 /*430 * Enable user space MSRs and let us check everything KVM cannot handle.431 * We will set up filtering later when ring-3 init has completed.432 */433 struct kvm_enable_cap CapEn =434 {435 KVM_CAP_X86_USER_SPACE_MSR, 0,436 { KVM_MSR_EXIT_REASON_FILTER | KVM_MSR_EXIT_REASON_UNKNOWN | KVM_MSR_EXIT_REASON_INVAL, 0, 0, 0}437 };438 int rcLnx = ioctl(pVM->nem.s.fdVm, KVM_ENABLE_CAP, &CapEn);439 if (rcLnx == -1)440 return RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "Failed to enable KVM_CAP_X86_USER_SPACE_MSR failed: %u", errno);441 442 /*443 * Create the VCpus.444 */445 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)446 {447 PVMCPU pVCpu = pVM->apCpusR3[idCpu];448 449 /* Create it. */450 pVCpu->nem.s.fdVCpu = ioctl(pVM->nem.s.fdVm, KVM_CREATE_VCPU, (unsigned long)idCpu);451 if (pVCpu->nem.s.fdVCpu < 0)452 return RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "KVM_CREATE_VCPU failed for VCpu #%u: %d", idCpu, errno);453 454 /* Map the KVM_RUN area. */455 pVCpu->nem.s.pRun = (struct kvm_run *)mmap(NULL, pVM->nem.s.cbVCpuMmap, PROT_READ | PROT_WRITE, MAP_SHARED,456 pVCpu->nem.s.fdVCpu, 0 /*offset*/);457 if ((void *)pVCpu->nem.s.pRun == MAP_FAILED)458 return RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "mmap failed for VCpu #%u: %d", idCpu, errno);459 460 /* We want all x86 registers and events on each exit. */461 pVCpu->nem.s.pRun->kvm_valid_regs = KVM_SYNC_X86_REGS | KVM_SYNC_X86_SREGS | KVM_SYNC_X86_EVENTS;462 }463 return VINF_SUCCESS;464 }465 466 467 422 /** @callback_method_impl{FNVMMEMTRENDEZVOUS} */ 468 423 static DECLCALLBACK(VBOXSTRICTRC) nemR3LnxFixThreadPoke(PVM pVM, PVMCPU pVCpu, void *pvUser) … … 519 474 520 475 /* 521 * Create an empty VM since it is recommended we check capabilities on 522 * the VM rather than the system descriptor. 476 * Check capabilities. 523 477 */ 524 int fdVm = ioctl(fdKvm, KVM_CREATE_VM, 0UL /* Type must be zero on x86 */);525 if ( fdVm >= 0)478 rc = nemR3LnxInitCheckCapabilities(pVM, pErrInfo); 479 if (RT_SUCCESS(rc)) 526 480 { 527 pVM->nem.s.fdVm = fdVm;528 529 481 /* 530 * Check capabilities. 482 * Create an empty VM since it is recommended we check capabilities on 483 * the VM rather than the system descriptor. 531 484 */ 532 rc = nemR3LnxInitCheckCapabilities(pVM, pErrInfo); 533 if (RT_SUCCESS(rc)) 485 #ifdef VBOX_VMM_TARGET_ARMV8 486 int fdVm = ioctl(fdKvm, KVM_CREATE_VM, pVM->nem.s.cIpaBits); 487 #else 488 int fdVm = ioctl(fdKvm, KVM_CREATE_VM, 0UL /* Type must be zero on x86 */); 489 #endif 490 if (fdVm >= 0) 534 491 { 492 pVM->nem.s.fdVm = fdVm; 493 535 494 /* 536 495 * Set up the VM (more on this later). … … 585 544 return VINF_SUCCESS; 586 545 } 546 close(fdVm); 547 pVM->nem.s.fdVm = -1; 587 548 588 549 /* … … 590 551 */ 591 552 } 592 close(fdVm);593 pVM->nem.s.fdVm = -1;553 else 554 rc = RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "KVM_CREATE_VM failed: %u", errno); 594 555 } 595 else596 rc = RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "KVM_CREATE_VM failed: %u", errno);597 556 close(fdKvm); 598 557 pVM->nem.s.fdKvm = -1; … … 633 592 634 593 /** @todo */ 635 636 return VINF_SUCCESS;637 }638 639 640 /**641 * Update the CPUID leaves for a VCPU.642 *643 * The KVM_SET_CPUID2 call replaces any previous leaves, so we have to redo644 * everything when there really just are single bit changes. That said, it645 * looks like KVM update the XCR/XSAVE related stuff as well as the APIC enabled646 * bit(s), so it should suffice if we do this at startup, I hope.647 */648 static int nemR3LnxUpdateCpuIdsLeaves(PVM pVM, PVMCPU pVCpu)649 {650 uint32_t cLeaves = 0;651 PCCPUMCPUIDLEAF const paLeaves = CPUMR3CpuIdGetPtr(pVM, &cLeaves);652 struct kvm_cpuid2 *pReq = (struct kvm_cpuid2 *)alloca(RT_UOFFSETOF_DYN(struct kvm_cpuid2, entries[cLeaves + 2]));653 654 pReq->nent = cLeaves;655 pReq->padding = 0;656 657 for (uint32_t i = 0; i < cLeaves; i++)658 {659 CPUMGetGuestCpuId(pVCpu, paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, -1 /*f64BitMode*/,660 &pReq->entries[i].eax,661 &pReq->entries[i].ebx,662 &pReq->entries[i].ecx,663 &pReq->entries[i].edx);664 pReq->entries[i].function = paLeaves[i].uLeaf;665 pReq->entries[i].index = paLeaves[i].uSubLeaf;666 pReq->entries[i].flags = !paLeaves[i].fSubLeafMask ? 0 : KVM_CPUID_FLAG_SIGNIFCANT_INDEX;667 pReq->entries[i].padding[0] = 0;668 pReq->entries[i].padding[1] = 0;669 pReq->entries[i].padding[2] = 0;670 }671 672 int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_CPUID2, pReq);673 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d cLeaves=%#x\n", rcLnx, errno, cLeaves), RTErrConvertFromErrno(errno));674 675 return VINF_SUCCESS;676 }677 678 679 int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)680 {681 /*682 * Make RTThreadPoke work again (disabled for avoiding unnecessary683 * critical section issues in ring-0).684 */685 if (enmWhat == VMINITCOMPLETED_RING3)686 VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ALL_AT_ONCE, nemR3LnxFixThreadPoke, NULL);687 688 /*689 * Configure CPUIDs after ring-3 init has been done.690 */691 if (enmWhat == VMINITCOMPLETED_RING3)692 {693 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)694 {695 int rc = nemR3LnxUpdateCpuIdsLeaves(pVM, pVM->apCpusR3[idCpu]);696 AssertRCReturn(rc, rc);697 }698 }699 700 /*701 * Configure MSRs after ring-3 init is done.702 *703 * We only need to tell KVM which MSRs it can handle, as we already704 * requested KVM_MSR_EXIT_REASON_FILTER, KVM_MSR_EXIT_REASON_UNKNOWN705 * and KVM_MSR_EXIT_REASON_INVAL in nemR3LnxInitSetupVm, and here we706 * will use KVM_MSR_FILTER_DEFAULT_DENY. So, all MSRs w/o a 1 in the707 * bitmaps should be deferred to ring-3.708 */709 if (enmWhat == VMINITCOMPLETED_RING3)710 {711 struct kvm_msr_filter MsrFilters = {0}; /* Structure with a couple of implicit paddings on 64-bit systems. */712 MsrFilters.flags = KVM_MSR_FILTER_DEFAULT_DENY;713 714 unsigned iRange = 0;715 #define MSR_RANGE_BEGIN(a_uBase, a_uEnd, a_fFlags) \716 AssertCompile(0x3000 <= KVM_MSR_FILTER_MAX_BITMAP_SIZE * 8); \717 uint64_t RT_CONCAT(bm, a_uBase)[0x3000 / 64] = {0}; \718 do { \719 uint64_t * const pbm = RT_CONCAT(bm, a_uBase); \720 uint32_t const uBase = UINT32_C(a_uBase); \721 uint32_t const cMsrs = UINT32_C(a_uEnd) - UINT32_C(a_uBase); \722 MsrFilters.ranges[iRange].base = UINT32_C(a_uBase); \723 MsrFilters.ranges[iRange].nmsrs = cMsrs; \724 MsrFilters.ranges[iRange].flags = (a_fFlags); \725 MsrFilters.ranges[iRange].bitmap = (uint8_t *)&RT_CONCAT(bm, a_uBase)[0]726 #define MSR_RANGE_ADD(a_Msr) \727 do { Assert((uint32_t)(a_Msr) - uBase < cMsrs); ASMBitSet(pbm, (uint32_t)(a_Msr) - uBase); } while (0)728 #define MSR_RANGE_END(a_cMinMsrs) \729 /* optimize the range size before closing: */ \730 uint32_t cBitmap = cMsrs / 64; \731 while (cBitmap > ((a_cMinMsrs) + 63 / 64) && pbm[cBitmap - 1] == 0) \732 cBitmap -= 1; \733 MsrFilters.ranges[iRange].nmsrs = cBitmap * 64; \734 iRange++; \735 } while (0)736 737 /* 1st Intel range: 0000_0000 to 0000_3000. */738 MSR_RANGE_BEGIN(0x00000000, 0x00003000, KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE);739 MSR_RANGE_ADD(MSR_IA32_TSC);740 MSR_RANGE_ADD(MSR_IA32_SYSENTER_CS);741 MSR_RANGE_ADD(MSR_IA32_SYSENTER_ESP);742 MSR_RANGE_ADD(MSR_IA32_SYSENTER_EIP);743 MSR_RANGE_ADD(MSR_IA32_CR_PAT);744 /** @todo more? */745 MSR_RANGE_END(64);746 747 /* 1st AMD range: c000_0000 to c000_3000 */748 MSR_RANGE_BEGIN(0xc0000000, 0xc0003000, KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE);749 MSR_RANGE_ADD(MSR_K6_EFER);750 MSR_RANGE_ADD(MSR_K6_STAR);751 MSR_RANGE_ADD(MSR_K8_GS_BASE);752 MSR_RANGE_ADD(MSR_K8_KERNEL_GS_BASE);753 MSR_RANGE_ADD(MSR_K8_LSTAR);754 MSR_RANGE_ADD(MSR_K8_CSTAR);755 MSR_RANGE_ADD(MSR_K8_SF_MASK);756 MSR_RANGE_ADD(MSR_K8_TSC_AUX);757 /** @todo add more? */758 MSR_RANGE_END(64);759 760 /** @todo Specify other ranges too? Like hyper-V and KVM to make sure we get761 * the MSR requests instead of KVM. */762 763 int rcLnx = ioctl(pVM->nem.s.fdVm, KVM_X86_SET_MSR_FILTER, &MsrFilters);764 if (rcLnx == -1)765 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,766 "Failed to enable KVM_X86_SET_MSR_FILTER failed: %u", errno);767 }768 594 769 595 return VINF_SUCCESS; … … 1186 1012 RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State); 1187 1013 } 1188 1189 1190 /*********************************************************************************************************************************1191 * CPU State *1192 *********************************************************************************************************************************/1193 1194 /**1195 * Worker that imports selected state from KVM.1196 */1197 static int nemHCLnxImportState(PVMCPUCC pVCpu, uint64_t fWhat, PCPUMCTX pCtx, struct kvm_run *pRun)1198 {1199 fWhat &= pVCpu->cpum.GstCtx.fExtrn;1200 if (!fWhat)1201 return VINF_SUCCESS;1202 1203 /*1204 * Stuff that goes into kvm_run::s.regs.regs:1205 */1206 if (fWhat & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_GPRS_MASK))1207 {1208 if (fWhat & CPUMCTX_EXTRN_RIP)1209 pCtx->rip = pRun->s.regs.regs.rip;1210 if (fWhat & CPUMCTX_EXTRN_RFLAGS)1211 pCtx->rflags.u = pRun->s.regs.regs.rflags;1212 1213 if (fWhat & CPUMCTX_EXTRN_RAX)1214 pCtx->rax = pRun->s.regs.regs.rax;1215 if (fWhat & CPUMCTX_EXTRN_RCX)1216 pCtx->rcx = pRun->s.regs.regs.rcx;1217 if (fWhat & CPUMCTX_EXTRN_RDX)1218 pCtx->rdx = pRun->s.regs.regs.rdx;1219 if (fWhat & CPUMCTX_EXTRN_RBX)1220 pCtx->rbx = pRun->s.regs.regs.rbx;1221 if (fWhat & CPUMCTX_EXTRN_RSP)1222 pCtx->rsp = pRun->s.regs.regs.rsp;1223 if (fWhat & CPUMCTX_EXTRN_RBP)1224 pCtx->rbp = pRun->s.regs.regs.rbp;1225 if (fWhat & CPUMCTX_EXTRN_RSI)1226 pCtx->rsi = pRun->s.regs.regs.rsi;1227 if (fWhat & CPUMCTX_EXTRN_RDI)1228 pCtx->rdi = pRun->s.regs.regs.rdi;1229 if (fWhat & CPUMCTX_EXTRN_R8_R15)1230 {1231 pCtx->r8 = pRun->s.regs.regs.r8;1232 pCtx->r9 = pRun->s.regs.regs.r9;1233 pCtx->r10 = pRun->s.regs.regs.r10;1234 pCtx->r11 = pRun->s.regs.regs.r11;1235 pCtx->r12 = pRun->s.regs.regs.r12;1236 pCtx->r13 = pRun->s.regs.regs.r13;1237 pCtx->r14 = pRun->s.regs.regs.r14;1238 pCtx->r15 = pRun->s.regs.regs.r15;1239 }1240 }1241 1242 /*1243 * Stuff that goes into kvm_run::s.regs.sregs.1244 *1245 * Note! The apic_base can be ignored because we gets all MSR writes to it1246 * and VBox always keeps the correct value.1247 */1248 bool fMaybeChangedMode = false;1249 bool fUpdateCr3 = false;1250 if (fWhat & ( CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_TABLE_MASK | CPUMCTX_EXTRN_CR_MASK1251 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_APIC_TPR))1252 {1253 /** @todo what about Attr.n.u4LimitHigh? */1254 #define NEM_LNX_IMPORT_SEG(a_CtxSeg, a_KvmSeg) do { \1255 (a_CtxSeg).u64Base = (a_KvmSeg).base; \1256 (a_CtxSeg).u32Limit = (a_KvmSeg).limit; \1257 (a_CtxSeg).ValidSel = (a_CtxSeg).Sel = (a_KvmSeg).selector; \1258 (a_CtxSeg).Attr.n.u4Type = (a_KvmSeg).type; \1259 (a_CtxSeg).Attr.n.u1DescType = (a_KvmSeg).s; \1260 (a_CtxSeg).Attr.n.u2Dpl = (a_KvmSeg).dpl; \1261 (a_CtxSeg).Attr.n.u1Present = (a_KvmSeg).present; \1262 (a_CtxSeg).Attr.n.u1Available = (a_KvmSeg).avl; \1263 (a_CtxSeg).Attr.n.u1Long = (a_KvmSeg).l; \1264 (a_CtxSeg).Attr.n.u1DefBig = (a_KvmSeg).db; \1265 (a_CtxSeg).Attr.n.u1Granularity = (a_KvmSeg).g; \1266 (a_CtxSeg).Attr.n.u1Unusable = (a_KvmSeg).unusable; \1267 (a_CtxSeg).fFlags = CPUMSELREG_FLAGS_VALID; \1268 CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &(a_CtxSeg)); \1269 } while (0)1270 1271 if (fWhat & CPUMCTX_EXTRN_SREG_MASK)1272 {1273 if (fWhat & CPUMCTX_EXTRN_ES)1274 NEM_LNX_IMPORT_SEG(pCtx->es, pRun->s.regs.sregs.es);1275 if (fWhat & CPUMCTX_EXTRN_CS)1276 NEM_LNX_IMPORT_SEG(pCtx->cs, pRun->s.regs.sregs.cs);1277 if (fWhat & CPUMCTX_EXTRN_SS)1278 NEM_LNX_IMPORT_SEG(pCtx->ss, pRun->s.regs.sregs.ss);1279 if (fWhat & CPUMCTX_EXTRN_DS)1280 NEM_LNX_IMPORT_SEG(pCtx->ds, pRun->s.regs.sregs.ds);1281 if (fWhat & CPUMCTX_EXTRN_FS)1282 NEM_LNX_IMPORT_SEG(pCtx->fs, pRun->s.regs.sregs.fs);1283 if (fWhat & CPUMCTX_EXTRN_GS)1284 NEM_LNX_IMPORT_SEG(pCtx->gs, pRun->s.regs.sregs.gs);1285 }1286 if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)1287 {1288 if (fWhat & CPUMCTX_EXTRN_GDTR)1289 {1290 pCtx->gdtr.pGdt = pRun->s.regs.sregs.gdt.base;1291 pCtx->gdtr.cbGdt = pRun->s.regs.sregs.gdt.limit;1292 }1293 if (fWhat & CPUMCTX_EXTRN_IDTR)1294 {1295 pCtx->idtr.pIdt = pRun->s.regs.sregs.idt.base;1296 pCtx->idtr.cbIdt = pRun->s.regs.sregs.idt.limit;1297 }1298 if (fWhat & CPUMCTX_EXTRN_LDTR)1299 NEM_LNX_IMPORT_SEG(pCtx->ldtr, pRun->s.regs.sregs.ldt);1300 if (fWhat & CPUMCTX_EXTRN_TR)1301 NEM_LNX_IMPORT_SEG(pCtx->tr, pRun->s.regs.sregs.tr);1302 }1303 if (fWhat & CPUMCTX_EXTRN_CR_MASK)1304 {1305 if (fWhat & CPUMCTX_EXTRN_CR0)1306 {1307 if (pVCpu->cpum.GstCtx.cr0 != pRun->s.regs.sregs.cr0)1308 {1309 CPUMSetGuestCR0(pVCpu, pRun->s.regs.sregs.cr0);1310 fMaybeChangedMode = true;1311 }1312 }1313 if (fWhat & CPUMCTX_EXTRN_CR2)1314 pCtx->cr2 = pRun->s.regs.sregs.cr2;1315 if (fWhat & CPUMCTX_EXTRN_CR3)1316 {1317 if (pCtx->cr3 != pRun->s.regs.sregs.cr3)1318 {1319 CPUMSetGuestCR3(pVCpu, pRun->s.regs.sregs.cr3);1320 fUpdateCr3 = true;1321 }1322 }1323 if (fWhat & CPUMCTX_EXTRN_CR4)1324 {1325 if (pCtx->cr4 != pRun->s.regs.sregs.cr4)1326 {1327 CPUMSetGuestCR4(pVCpu, pRun->s.regs.sregs.cr4);1328 fMaybeChangedMode = true;1329 }1330 }1331 }1332 if (fWhat & CPUMCTX_EXTRN_APIC_TPR)1333 APICSetTpr(pVCpu, (uint8_t)pRun->s.regs.sregs.cr8 << 4);1334 if (fWhat & CPUMCTX_EXTRN_EFER)1335 {1336 if (pCtx->msrEFER != pRun->s.regs.sregs.efer)1337 {1338 Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, pRun->s.regs.sregs.efer));1339 if ((pRun->s.regs.sregs.efer ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)1340 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pRun->s.regs.sregs.efer & MSR_K6_EFER_NXE));1341 pCtx->msrEFER = pRun->s.regs.sregs.efer;1342 fMaybeChangedMode = true;1343 }1344 }1345 #undef NEM_LNX_IMPORT_SEG1346 }1347 1348 /*1349 * Debug registers.1350 */1351 if (fWhat & CPUMCTX_EXTRN_DR_MASK)1352 {1353 struct kvm_debugregs DbgRegs = {{0}};1354 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_DEBUGREGS, &DbgRegs);1355 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);1356 1357 if (fWhat & CPUMCTX_EXTRN_DR0_DR3)1358 {1359 pCtx->dr[0] = DbgRegs.db[0];1360 pCtx->dr[1] = DbgRegs.db[1];1361 pCtx->dr[2] = DbgRegs.db[2];1362 pCtx->dr[3] = DbgRegs.db[3];1363 }1364 if (fWhat & CPUMCTX_EXTRN_DR6)1365 pCtx->dr[6] = DbgRegs.dr6;1366 if (fWhat & CPUMCTX_EXTRN_DR7)1367 pCtx->dr[7] = DbgRegs.dr7;1368 }1369 1370 /*1371 * FPU, SSE, AVX, ++.1372 */1373 if (fWhat & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx))1374 {1375 if (fWhat & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE))1376 {1377 fWhat |= CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE; /* we do all or nothing at all */1378 1379 AssertCompile(sizeof(pCtx->XState) >= sizeof(struct kvm_xsave));1380 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_XSAVE, &pCtx->XState);1381 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);1382 }1383 1384 if (fWhat & CPUMCTX_EXTRN_XCRx)1385 {1386 struct kvm_xcrs Xcrs =1387 { /*.nr_xcrs = */ 2,1388 /*.flags = */ 0,1389 /*.xcrs= */ {1390 { /*.xcr =*/ 0, /*.reserved=*/ 0, /*.value=*/ pCtx->aXcr[0] },1391 { /*.xcr =*/ 1, /*.reserved=*/ 0, /*.value=*/ pCtx->aXcr[1] },1392 }1393 };1394 1395 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_XCRS, &Xcrs);1396 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);1397 1398 pCtx->aXcr[0] = Xcrs.xcrs[0].value;1399 pCtx->aXcr[1] = Xcrs.xcrs[1].value;1400 }1401 }1402 1403 /*1404 * MSRs.1405 */1406 if (fWhat & ( CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_SYSCALL_MSRS | CPUMCTX_EXTRN_SYSENTER_MSRS1407 | CPUMCTX_EXTRN_TSC_AUX | CPUMCTX_EXTRN_OTHER_MSRS))1408 {1409 union1410 {1411 struct kvm_msrs Core;1412 uint64_t padding[2 + sizeof(struct kvm_msr_entry) * 32];1413 } uBuf;1414 uint64_t *pauDsts[32];1415 uint32_t iMsr = 0;1416 PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);1417 1418 #define ADD_MSR(a_Msr, a_uValue) do { \1419 Assert(iMsr < 32); \1420 uBuf.Core.entries[iMsr].index = (a_Msr); \1421 uBuf.Core.entries[iMsr].reserved = 0; \1422 uBuf.Core.entries[iMsr].data = UINT64_MAX; \1423 pauDsts[iMsr] = &(a_uValue); \1424 iMsr += 1; \1425 } while (0)1426 1427 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)1428 ADD_MSR(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);1429 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)1430 {1431 ADD_MSR(MSR_K6_STAR, pCtx->msrSTAR);1432 ADD_MSR(MSR_K8_LSTAR, pCtx->msrLSTAR);1433 ADD_MSR(MSR_K8_CSTAR, pCtx->msrCSTAR);1434 ADD_MSR(MSR_K8_SF_MASK, pCtx->msrSFMASK);1435 }1436 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)1437 {1438 ADD_MSR(MSR_IA32_SYSENTER_CS, pCtx->SysEnter.cs);1439 ADD_MSR(MSR_IA32_SYSENTER_EIP, pCtx->SysEnter.eip);1440 ADD_MSR(MSR_IA32_SYSENTER_ESP, pCtx->SysEnter.esp);1441 }1442 if (fWhat & CPUMCTX_EXTRN_TSC_AUX)1443 ADD_MSR(MSR_K8_TSC_AUX, pCtxMsrs->msr.TscAux);1444 if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)1445 {1446 ADD_MSR(MSR_IA32_CR_PAT, pCtx->msrPAT);1447 /** @todo What do we _have_ to add here?1448 * We also have: Mttr*, MiscEnable, FeatureControl. */1449 }1450 1451 uBuf.Core.pad = 0;1452 uBuf.Core.nmsrs = iMsr;1453 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_MSRS, &uBuf);1454 AssertMsgReturn(rc == (int)iMsr,1455 ("rc=%d iMsr=%d (->%#x) errno=%d\n",1456 rc, iMsr, (uint32_t)rc < iMsr ? uBuf.Core.entries[rc].index : 0, errno),1457 VERR_NEM_IPE_3);1458 1459 while (iMsr-- > 0)1460 *pauDsts[iMsr] = uBuf.Core.entries[iMsr].data;1461 #undef ADD_MSR1462 }1463 1464 /*1465 * Interruptibility state and pending interrupts.1466 */1467 if (fWhat & (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI))1468 {1469 fWhat |= CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI; /* always do both, see export and interrupt FF handling */1470 1471 struct kvm_vcpu_events KvmEvents = {0};1472 int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_VCPU_EVENTS, &KvmEvents);1473 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_3);1474 1475 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_RIP)1476 pVCpu->cpum.GstCtx.rip = pRun->s.regs.regs.rip;1477 1478 CPUMUpdateInterruptShadowSsStiEx(&pVCpu->cpum.GstCtx,1479 RT_BOOL(KvmEvents.interrupt.shadow & KVM_X86_SHADOW_INT_MOV_SS),1480 RT_BOOL(KvmEvents.interrupt.shadow & KVM_X86_SHADOW_INT_STI),1481 pVCpu->cpum.GstCtx.rip);1482 CPUMUpdateInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx, KvmEvents.nmi.masked != 0);1483 1484 if (KvmEvents.interrupt.injected)1485 {1486 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportPendingInterrupt);1487 TRPMAssertTrap(pVCpu, KvmEvents.interrupt.nr, !KvmEvents.interrupt.soft ? TRPM_HARDWARE_INT : TRPM_SOFTWARE_INT);1488 }1489 1490 Assert(KvmEvents.nmi.injected == 0);1491 Assert(KvmEvents.nmi.pending == 0);1492 }1493 1494 /*1495 * Update the external mask.1496 */1497 pCtx->fExtrn &= ~fWhat;1498 pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;1499 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))1500 pVCpu->cpum.GstCtx.fExtrn = 0;1501 1502 /*1503 * We sometimes need to update PGM on the guest status.1504 */1505 if (!fMaybeChangedMode && !fUpdateCr3)1506 { /* likely */ }1507 else1508 {1509 /*1510 * Make sure we got all the state PGM might need.1511 */1512 Log7(("nemHCLnxImportState: fMaybeChangedMode=%d fUpdateCr3=%d fExtrnNeeded=%#RX64\n", fMaybeChangedMode, fUpdateCr3,1513 pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_EFER) ));1514 if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_EFER))1515 {1516 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR0)1517 {1518 if (pVCpu->cpum.GstCtx.cr0 != pRun->s.regs.sregs.cr0)1519 {1520 CPUMSetGuestCR0(pVCpu, pRun->s.regs.sregs.cr0);1521 fMaybeChangedMode = true;1522 }1523 }1524 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR3)1525 {1526 if (pCtx->cr3 != pRun->s.regs.sregs.cr3)1527 {1528 CPUMSetGuestCR3(pVCpu, pRun->s.regs.sregs.cr3);1529 fUpdateCr3 = true;1530 }1531 }1532 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR4)1533 {1534 if (pCtx->cr4 != pRun->s.regs.sregs.cr4)1535 {1536 CPUMSetGuestCR4(pVCpu, pRun->s.regs.sregs.cr4);1537 fMaybeChangedMode = true;1538 }1539 }1540 if (fWhat & CPUMCTX_EXTRN_EFER)1541 {1542 if (pCtx->msrEFER != pRun->s.regs.sregs.efer)1543 {1544 Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, pRun->s.regs.sregs.efer));1545 if ((pRun->s.regs.sregs.efer ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)1546 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pRun->s.regs.sregs.efer & MSR_K6_EFER_NXE));1547 pCtx->msrEFER = pRun->s.regs.sregs.efer;1548 fMaybeChangedMode = true;1549 }1550 }1551 1552 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_EFER);1553 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))1554 pVCpu->cpum.GstCtx.fExtrn = 0;1555 }1556 1557 /*1558 * Notify PGM about the changes.1559 */1560 if (fMaybeChangedMode)1561 {1562 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4,1563 pVCpu->cpum.GstCtx.msrEFER, false /*fForce*/);1564 AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_1);1565 }1566 1567 if (fUpdateCr3)1568 {1569 int rc = PGMUpdateCR3(pVCpu, pVCpu->cpum.GstCtx.cr3);1570 if (rc == VINF_SUCCESS)1571 { /* likely */ }1572 else1573 AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_2);1574 }1575 }1576 1577 return VINF_SUCCESS;1578 }1579 1580 1581 /**1582 * Interface for importing state on demand (used by IEM).1583 *1584 * @returns VBox status code.1585 * @param pVCpu The cross context CPU structure.1586 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.1587 */1588 VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)1589 {1590 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);1591 return nemHCLnxImportState(pVCpu, fWhat, &pVCpu->cpum.GstCtx, pVCpu->nem.s.pRun);1592 }1593 1594 1595 /**1596 * Exports state to KVM.1597 */1598 static int nemHCLnxExportState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, struct kvm_run *pRun)1599 {1600 uint64_t const fExtrn = ~pCtx->fExtrn & CPUMCTX_EXTRN_ALL;1601 Assert((~fExtrn & CPUMCTX_EXTRN_ALL) != CPUMCTX_EXTRN_ALL);1602 1603 /*1604 * Stuff that goes into kvm_run::s.regs.regs:1605 */1606 if (fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_GPRS_MASK))1607 {1608 if (fExtrn & CPUMCTX_EXTRN_RIP)1609 pRun->s.regs.regs.rip = pCtx->rip;1610 if (fExtrn & CPUMCTX_EXTRN_RFLAGS)1611 pRun->s.regs.regs.rflags = pCtx->rflags.u;1612 1613 if (fExtrn & CPUMCTX_EXTRN_RAX)1614 pRun->s.regs.regs.rax = pCtx->rax;1615 if (fExtrn & CPUMCTX_EXTRN_RCX)1616 pRun->s.regs.regs.rcx = pCtx->rcx;1617 if (fExtrn & CPUMCTX_EXTRN_RDX)1618 pRun->s.regs.regs.rdx = pCtx->rdx;1619 if (fExtrn & CPUMCTX_EXTRN_RBX)1620 pRun->s.regs.regs.rbx = pCtx->rbx;1621 if (fExtrn & CPUMCTX_EXTRN_RSP)1622 pRun->s.regs.regs.rsp = pCtx->rsp;1623 if (fExtrn & CPUMCTX_EXTRN_RBP)1624 pRun->s.regs.regs.rbp = pCtx->rbp;1625 if (fExtrn & CPUMCTX_EXTRN_RSI)1626 pRun->s.regs.regs.rsi = pCtx->rsi;1627 if (fExtrn & CPUMCTX_EXTRN_RDI)1628 pRun->s.regs.regs.rdi = pCtx->rdi;1629 if (fExtrn & CPUMCTX_EXTRN_R8_R15)1630 {1631 pRun->s.regs.regs.r8 = pCtx->r8;1632 pRun->s.regs.regs.r9 = pCtx->r9;1633 pRun->s.regs.regs.r10 = pCtx->r10;1634 pRun->s.regs.regs.r11 = pCtx->r11;1635 pRun->s.regs.regs.r12 = pCtx->r12;1636 pRun->s.regs.regs.r13 = pCtx->r13;1637 pRun->s.regs.regs.r14 = pCtx->r14;1638 pRun->s.regs.regs.r15 = pCtx->r15;1639 }1640 pRun->kvm_dirty_regs |= KVM_SYNC_X86_REGS;1641 }1642 1643 /*1644 * Stuff that goes into kvm_run::s.regs.sregs:1645 *1646 * The APIC base register updating is a little suboptimal... But at least1647 * VBox always has the right base register value, so it's one directional.1648 */1649 uint64_t const uApicBase = APICGetBaseMsrNoCheck(pVCpu);1650 if ( (fExtrn & ( CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_TABLE_MASK | CPUMCTX_EXTRN_CR_MASK1651 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_APIC_TPR))1652 || uApicBase != pVCpu->nem.s.uKvmApicBase)1653 {1654 if ((pVCpu->nem.s.uKvmApicBase ^ uApicBase) & MSR_IA32_APICBASE_EN)1655 Log(("NEM/%u: APICBASE_EN changed %#010RX64 -> %#010RX64\n", pVCpu->idCpu, pVCpu->nem.s.uKvmApicBase, uApicBase));1656 pRun->s.regs.sregs.apic_base = uApicBase;1657 pVCpu->nem.s.uKvmApicBase = uApicBase;1658 1659 if (fExtrn & CPUMCTX_EXTRN_APIC_TPR)1660 pRun->s.regs.sregs.cr8 = CPUMGetGuestCR8(pVCpu);1661 1662 #define NEM_LNX_EXPORT_SEG(a_KvmSeg, a_CtxSeg) do { \1663 (a_KvmSeg).base = (a_CtxSeg).u64Base; \1664 (a_KvmSeg).limit = (a_CtxSeg).u32Limit; \1665 (a_KvmSeg).selector = (a_CtxSeg).Sel; \1666 (a_KvmSeg).type = (a_CtxSeg).Attr.n.u4Type; \1667 (a_KvmSeg).s = (a_CtxSeg).Attr.n.u1DescType; \1668 (a_KvmSeg).dpl = (a_CtxSeg).Attr.n.u2Dpl; \1669 (a_KvmSeg).present = (a_CtxSeg).Attr.n.u1Present; \1670 (a_KvmSeg).avl = (a_CtxSeg).Attr.n.u1Available; \1671 (a_KvmSeg).l = (a_CtxSeg).Attr.n.u1Long; \1672 (a_KvmSeg).db = (a_CtxSeg).Attr.n.u1DefBig; \1673 (a_KvmSeg).g = (a_CtxSeg).Attr.n.u1Granularity; \1674 (a_KvmSeg).unusable = (a_CtxSeg).Attr.n.u1Unusable; \1675 (a_KvmSeg).padding = 0; \1676 } while (0)1677 1678 if (fExtrn & CPUMCTX_EXTRN_SREG_MASK)1679 {1680 if (fExtrn & CPUMCTX_EXTRN_ES)1681 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.es, pCtx->es);1682 if (fExtrn & CPUMCTX_EXTRN_CS)1683 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.cs, pCtx->cs);1684 if (fExtrn & CPUMCTX_EXTRN_SS)1685 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ss, pCtx->ss);1686 if (fExtrn & CPUMCTX_EXTRN_DS)1687 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ds, pCtx->ds);1688 if (fExtrn & CPUMCTX_EXTRN_FS)1689 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.fs, pCtx->fs);1690 if (fExtrn & CPUMCTX_EXTRN_GS)1691 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.gs, pCtx->gs);1692 }1693 if (fExtrn & CPUMCTX_EXTRN_TABLE_MASK)1694 {1695 if (fExtrn & CPUMCTX_EXTRN_GDTR)1696 {1697 pRun->s.regs.sregs.gdt.base = pCtx->gdtr.pGdt;1698 pRun->s.regs.sregs.gdt.limit = pCtx->gdtr.cbGdt;1699 pRun->s.regs.sregs.gdt.padding[0] = 0;1700 pRun->s.regs.sregs.gdt.padding[1] = 0;1701 pRun->s.regs.sregs.gdt.padding[2] = 0;1702 }1703 if (fExtrn & CPUMCTX_EXTRN_IDTR)1704 {1705 pRun->s.regs.sregs.idt.base = pCtx->idtr.pIdt;1706 pRun->s.regs.sregs.idt.limit = pCtx->idtr.cbIdt;1707 pRun->s.regs.sregs.idt.padding[0] = 0;1708 pRun->s.regs.sregs.idt.padding[1] = 0;1709 pRun->s.regs.sregs.idt.padding[2] = 0;1710 }1711 if (fExtrn & CPUMCTX_EXTRN_LDTR)1712 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ldt, pCtx->ldtr);1713 if (fExtrn & CPUMCTX_EXTRN_TR)1714 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.tr, pCtx->tr);1715 }1716 if (fExtrn & CPUMCTX_EXTRN_CR_MASK)1717 {1718 if (fExtrn & CPUMCTX_EXTRN_CR0)1719 pRun->s.regs.sregs.cr0 = pCtx->cr0;1720 if (fExtrn & CPUMCTX_EXTRN_CR2)1721 pRun->s.regs.sregs.cr2 = pCtx->cr2;1722 if (fExtrn & CPUMCTX_EXTRN_CR3)1723 pRun->s.regs.sregs.cr3 = pCtx->cr3;1724 if (fExtrn & CPUMCTX_EXTRN_CR4)1725 pRun->s.regs.sregs.cr4 = pCtx->cr4;1726 }1727 if (fExtrn & CPUMCTX_EXTRN_EFER)1728 pRun->s.regs.sregs.efer = pCtx->msrEFER;1729 1730 RT_ZERO(pRun->s.regs.sregs.interrupt_bitmap); /* this is an alternative interrupt injection interface */1731 1732 pRun->kvm_dirty_regs |= KVM_SYNC_X86_SREGS;1733 }1734 1735 /*1736 * Debug registers.1737 */1738 if (fExtrn & CPUMCTX_EXTRN_DR_MASK)1739 {1740 struct kvm_debugregs DbgRegs = {{0}};1741 1742 if ((fExtrn & CPUMCTX_EXTRN_DR_MASK) != CPUMCTX_EXTRN_DR_MASK)1743 {1744 /* Partial debug state, we must get DbgRegs first so we can merge: */1745 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_DEBUGREGS, &DbgRegs);1746 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);1747 }1748 1749 if (fExtrn & CPUMCTX_EXTRN_DR0_DR3)1750 {1751 DbgRegs.db[0] = pCtx->dr[0];1752 DbgRegs.db[1] = pCtx->dr[1];1753 DbgRegs.db[2] = pCtx->dr[2];1754 DbgRegs.db[3] = pCtx->dr[3];1755 }1756 if (fExtrn & CPUMCTX_EXTRN_DR6)1757 DbgRegs.dr6 = pCtx->dr[6];1758 if (fExtrn & CPUMCTX_EXTRN_DR7)1759 DbgRegs.dr7 = pCtx->dr[7];1760 1761 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_DEBUGREGS, &DbgRegs);1762 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);1763 }1764 1765 /*1766 * FPU, SSE, AVX, ++.1767 */1768 if (fExtrn & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx))1769 {1770 if (fExtrn & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE))1771 {1772 /** @todo could IEM just grab state partial control in some situations? */1773 Assert( (fExtrn & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE))1774 == (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE)); /* no partial states */1775 1776 AssertCompile(sizeof(pCtx->XState) >= sizeof(struct kvm_xsave));1777 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_XSAVE, &pCtx->XState);1778 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);1779 }1780 1781 if (fExtrn & CPUMCTX_EXTRN_XCRx)1782 {1783 struct kvm_xcrs Xcrs =1784 { /*.nr_xcrs = */ 2,1785 /*.flags = */ 0,1786 /*.xcrs= */ {1787 { /*.xcr =*/ 0, /*.reserved=*/ 0, /*.value=*/ pCtx->aXcr[0] },1788 { /*.xcr =*/ 1, /*.reserved=*/ 0, /*.value=*/ pCtx->aXcr[1] },1789 }1790 };1791 1792 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_XCRS, &Xcrs);1793 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);1794 }1795 }1796 1797 /*1798 * MSRs.1799 */1800 if (fExtrn & ( CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_SYSCALL_MSRS | CPUMCTX_EXTRN_SYSENTER_MSRS1801 | CPUMCTX_EXTRN_TSC_AUX | CPUMCTX_EXTRN_OTHER_MSRS))1802 {1803 union1804 {1805 struct kvm_msrs Core;1806 uint64_t padding[2 + sizeof(struct kvm_msr_entry) * 32];1807 } uBuf;1808 uint32_t iMsr = 0;1809 PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);1810 1811 #define ADD_MSR(a_Msr, a_uValue) do { \1812 Assert(iMsr < 32); \1813 uBuf.Core.entries[iMsr].index = (a_Msr); \1814 uBuf.Core.entries[iMsr].reserved = 0; \1815 uBuf.Core.entries[iMsr].data = (a_uValue); \1816 iMsr += 1; \1817 } while (0)1818 1819 if (fExtrn & CPUMCTX_EXTRN_KERNEL_GS_BASE)1820 ADD_MSR(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);1821 if (fExtrn & CPUMCTX_EXTRN_SYSCALL_MSRS)1822 {1823 ADD_MSR(MSR_K6_STAR, pCtx->msrSTAR);1824 ADD_MSR(MSR_K8_LSTAR, pCtx->msrLSTAR);1825 ADD_MSR(MSR_K8_CSTAR, pCtx->msrCSTAR);1826 ADD_MSR(MSR_K8_SF_MASK, pCtx->msrSFMASK);1827 }1828 if (fExtrn & CPUMCTX_EXTRN_SYSENTER_MSRS)1829 {1830 ADD_MSR(MSR_IA32_SYSENTER_CS, pCtx->SysEnter.cs);1831 ADD_MSR(MSR_IA32_SYSENTER_EIP, pCtx->SysEnter.eip);1832 ADD_MSR(MSR_IA32_SYSENTER_ESP, pCtx->SysEnter.esp);1833 }1834 if (fExtrn & CPUMCTX_EXTRN_TSC_AUX)1835 ADD_MSR(MSR_K8_TSC_AUX, pCtxMsrs->msr.TscAux);1836 if (fExtrn & CPUMCTX_EXTRN_OTHER_MSRS)1837 {1838 ADD_MSR(MSR_IA32_CR_PAT, pCtx->msrPAT);1839 /** @todo What do we _have_ to add here?1840 * We also have: Mttr*, MiscEnable, FeatureControl. */1841 }1842 1843 uBuf.Core.pad = 0;1844 uBuf.Core.nmsrs = iMsr;1845 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_MSRS, &uBuf);1846 AssertMsgReturn(rc == (int)iMsr,1847 ("rc=%d iMsr=%d (->%#x) errno=%d\n",1848 rc, iMsr, (uint32_t)rc < iMsr ? uBuf.Core.entries[rc].index : 0, errno),1849 VERR_NEM_IPE_3);1850 }1851 1852 /*1853 * Interruptibility state.1854 *1855 * Note! This I/O control function sets most fields passed in, so when1856 * raising an interrupt, NMI, SMI or exception, this must be done1857 * by the code doing the rasing or we'll overwrite it here.1858 */1859 if (fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI))1860 {1861 Assert( (fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI))1862 == (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI));1863 1864 struct kvm_vcpu_events KvmEvents = {0};1865 1866 KvmEvents.flags = KVM_VCPUEVENT_VALID_SHADOW;1867 if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx))1868 { /* probably likely */ }1869 else1870 KvmEvents.interrupt.shadow = (CPUMIsInInterruptShadowAfterSs() ? KVM_X86_SHADOW_INT_MOV_SS : 0)1871 | (CPUMIsInInterruptShadowAfterSti() ? KVM_X86_SHADOW_INT_STI : 0);1872 1873 /* No flag - this is updated unconditionally. */1874 KvmEvents.nmi.masked = CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx);1875 1876 if (TRPMHasTrap(pVCpu))1877 {1878 TRPMEVENT enmType = TRPM_32BIT_HACK;1879 uint8_t bTrapNo = 0;1880 TRPMQueryTrap(pVCpu, &bTrapNo, &enmType);1881 Log(("nemHCLnxExportState: Pending trap: bTrapNo=%#x enmType=%d\n", bTrapNo, enmType));1882 if ( enmType == TRPM_HARDWARE_INT1883 || enmType == TRPM_SOFTWARE_INT)1884 {1885 KvmEvents.interrupt.soft = enmType == TRPM_SOFTWARE_INT;1886 KvmEvents.interrupt.nr = bTrapNo;1887 KvmEvents.interrupt.injected = 1;1888 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExportPendingInterrupt);1889 TRPMResetTrap(pVCpu);1890 }1891 else1892 AssertFailed();1893 }1894 1895 int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_VCPU_EVENTS, &KvmEvents);1896 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_3);1897 }1898 1899 /*1900 * KVM now owns all the state.1901 */1902 pCtx->fExtrn = CPUMCTX_EXTRN_KEEPER_NEM | CPUMCTX_EXTRN_ALL;1903 1904 RT_NOREF(pVM);1905 return VINF_SUCCESS;1906 }1907 1908 1909 /**1910 * Query the CPU tick counter and optionally the TSC_AUX MSR value.1911 *1912 * @returns VBox status code.1913 * @param pVCpu The cross context CPU structure.1914 * @param pcTicks Where to return the CPU tick count.1915 * @param puAux Where to return the TSC_AUX register value.1916 */1917 VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t *pcTicks, uint32_t *puAux)1918 {1919 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);1920 // KVM_GET_CLOCK?1921 RT_NOREF(pVCpu, pcTicks, puAux);1922 return VINF_SUCCESS;1923 }1924 1925 1926 /**1927 * Resumes CPU clock (TSC) on all virtual CPUs.1928 *1929 * This is called by TM when the VM is started, restored, resumed or similar.1930 *1931 * @returns VBox status code.1932 * @param pVM The cross context VM structure.1933 * @param pVCpu The cross context CPU structure of the calling EMT.1934 * @param uPausedTscValue The TSC value at the time of pausing.1935 */1936 VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)1937 {1938 // KVM_SET_CLOCK?1939 RT_NOREF(pVM, pVCpu, uPausedTscValue);1940 return VINF_SUCCESS;1941 }1942 1943 1944 VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)1945 {1946 RT_NOREF(pVM);1947 return NEM_FEAT_F_NESTED_PAGING1948 | NEM_FEAT_F_FULL_GST_EXEC1949 | NEM_FEAT_F_XSAVE_XRSTOR;1950 }1951 1952 1953 1954 /*********************************************************************************************************************************1955 * Execution *1956 *********************************************************************************************************************************/1957 1958 1959 VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)1960 {1961 /*1962 * Only execute when the A20 gate is enabled as I cannot immediately1963 * spot any A20 support in KVM.1964 */1965 RT_NOREF(pVM);1966 Assert(VM_IS_NEM_ENABLED(pVM));1967 return PGMPhysIsA20Enabled(pVCpu);1968 }1969 1970 1971 bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)1972 {1973 NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);1974 return false;1975 }1976 1977 1978 void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)1979 {1980 int rc = RTThreadPoke(pVCpu->hThread);1981 LogFlow(("nemR3NativeNotifyFF: #%u -> %Rrc\n", pVCpu->idCpu, rc));1982 AssertRC(rc);1983 RT_NOREF(pVM, fFlags);1984 }1985 1986 1987 DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChanged(PVM pVM, bool fUseDebugLoop)1988 {1989 RT_NOREF(pVM, fUseDebugLoop);1990 return false;1991 }1992 1993 1994 DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu, bool fUseDebugLoop)1995 {1996 RT_NOREF(pVM, pVCpu, fUseDebugLoop);1997 return false;1998 }1999 2000 2001 /**2002 * Deals with pending interrupt FFs prior to executing guest code.2003 */2004 static VBOXSTRICTRC nemHCLnxHandleInterruptFF(PVM pVM, PVMCPU pVCpu, struct kvm_run *pRun)2005 {2006 RT_NOREF_PV(pVM);2007 2008 /*2009 * Do not doing anything if TRPM has something pending already as we can2010 * only inject one event per KVM_RUN call. This can only happend if we2011 * can directly from the loop in EM, so the inhibit bits must be internal.2012 */2013 if (!TRPMHasTrap(pVCpu))2014 { /* semi likely */ }2015 else2016 {2017 Assert(!(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI)));2018 Log8(("nemHCLnxHandleInterruptFF: TRPM has an pending event already\n"));2019 return VINF_SUCCESS;2020 }2021 2022 /*2023 * First update APIC. We ASSUME this won't need TPR/CR8.2024 */2025 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))2026 {2027 APICUpdatePendingInterrupts(pVCpu);2028 if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC2029 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))2030 return VINF_SUCCESS;2031 }2032 2033 /*2034 * We don't currently implement SMIs.2035 */2036 AssertReturn(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI), VERR_NEM_IPE_0);2037 2038 /*2039 * In KVM the CPUMCTX_EXTRN_INHIBIT_INT and CPUMCTX_EXTRN_INHIBIT_NMI states2040 * are tied together with interrupt and NMI delivery, so we must get and2041 * synchronize these all in one go and set both CPUMCTX_EXTRN_INHIBIT_XXX flags.2042 * If we don't we may lose the interrupt/NMI we marked pending here when the2043 * state is exported again before execution.2044 */2045 struct kvm_vcpu_events KvmEvents = {0};2046 int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_VCPU_EVENTS, &KvmEvents);2047 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);2048 2049 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_RIP))2050 pRun->s.regs.regs.rip = pVCpu->cpum.GstCtx.rip;2051 2052 KvmEvents.flags |= KVM_VCPUEVENT_VALID_SHADOW;2053 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_INT))2054 KvmEvents.interrupt.shadow = !CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx) ? 02055 : (CPUMIsInInterruptShadowAfterSs() ? KVM_X86_SHADOW_INT_MOV_SS : 0)2056 | (CPUMIsInInterruptShadowAfterSti() ? KVM_X86_SHADOW_INT_STI : 0);2057 else2058 CPUMUpdateInterruptShadowSsStiEx(&pVCpu->cpum.GstCtx,2059 RT_BOOL(KvmEvents.interrupt.shadow & KVM_X86_SHADOW_INT_MOV_SS),2060 RT_BOOL(KvmEvents.interrupt.shadow & KVM_X86_SHADOW_INT_MOV_STI),2061 pRun->s.regs.regs.rip);2062 2063 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_NMI))2064 KvmEvents.nmi.masked = CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx);2065 else2066 CPUMUpdateInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx, KvmEvents.nmi.masked != 0);2067 2068 /* KVM will own the INT + NMI inhibit state soon: */2069 pVCpu->cpum.GstCtx.fExtrn = (pVCpu->cpum.GstCtx.fExtrn & ~CPUMCTX_EXTRN_KEEPER_MASK)2070 | CPUMCTX_EXTRN_KEEPER_NEM | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI;2071 2072 /*2073 * NMI? Try deliver it first.2074 */2075 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI))2076 {2077 #if 02078 int rcLnx = ioctl(pVCpu->nem.s.fdVm, KVM_NMI, 0UL);2079 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);2080 #else2081 KvmEvents.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;2082 KvmEvents.nmi.pending = 1;2083 #endif2084 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);2085 Log8(("Queuing NMI on %u\n", pVCpu->idCpu));2086 }2087 2088 /*2089 * APIC or PIC interrupt?2090 */2091 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))2092 {2093 if (pRun->s.regs.regs.rflags & X86_EFL_IF)2094 {2095 if (KvmEvents.interrupt.shadow == 0)2096 {2097 /*2098 * If CR8 is in KVM, update the VBox copy so PDMGetInterrupt will2099 * work correctly.2100 */2101 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_APIC_TPR)2102 APICSetTpr(pVCpu, (uint8_t)pRun->cr8 << 4);2103 2104 uint8_t bInterrupt;2105 int rc = PDMGetInterrupt(pVCpu, &bInterrupt);2106 if (RT_SUCCESS(rc))2107 {2108 Assert(KvmEvents.interrupt.injected == false);2109 #if 02110 int rcLnx = ioctl(pVCpu->nem.s.fdVm, KVM_INTERRUPT, (unsigned long)bInterrupt);2111 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);2112 #else2113 KvmEvents.interrupt.nr = bInterrupt;2114 KvmEvents.interrupt.soft = false;2115 KvmEvents.interrupt.injected = true;2116 #endif2117 Log8(("Queuing interrupt %#x on %u: %04x:%08RX64 efl=%#x\n", bInterrupt, pVCpu->idCpu,2118 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eflags.u));2119 }2120 else if (rc == VERR_APIC_INTR_MASKED_BY_TPR) /** @todo this isn't extremely efficient if we get a lot of exits... */2121 Log8(("VERR_APIC_INTR_MASKED_BY_TPR\n")); /* We'll get a TRP exit - no interrupt window needed. */2122 else2123 Log8(("PDMGetInterrupt failed -> %Rrc\n", rc));2124 }2125 else2126 {2127 pRun->request_interrupt_window = 1;2128 Log8(("Interrupt window pending on %u (#2)\n", pVCpu->idCpu));2129 }2130 }2131 else2132 {2133 pRun->request_interrupt_window = 1;2134 Log8(("Interrupt window pending on %u (#1)\n", pVCpu->idCpu));2135 }2136 }2137 2138 /*2139 * Now, update the state.2140 */2141 /** @todo skip when possible... */2142 rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_VCPU_EVENTS, &KvmEvents);2143 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);2144 2145 return VINF_SUCCESS;2146 }2147 2148 2149 /**2150 * Handles KVM_EXIT_INTERNAL_ERROR.2151 */2152 static VBOXSTRICTRC nemR3LnxHandleInternalError(PVMCPU pVCpu, struct kvm_run *pRun)2153 {2154 Log(("NEM: KVM_EXIT_INTERNAL_ERROR! suberror=%#x (%d) ndata=%u data=%.*Rhxs\n", pRun->internal.suberror,2155 pRun->internal.suberror, pRun->internal.ndata, sizeof(pRun->internal.data), &pRun->internal.data[0]));2156 2157 /*2158 * Deal with each suberror, returning if we don't want IEM to handle it.2159 */2160 switch (pRun->internal.suberror)2161 {2162 case KVM_INTERNAL_ERROR_EMULATION:2163 {2164 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTERNAL_ERROR_EMULATION),2165 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());2166 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInternalErrorEmulation);2167 break;2168 }2169 2170 case KVM_INTERNAL_ERROR_SIMUL_EX:2171 case KVM_INTERNAL_ERROR_DELIVERY_EV:2172 case KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON:2173 default:2174 {2175 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTERNAL_ERROR_FATAL),2176 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());2177 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInternalErrorFatal);2178 const char *pszName;2179 switch (pRun->internal.suberror)2180 {2181 case KVM_INTERNAL_ERROR_EMULATION: pszName = "KVM_INTERNAL_ERROR_EMULATION"; break;2182 case KVM_INTERNAL_ERROR_SIMUL_EX: pszName = "KVM_INTERNAL_ERROR_SIMUL_EX"; break;2183 case KVM_INTERNAL_ERROR_DELIVERY_EV: pszName = "KVM_INTERNAL_ERROR_DELIVERY_EV"; break;2184 case KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON: pszName = "KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON"; break;2185 default: pszName = "unknown"; break;2186 }2187 LogRel(("NEM: KVM_EXIT_INTERNAL_ERROR! suberror=%#x (%s) ndata=%u data=%.*Rhxs\n", pRun->internal.suberror, pszName,2188 pRun->internal.ndata, sizeof(pRun->internal.data), &pRun->internal.data[0]));2189 return VERR_NEM_IPE_0;2190 }2191 }2192 2193 /*2194 * Execute instruction in IEM and try get on with it.2195 */2196 Log2(("nemR3LnxHandleInternalError: Executing instruction at %04x:%08RX64 in IEM\n",2197 pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip));2198 VBOXSTRICTRC rcStrict = nemHCLnxImportState(pVCpu,2199 IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_INHIBIT_INT2200 | CPUMCTX_EXTRN_INHIBIT_NMI,2201 &pVCpu->cpum.GstCtx, pRun);2202 if (RT_SUCCESS(rcStrict))2203 rcStrict = IEMExecOne(pVCpu);2204 return rcStrict;2205 }2206 2207 2208 /**2209 * Handles KVM_EXIT_IO.2210 */2211 static VBOXSTRICTRC nemHCLnxHandleExitIo(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun)2212 {2213 /*2214 * Input validation.2215 */2216 Assert(pRun->io.count > 0);2217 Assert(pRun->io.size == 1 || pRun->io.size == 2 || pRun->io.size == 4);2218 Assert(pRun->io.direction == KVM_EXIT_IO_IN || pRun->io.direction == KVM_EXIT_IO_OUT);2219 Assert(pRun->io.data_offset < pVM->nem.s.cbVCpuMmap);2220 Assert(pRun->io.data_offset + pRun->io.size * pRun->io.count <= pVM->nem.s.cbVCpuMmap);2221 2222 /*2223 * We cannot easily act on the exit history here, because the I/O port2224 * exit is stateful and the instruction will be completed in the next2225 * KVM_RUN call. There seems no way to avoid this.2226 */2227 EMHistoryAddExit(pVCpu,2228 pRun->io.count == 12229 ? ( pRun->io.direction == KVM_EXIT_IO_IN2230 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ)2231 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE))2232 : ( pRun->io.direction == KVM_EXIT_IO_IN2233 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)2234 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE)),2235 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());2236 2237 /*2238 * Do the requested job.2239 */2240 VBOXSTRICTRC rcStrict;2241 RTPTRUNION uPtrData;2242 uPtrData.pu8 = (uint8_t *)pRun + pRun->io.data_offset;2243 if (pRun->io.count == 1)2244 {2245 if (pRun->io.direction == KVM_EXIT_IO_IN)2246 {2247 uint32_t uValue = 0;2248 rcStrict = IOMIOPortRead(pVM, pVCpu, pRun->io.port, &uValue, pRun->io.size);2249 Log4(("IOExit/%u: %04x:%08RX64: IN %#x LB %u -> %#x, rcStrict=%Rrc\n",2250 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,2251 pRun->io.port, pRun->io.size, uValue, VBOXSTRICTRC_VAL(rcStrict) ));2252 if (IOM_SUCCESS(rcStrict))2253 {2254 if (pRun->io.size == 4)2255 *uPtrData.pu32 = uValue;2256 else if (pRun->io.size == 2)2257 *uPtrData.pu16 = (uint16_t)uValue;2258 else2259 *uPtrData.pu8 = (uint8_t)uValue;2260 }2261 }2262 else2263 {2264 uint32_t const uValue = pRun->io.size == 4 ? *uPtrData.pu322265 : pRun->io.size == 2 ? *uPtrData.pu162266 : *uPtrData.pu8;2267 rcStrict = IOMIOPortWrite(pVM, pVCpu, pRun->io.port, uValue, pRun->io.size);2268 Log4(("IOExit/%u: %04x:%08RX64: OUT %#x, %#x LB %u rcStrict=%Rrc\n",2269 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,2270 pRun->io.port, uValue, pRun->io.size, VBOXSTRICTRC_VAL(rcStrict) ));2271 }2272 }2273 else2274 {2275 uint32_t cTransfers = pRun->io.count;2276 if (pRun->io.direction == KVM_EXIT_IO_IN)2277 {2278 rcStrict = IOMIOPortReadString(pVM, pVCpu, pRun->io.port, uPtrData.pv, &cTransfers, pRun->io.size);2279 Log4(("IOExit/%u: %04x:%08RX64: REP INS %#x LB %u * %#x times -> rcStrict=%Rrc cTransfers=%d\n",2280 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,2281 pRun->io.port, pRun->io.size, pRun->io.count, VBOXSTRICTRC_VAL(rcStrict), cTransfers ));2282 }2283 else2284 {2285 rcStrict = IOMIOPortWriteString(pVM, pVCpu, pRun->io.port, uPtrData.pv, &cTransfers, pRun->io.size);2286 Log4(("IOExit/%u: %04x:%08RX64: REP OUTS %#x LB %u * %#x times -> rcStrict=%Rrc cTransfers=%d\n",2287 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,2288 pRun->io.port, pRun->io.size, pRun->io.count, VBOXSTRICTRC_VAL(rcStrict), cTransfers ));2289 }2290 Assert(cTransfers == 0);2291 }2292 return rcStrict;2293 }2294 2295 2296 /**2297 * Handles KVM_EXIT_MMIO.2298 */2299 static VBOXSTRICTRC nemHCLnxHandleExitMmio(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun)2300 {2301 /*2302 * Input validation.2303 */2304 Assert(pRun->mmio.len <= sizeof(pRun->mmio.data));2305 Assert(pRun->mmio.is_write <= 1);2306 2307 /*2308 * We cannot easily act on the exit history here, because the MMIO port2309 * exit is stateful and the instruction will be completed in the next2310 * KVM_RUN call. There seems no way to circumvent this.2311 */2312 EMHistoryAddExit(pVCpu,2313 pRun->mmio.is_write2314 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)2315 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),2316 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());2317 2318 /*2319 * Do the requested job.2320 */2321 VBOXSTRICTRC rcStrict;2322 if (pRun->mmio.is_write)2323 {2324 rcStrict = PGMPhysWrite(pVM, pRun->mmio.phys_addr, pRun->mmio.data, pRun->mmio.len, PGMACCESSORIGIN_HM);2325 Log4(("MmioExit/%u: %04x:%08RX64: WRITE %#x LB %u, %.*Rhxs -> rcStrict=%Rrc\n",2326 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,2327 pRun->mmio.phys_addr, pRun->mmio.len, pRun->mmio.len, pRun->mmio.data, VBOXSTRICTRC_VAL(rcStrict) ));2328 }2329 else2330 {2331 rcStrict = PGMPhysRead(pVM, pRun->mmio.phys_addr, pRun->mmio.data, pRun->mmio.len, PGMACCESSORIGIN_HM);2332 Log4(("MmioExit/%u: %04x:%08RX64: READ %#x LB %u -> %.*Rhxs rcStrict=%Rrc\n",2333 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,2334 pRun->mmio.phys_addr, pRun->mmio.len, pRun->mmio.len, pRun->mmio.data, VBOXSTRICTRC_VAL(rcStrict) ));2335 }2336 return rcStrict;2337 }2338 2339 2340 /**2341 * Handles KVM_EXIT_RDMSR2342 */2343 static VBOXSTRICTRC nemHCLnxHandleExitRdMsr(PVMCPUCC pVCpu, struct kvm_run *pRun)2344 {2345 /*2346 * Input validation.2347 */2348 Assert( pRun->msr.reason == KVM_MSR_EXIT_REASON_INVAL2349 || pRun->msr.reason == KVM_MSR_EXIT_REASON_UNKNOWN2350 || pRun->msr.reason == KVM_MSR_EXIT_REASON_FILTER);2351 2352 /*2353 * We cannot easily act on the exit history here, because the MSR exit is2354 * stateful and the instruction will be completed in the next KVM_RUN call.2355 * There seems no way to circumvent this.2356 */2357 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ),2358 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());2359 2360 /*2361 * Do the requested job.2362 */2363 uint64_t uValue = 0;2364 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pRun->msr.index, &uValue);2365 pRun->msr.data = uValue;2366 if (rcStrict != VERR_CPUM_RAISE_GP_0)2367 {2368 Log3(("MsrRead/%u: %04x:%08RX64: msr=%#010x (reason=%#x) -> %#RX64 rcStrict=%Rrc\n", pVCpu->idCpu,2369 pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->msr.index, pRun->msr.reason, uValue, VBOXSTRICTRC_VAL(rcStrict) ));2370 pRun->msr.error = 0;2371 }2372 else2373 {2374 Log3(("MsrRead/%u: %04x:%08RX64: msr=%#010x (reason%#x)-> %#RX64 rcStrict=#GP!\n", pVCpu->idCpu,2375 pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->msr.index, pRun->msr.reason, uValue));2376 pRun->msr.error = 1;2377 rcStrict = VINF_SUCCESS;2378 }2379 return rcStrict;2380 }2381 2382 2383 /**2384 * Handles KVM_EXIT_WRMSR2385 */2386 static VBOXSTRICTRC nemHCLnxHandleExitWrMsr(PVMCPUCC pVCpu, struct kvm_run *pRun)2387 {2388 /*2389 * Input validation.2390 */2391 Assert( pRun->msr.reason == KVM_MSR_EXIT_REASON_INVAL2392 || pRun->msr.reason == KVM_MSR_EXIT_REASON_UNKNOWN2393 || pRun->msr.reason == KVM_MSR_EXIT_REASON_FILTER);2394 2395 /*2396 * We cannot easily act on the exit history here, because the MSR exit is2397 * stateful and the instruction will be completed in the next KVM_RUN call.2398 * There seems no way to circumvent this.2399 */2400 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),2401 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());2402 2403 /*2404 * Do the requested job.2405 */2406 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pRun->msr.index, pRun->msr.data);2407 if (rcStrict != VERR_CPUM_RAISE_GP_0)2408 {2409 Log3(("MsrWrite/%u: %04x:%08RX64: msr=%#010x := %#RX64 (reason=%#x) -> rcStrict=%Rrc\n", pVCpu->idCpu,2410 pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->msr.index, pRun->msr.data, pRun->msr.reason, VBOXSTRICTRC_VAL(rcStrict) ));2411 pRun->msr.error = 0;2412 }2413 else2414 {2415 Log3(("MsrWrite/%u: %04x:%08RX64: msr=%#010x := %#RX64 (reason%#x)-> rcStrict=#GP!\n", pVCpu->idCpu,2416 pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->msr.index, pRun->msr.data, pRun->msr.reason));2417 pRun->msr.error = 1;2418 rcStrict = VINF_SUCCESS;2419 }2420 return rcStrict;2421 }2422 2423 2424 2425 static VBOXSTRICTRC nemHCLnxHandleExit(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun, bool *pfStatefulExit)2426 {2427 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitTotal);2428 switch (pRun->exit_reason)2429 {2430 case KVM_EXIT_EXCEPTION:2431 AssertFailed();2432 break;2433 2434 case KVM_EXIT_IO:2435 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIo);2436 *pfStatefulExit = true;2437 return nemHCLnxHandleExitIo(pVM, pVCpu, pRun);2438 2439 case KVM_EXIT_MMIO:2440 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMmio);2441 *pfStatefulExit = true;2442 return nemHCLnxHandleExitMmio(pVM, pVCpu, pRun);2443 2444 case KVM_EXIT_IRQ_WINDOW_OPEN:2445 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTTERRUPT_WINDOW),2446 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());2447 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIrqWindowOpen);2448 Log5(("IrqWinOpen/%u: %d\n", pVCpu->idCpu, pRun->request_interrupt_window));2449 pRun->request_interrupt_window = 0;2450 return VINF_SUCCESS;2451 2452 case KVM_EXIT_SET_TPR:2453 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitSetTpr);2454 AssertFailed();2455 break;2456 2457 case KVM_EXIT_TPR_ACCESS:2458 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitTprAccess);2459 AssertFailed();2460 break;2461 2462 case KVM_EXIT_X86_RDMSR:2463 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitRdMsr);2464 *pfStatefulExit = true;2465 return nemHCLnxHandleExitRdMsr(pVCpu, pRun);2466 2467 case KVM_EXIT_X86_WRMSR:2468 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitWrMsr);2469 *pfStatefulExit = true;2470 return nemHCLnxHandleExitWrMsr(pVCpu, pRun);2471 2472 case KVM_EXIT_HLT:2473 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_HALT),2474 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());2475 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHalt);2476 Log5(("Halt/%u\n", pVCpu->idCpu));2477 return VINF_EM_HALT;2478 2479 case KVM_EXIT_INTR: /* EINTR */2480 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTERRUPTED),2481 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());2482 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIntr);2483 Log5(("Intr/%u\n", pVCpu->idCpu));2484 return VINF_SUCCESS;2485 2486 case KVM_EXIT_HYPERCALL:2487 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHypercall);2488 AssertFailed();2489 break;2490 2491 case KVM_EXIT_DEBUG:2492 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitDebug);2493 AssertFailed();2494 break;2495 2496 case KVM_EXIT_SYSTEM_EVENT:2497 AssertFailed();2498 break;2499 case KVM_EXIT_IOAPIC_EOI:2500 AssertFailed();2501 break;2502 case KVM_EXIT_HYPERV:2503 AssertFailed();2504 break;2505 2506 case KVM_EXIT_DIRTY_RING_FULL:2507 AssertFailed();2508 break;2509 case KVM_EXIT_AP_RESET_HOLD:2510 AssertFailed();2511 break;2512 case KVM_EXIT_X86_BUS_LOCK:2513 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitBusLock);2514 AssertFailed();2515 break;2516 2517 2518 case KVM_EXIT_SHUTDOWN:2519 AssertFailed();2520 break;2521 2522 case KVM_EXIT_FAIL_ENTRY:2523 LogRel(("NEM: KVM_EXIT_FAIL_ENTRY! hardware_entry_failure_reason=%#x cpu=%#x\n",2524 pRun->fail_entry.hardware_entry_failure_reason, pRun->fail_entry.cpu));2525 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_FAILED_ENTRY),2526 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());2527 return VERR_NEM_IPE_1;2528 2529 case KVM_EXIT_INTERNAL_ERROR:2530 /* we're counting sub-reasons inside the function. */2531 return nemR3LnxHandleInternalError(pVCpu, pRun);2532 2533 /*2534 * Foreign and unknowns.2535 */2536 case KVM_EXIT_NMI:2537 AssertLogRelMsgFailedReturn(("KVM_EXIT_NMI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2538 case KVM_EXIT_EPR:2539 AssertLogRelMsgFailedReturn(("KVM_EXIT_EPR on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2540 case KVM_EXIT_WATCHDOG:2541 AssertLogRelMsgFailedReturn(("KVM_EXIT_WATCHDOG on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2542 case KVM_EXIT_ARM_NISV:2543 AssertLogRelMsgFailedReturn(("KVM_EXIT_ARM_NISV on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2544 case KVM_EXIT_S390_STSI:2545 AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_STSI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2546 case KVM_EXIT_S390_TSCH:2547 AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_TSCH on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2548 case KVM_EXIT_OSI:2549 AssertLogRelMsgFailedReturn(("KVM_EXIT_OSI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2550 case KVM_EXIT_PAPR_HCALL:2551 AssertLogRelMsgFailedReturn(("KVM_EXIT_PAPR_HCALL on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2552 case KVM_EXIT_S390_UCONTROL:2553 AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_UCONTROL on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2554 case KVM_EXIT_DCR:2555 AssertLogRelMsgFailedReturn(("KVM_EXIT_DCR on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2556 case KVM_EXIT_S390_SIEIC:2557 AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_SIEIC on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2558 case KVM_EXIT_S390_RESET:2559 AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_RESET on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2560 case KVM_EXIT_UNKNOWN:2561 AssertLogRelMsgFailedReturn(("KVM_EXIT_UNKNOWN on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2562 case KVM_EXIT_XEN:2563 AssertLogRelMsgFailedReturn(("KVM_EXIT_XEN on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2564 default:2565 AssertLogRelMsgFailedReturn(("Unknown exit reason %u on VCpu #%u at %04x:%RX64!\n", pRun->exit_reason, pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);2566 }2567 2568 RT_NOREF(pVM, pVCpu, pRun);2569 return VERR_NOT_IMPLEMENTED;2570 }2571 2572 2573 VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)2574 {2575 /*2576 * Try switch to NEM runloop state.2577 */2578 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))2579 { /* likely */ }2580 else2581 {2582 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);2583 LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));2584 return VINF_SUCCESS;2585 }2586 2587 /*2588 * The run loop.2589 */2590 struct kvm_run * const pRun = pVCpu->nem.s.pRun;2591 const bool fSingleStepping = DBGFIsStepping(pVCpu);2592 VBOXSTRICTRC rcStrict = VINF_SUCCESS;2593 bool fStatefulExit = false; /* For MMIO and IO exits. */2594 for (unsigned iLoop = 0;; iLoop++)2595 {2596 /*2597 * Pending interrupts or such? Need to check and deal with this prior2598 * to the state syncing.2599 */2600 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC2601 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))2602 {2603 /* Try inject interrupt. */2604 rcStrict = nemHCLnxHandleInterruptFF(pVM, pVCpu, pRun);2605 if (rcStrict == VINF_SUCCESS)2606 { /* likely */ }2607 else2608 {2609 LogFlow(("NEM/%u: breaking: nemHCLnxHandleInterruptFF -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));2610 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);2611 break;2612 }2613 }2614 2615 /*2616 * Do not execute in KVM if the A20 isn't enabled.2617 */2618 if (PGMPhysIsA20Enabled(pVCpu))2619 { /* likely */ }2620 else2621 {2622 rcStrict = VINF_EM_RESCHEDULE_REM;2623 LogFlow(("NEM/%u: breaking: A20 disabled\n", pVCpu->idCpu));2624 break;2625 }2626 2627 /*2628 * Ensure KVM has the whole state.2629 */2630 if ((pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL) != CPUMCTX_EXTRN_ALL)2631 {2632 int rc2 = nemHCLnxExportState(pVM, pVCpu, &pVCpu->cpum.GstCtx, pRun);2633 AssertRCReturn(rc2, rc2);2634 }2635 2636 /*2637 * Poll timers and run for a bit.2638 *2639 * With the VID approach (ring-0 or ring-3) we can specify a timeout here,2640 * so we take the time of the next timer event and uses that as a deadline.2641 * The rounding heuristics are "tuned" so that rhel5 (1K timer) will boot fine.2642 */2643 /** @todo See if we cannot optimize this TMTimerPollGIP by only redoing2644 * the whole polling job when timers have changed... */2645 uint64_t offDeltaIgnored;2646 uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);2647 if ( !VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)2648 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))2649 {2650 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_WAIT, VMCPUSTATE_STARTED_EXEC_NEM))2651 {2652 LogFlow(("NEM/%u: Entry @ %04x:%08RX64 IF=%d EFL=%#RX64 SS:RSP=%04x:%08RX64 cr0=%RX64\n",2653 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,2654 !!(pRun->s.regs.regs.rflags & X86_EFL_IF), pRun->s.regs.regs.rflags,2655 pRun->s.regs.sregs.ss.selector, pRun->s.regs.regs.rsp, pRun->s.regs.sregs.cr0));2656 TMNotifyStartOfExecution(pVM, pVCpu);2657 2658 int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_RUN, 0UL);2659 2660 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT);2661 TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());2662 2663 #ifdef LOG_ENABLED2664 if (LogIsFlowEnabled())2665 {2666 struct kvm_mp_state MpState = {UINT32_MAX};2667 ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_MP_STATE, &MpState);2668 LogFlow(("NEM/%u: Exit @ %04x:%08RX64 IF=%d EFL=%#RX64 CR8=%#x Reason=%#x IrqReady=%d Flags=%#x %#lx\n", pVCpu->idCpu,2669 pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->if_flag,2670 pRun->s.regs.regs.rflags, pRun->s.regs.sregs.cr8, pRun->exit_reason,2671 pRun->ready_for_interrupt_injection, pRun->flags, MpState.mp_state));2672 }2673 #endif2674 fStatefulExit = false;2675 if (RT_LIKELY(rcLnx == 0 || errno == EINTR))2676 {2677 /*2678 * Deal with the exit.2679 */2680 rcStrict = nemHCLnxHandleExit(pVM, pVCpu, pRun, &fStatefulExit);2681 if (rcStrict == VINF_SUCCESS)2682 { /* hopefully likely */ }2683 else2684 {2685 LogFlow(("NEM/%u: breaking: nemHCLnxHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));2686 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);2687 break;2688 }2689 }2690 else2691 {2692 int rc2 = RTErrConvertFromErrno(errno);2693 AssertLogRelMsgFailedReturn(("KVM_RUN failed: rcLnx=%d errno=%u rc=%Rrc\n", rcLnx, errno, rc2), rc2);2694 }2695 2696 /*2697 * If no relevant FFs are pending, loop.2698 */2699 if ( !VM_FF_IS_ANY_SET( pVM, !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)2700 && !VMCPU_FF_IS_ANY_SET(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )2701 { /* likely */ }2702 else2703 {2704 2705 /** @todo Try handle pending flags, not just return to EM loops. Take care2706 * not to set important RCs here unless we've handled an exit. */2707 LogFlow(("NEM/%u: breaking: pending FF (%#x / %#RX64)\n",2708 pVCpu->idCpu, pVM->fGlobalForcedActions, (uint64_t)pVCpu->fLocalForcedActions));2709 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPost);2710 break;2711 }2712 }2713 else2714 {2715 LogFlow(("NEM/%u: breaking: canceled %d (pre exec)\n", pVCpu->idCpu, VMCPU_GET_STATE(pVCpu) ));2716 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnCancel);2717 break;2718 }2719 }2720 else2721 {2722 LogFlow(("NEM/%u: breaking: pending FF (pre exec)\n", pVCpu->idCpu));2723 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPre);2724 break;2725 }2726 } /* the run loop */2727 2728 2729 /*2730 * If the last exit was stateful, commit the state we provided before2731 * returning to the EM loop so we have a consistent state and can safely2732 * be rescheduled and whatnot. This may require us to make multiple runs2733 * for larger MMIO and I/O operations. Sigh^3.2734 *2735 * Note! There is no 'ing way to reset the kernel side completion callback2736 * for these stateful i/o exits. Very annoying interface.2737 */2738 /** @todo check how this works with string I/O and string MMIO. */2739 if (fStatefulExit && RT_SUCCESS(rcStrict))2740 {2741 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn);2742 uint32_t const uOrgExit = pRun->exit_reason;2743 for (uint32_t i = 0; ; i++)2744 {2745 pRun->immediate_exit = 1;2746 int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_RUN, 0UL);2747 Log(("NEM/%u: Flushed stateful exit -> %d/%d exit_reason=%d\n", pVCpu->idCpu, rcLnx, errno, pRun->exit_reason));2748 if (rcLnx == -1 && errno == EINTR)2749 {2750 switch (i)2751 {2752 case 0: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn1Loop); break;2753 case 1: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn2Loops); break;2754 case 2: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn3Loops); break;2755 default: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn4PlusLoops); break;2756 }2757 break;2758 }2759 AssertLogRelMsgBreakStmt(rcLnx == 0 && pRun->exit_reason == uOrgExit,2760 ("rcLnx=%d errno=%d exit_reason=%d uOrgExit=%d\n", rcLnx, errno, pRun->exit_reason, uOrgExit),2761 rcStrict = VERR_NEM_IPE_6);2762 VBOXSTRICTRC rcStrict2 = nemHCLnxHandleExit(pVM, pVCpu, pRun, &fStatefulExit);2763 if (rcStrict2 == VINF_SUCCESS || rcStrict2 == rcStrict)2764 { /* likely */ }2765 else if (RT_FAILURE(rcStrict2))2766 {2767 rcStrict = rcStrict2;2768 break;2769 }2770 else2771 {2772 AssertLogRelMsgBreakStmt(rcStrict == VINF_SUCCESS,2773 ("rcStrict=%Rrc rcStrict2=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict), VBOXSTRICTRC_VAL(rcStrict2)),2774 rcStrict = VERR_NEM_IPE_7);2775 rcStrict = rcStrict2;2776 }2777 }2778 pRun->immediate_exit = 0;2779 }2780 2781 /*2782 * If the CPU is running, make sure to stop it before we try sync back the2783 * state and return to EM. We don't sync back the whole state if we can help it.2784 */2785 if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))2786 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);2787 2788 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL)2789 {2790 /* Try anticipate what we might need. */2791 uint64_t fImport = CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI /* Required for processing APIC,PIC,NMI & SMI FFs. */2792 | IEM_CPUMCTX_EXTRN_MUST_MASK /*?*/;2793 if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)2794 || RT_FAILURE(rcStrict))2795 fImport = CPUMCTX_EXTRN_ALL;2796 # ifdef IN_RING0 /* Ring-3 I/O port access optimizations: */2797 else if ( rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE2798 || rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)2799 fImport = CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RFLAGS;2800 else if (rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)2801 fImport = CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RFLAGS;2802 # endif2803 else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_INTERRUPT_APIC2804 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))2805 fImport |= IEM_CPUMCTX_EXTRN_XCPT_MASK;2806 2807 if (pVCpu->cpum.GstCtx.fExtrn & fImport)2808 {2809 int rc2 = nemHCLnxImportState(pVCpu, fImport, &pVCpu->cpum.GstCtx, pRun);2810 if (RT_SUCCESS(rc2))2811 pVCpu->cpum.GstCtx.fExtrn &= ~fImport;2812 else if (RT_SUCCESS(rcStrict))2813 rcStrict = rc2;2814 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))2815 pVCpu->cpum.GstCtx.fExtrn = 0;2816 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);2817 }2818 else2819 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);2820 }2821 else2822 {2823 pVCpu->cpum.GstCtx.fExtrn = 0;2824 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);2825 }2826 2827 LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 => %Rrc\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,2828 pVCpu->cpum.GstCtx.rflags.u, VBOXSTRICTRC_VAL(rcStrict) ));2829 return rcStrict;2830 }2831 2832 2833 /** @page pg_nem_linux NEM/linux - Native Execution Manager, Linux.2834 *2835 * This is using KVM.2836 *2837 */2838
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