VirtualBox

Changeset 104990 in vbox for trunk/src/VBox/VMM


Ignore:
Timestamp:
Jun 20, 2024 11:13:34 PM (10 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
163604
Message:

VMM/IEM: Added IEMTlbInvalidateAllGlobal and made the IEMTlbInvalidateAll function handle non-global flushes. More TLB stats. bugref:10687

Location:
trunk/src/VBox/VMM
Files:
8 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/IEMAll-armv8.cpp

    r103290 r104990  
    115115
    116116
     117VMM_INT_DECL(void) IEMTlbInvalidateAllGlobal(PVMCPUCC pVCpu)
     118{
     119    RT_NOREF(pVCpu);
     120}
     121
     122
    117123VMM_INT_DECL(void) IEMTlbInvalidateAllPhysicalAllCpus(PVMCC pVM, VMCPUID idCpuCaller, IEMTLBPHYSFLUSHREASON enmReason)
    118124{

  • trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

    r104989 r104990  
    607607
    608608/**
    609  * Invalidates the IEM TLBs.
    610  *
    611  * This is called internally as well as by PGM when moving GC mappings.
    612  *
    613  * @param   pVCpu       The cross context virtual CPU structure of the calling
    614  *                      thread.
    615  */
    616 VMM_INT_DECL(void) IEMTlbInvalidateAll(PVMCPUCC pVCpu)
     609 * Worker for IEMTlbInvalidateAll and IEMTlbInvalidateAllGlobal.
     610 */
     611template<bool a_fGlobal>
     612DECL_FORCE_INLINE(void) iemTlbInvalidateAll(PVMCPUCC pVCpu)
    617613{
    618614#if defined(IEM_WITH_CODE_TLB) || defined(IEM_WITH_DATA_TLB)
    … …  
    620616# ifdef IEM_WITH_CODE_TLB
    621617    pVCpu->iem.s.cbInstrBufTotal = 0;
     618    if (!a_fGlobal)
     619        pVCpu->iem.s.CodeTlb.cTlsFlushes++;
     620    else
     621        pVCpu->iem.s.CodeTlb.cTlsGlobalFlushes++;
    622622    pVCpu->iem.s.CodeTlb.uTlbRevision += IEMTLB_REVISION_INCR;
    623     if (pVCpu->iem.s.CodeTlb.uTlbRevision != 0)
     623    if (RT_LIKELY(pVCpu->iem.s.CodeTlb.uTlbRevision != 0))
    624624    { /* very likely */ }
    625625    else
    626626    {
    627627        pVCpu->iem.s.CodeTlb.uTlbRevision = IEMTLB_REVISION_INCR;
     628        pVCpu->iem.s.CodeTlb.cTlbRevisionRollovers++;
    628629        unsigned i = RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries);
    629630        while (i-- > 0)
    … …  
    633634
    634635# ifdef IEM_WITH_DATA_TLB
     636    if (!a_fGlobal)
     637        pVCpu->iem.s.DataTlb.cTlsFlushes++;
     638    else
     639        pVCpu->iem.s.DataTlb.cTlsGlobalFlushes++;
    635640    pVCpu->iem.s.DataTlb.uTlbRevision += IEMTLB_REVISION_INCR;
    636641    if (pVCpu->iem.s.DataTlb.uTlbRevision != 0)
    … …  
    639644    {
    640645        pVCpu->iem.s.DataTlb.uTlbRevision = IEMTLB_REVISION_INCR;
     646        pVCpu->iem.s.DataTlb.cTlbRevisionRollovers++;
    641647        unsigned i = RT_ELEMENTS(pVCpu->iem.s.DataTlb.aEntries);
    642648        while (i-- > 0)
    … …  
    647653    RT_NOREF(pVCpu);
    648654#endif
     655}
     656
     657
     658/**
     659 * Invalidates non-global the IEM TLB entries.
     660 *
     661 * This is called internally as well as by PGM when moving GC mappings.
     662 *
     663 * @param   pVCpu       The cross context virtual CPU structure of the calling
     664 *                      thread.
     665 */
     666VMM_INT_DECL(void) IEMTlbInvalidateAll(PVMCPUCC pVCpu)
     667{
     668    iemTlbInvalidateAll<false>(pVCpu);
     669}
     670
     671
     672/**
     673 * Invalidates all the IEM TLB entries.
     674 *
     675 * This is called internally as well as by PGM when moving GC mappings.
     676 *
     677 * @param   pVCpu       The cross context virtual CPU structure of the calling
     678 *                      thread.
     679 */
     680VMM_INT_DECL(void) IEMTlbInvalidateAllGlobal(PVMCPUCC pVCpu)
     681{
     682    iemTlbInvalidateAll<true>(pVCpu);
    649683}
    650684
    … …  
    710744                                                               | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PHYS_REV);
    711745    }
     746    pVCpu->iem.s.CodeTlb.cTlbPhysRevRollovers++;
     747    pVCpu->iem.s.CodeTlb.cTlbPhysRevFlushes++;
    712748# endif
    713749# ifdef IEM_WITH_DATA_TLB
    … …  
    719755                                                               | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PHYS_REV);
    720756    }
     757    pVCpu->iem.s.DataTlb.cTlbPhysRevRollovers++;
     758    pVCpu->iem.s.DataTlb.cTlbPhysRevFlushes++;
    721759# endif
    722760
    … …  
    747785    {
    748786        pVCpu->iem.s.CodeTlb.uTlbPhysRev = uTlbPhysRev;
     787        pVCpu->iem.s.CodeTlb.cTlbPhysRevFlushes++;
    749788        pVCpu->iem.s.DataTlb.uTlbPhysRev = uTlbPhysRev;
     789        pVCpu->iem.s.DataTlb.cTlbPhysRevFlushes++;
    750790    }
    751791    else
    … …  
    795835            continue;
    796836        }
    797         ASMAtomicCmpXchgU64(&pVCpu->iem.s.CodeTlb.uTlbPhysRev, uTlbPhysRevNew, uTlbPhysRevPrev);
    798         ASMAtomicCmpXchgU64(&pVCpu->iem.s.DataTlb.uTlbPhysRev, uTlbPhysRevNew, uTlbPhysRevPrev);
     837        if (ASMAtomicCmpXchgU64(&pVCpu->iem.s.CodeTlb.uTlbPhysRev, uTlbPhysRevNew, uTlbPhysRevPrev))
     838            pVCpu->iem.s.CodeTlb.cTlbPhysRevFlushes++;
     839
     840        if (ASMAtomicCmpXchgU64(&pVCpu->iem.s.DataTlb.uTlbPhysRev, uTlbPhysRevNew, uTlbPhysRevPrev))
     841            pVCpu->iem.s.DataTlb.cTlbPhysRevFlushes++;
    799842    }
    800843    VMCC_FOR_EACH_VMCPU_END(pVM);

  • trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp

    r100072 r104990  
    138138
    139139    /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
    140     IEMTlbInvalidateAll(pVCpu);
     140    IEMTlbInvalidateAllGlobal(pVCpu);
    141141
    142142    /* Inform CPUM (recompiler), can later be removed. */

  • trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp

    r104932 r104990  
    12931293
    12941294    /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
    1295     IEMTlbInvalidateAll(pVCpu);
     1295    IEMTlbInvalidateAllGlobal(pVCpu);
    12961296
    12971297    /* Inform CPUM (recompiler), can later be removed. */

  • trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

    r104932 r104990  
    26822682    }
    26832683
    2684     IEMTlbInvalidateAll(pVCpu);
     2684    if (!fGlobal)
     2685        IEMTlbInvalidateAll(pVCpu);
     2686    else
     2687        IEMTlbInvalidateAllGlobal(pVCpu);
    26852688    STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLB), a);
    26862689    return rc;

  • trunk/src/VBox/VMM/VMMR3/IEMR3.cpp

    r104957 r104990  
    324324        STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision,        STAMTYPE_X64,       STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
    325325                        "Code TLB revision",                            "/IEM/CPU%u/Tlb/Code/Revision", idCpu);
     326        STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlsFlushes,         STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
     327                        "Code TLB non-global flushes",                  "/IEM/CPU%u/Tlb/Code/RevisionNonGlobalFlushes", idCpu);
     328        STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlsGlobalFlushes,   STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
     329                        "Code TLB global flushes",                      "/IEM/CPU%u/Tlb/Code/RevisionGlobalFlushes", idCpu);
     330        STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbRevisionRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
     331                        "Code TLB revision rollovers",                  "/IEM/CPU%u/Tlb/Code/RevisionRollovers", idCpu);
     332
    326333        STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64,       STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
    327                         "Code TLB physical revision",                   "/IEM/CPU%u/Tlb/Code/RevisionPhysical", idCpu);
     334                        "Code TLB physical revision",                   "/IEM/CPU%u/Tlb/Code/PhysicalRevision", idCpu);
     335        STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbPhysRevFlushes,  STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
     336                        "Code TLB revision flushes",                    "/IEM/CPU%u/Tlb/Code/PhysicalRevisionFlushes", idCpu);
     337        STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbPhysRevRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
     338                        "Code TLB revision rollovers",                  "/IEM/CPU%u/Tlb/Code/PhysicalRevisionRollovers", idCpu);
    328339
    329340        STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbCoreMisses,      STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
    … …  
    383394        STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision,        STAMTYPE_X64,       STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
    384395                        "Data TLB revision",                            "/IEM/CPU%u/Tlb/Data/Revision", idCpu);
     396        STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlsFlushes,         STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
     397                        "Data TLB non-global flushes",                  "/IEM/CPU%u/Tlb/Data/RevisionNonGlobalFlushes", idCpu);
     398        STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlsGlobalFlushes,   STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
     399                        "Data TLB global flushes",                      "/IEM/CPU%u/Tlb/Data/RevisionGlobalFlushes", idCpu);
     400        STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbRevisionRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
     401                        "Data TLB revision rollovers",                  "/IEM/CPU%u/Tlb/Data/RevisionRollovers", idCpu);
     402
    385403        STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64,       STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
    386                         "Data TLB physical revision",                   "/IEM/CPU%u/Tlb/Data/RevisionPhysical", idCpu);
     404                        "Data TLB physical revision",                   "/IEM/CPU%u/Tlb/Data/PhysicalRevision", idCpu);
     405        STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbPhysRevFlushes,  STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
     406                        "Data TLB revision flushes",                    "/IEM/CPU%u/Tlb/Data/PhysicalRevisionFlushes", idCpu);
     407        STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbPhysRevRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
     408                        "Data TLB revision rollovers",                  "/IEM/CPU%u/Tlb/Data/PhysicalRevisionRollovers", idCpu);
    387409
    388410        STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbCoreMisses,      STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
    … …  
    13951417    if (pVCpu)
    13961418    {
    1397         VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAll, 1, pVCpu);
     1419        VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAllGlobal, 1, pVCpu);
    13981420        return VINF_SUCCESS;
    13991421    }

  • trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp

    r104910 r104990  
    62976297        IEMTlbInvalidateAllPhysical(pVCpu);
    62986298#else
    6299         IEMTlbInvalidateAll(pVCpu);
     6299        IEMTlbInvalidateAllGlobal(pVCpu);
    63006300#endif
    63016301        STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cA20Changes);

  • trunk/src/VBox/VMM/include/IEMInternal.h

    r104984 r104990  
    600600    uint32_t            cTlbSlowCodeReadPath;
    601601
    602     /** Alignment padding. */
    603     uint32_t            au32Padding[5];
     602    /** Regular TLB flush count. */
     603    uint32_t            cTlsFlushes;
     604    /** Global TLB flush count. */
     605    uint32_t            cTlsGlobalFlushes;
     606    /** Revision rollovers. */
     607    uint32_t            cTlbRevisionRollovers;
     608    /** Physical revision flushes. */
     609    uint32_t            cTlbPhysRevFlushes;
     610    /** Physical revision rollovers. */
     611    uint32_t            cTlbPhysRevRollovers;
    604612
    605613    /** The TLB entries. */
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