Changeset 107389 in vbox for trunk/include/VBox/vmm
- Timestamp:
- Dec 19, 2024 3:55:08 PM (3 months ago)
- svn:sync-xref-src-repo-rev:
- 166432
- Location:
- trunk/include/VBox/vmm
- Files:
-
- 3 edited
-
cpum-armv8.h (modified) (1 diff)
-
cpum-x86-amd64.h (modified) (1 diff)
-
cpum.h (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/cpum-armv8.h
r107031 r107389 164 164 /** Pointer to a const system register range. */ 165 165 typedef CPUMSYSREGRANGE const *PCCPUMSYSREGRANGE; 166 167 168 /**169 * CPU features and quirks.170 * This is mostly exploded CPUID info.171 */172 typedef struct CPUMFEATURES173 {174 /** The CPU vendor (CPUMCPUVENDOR). */175 uint8_t enmCpuVendor;176 /** The CPU family. */177 uint8_t uFamily;178 /** The CPU model. */179 uint8_t uModel;180 /** The CPU stepping. */181 uint8_t uStepping;182 /** The microarchitecture. */183 #ifndef VBOX_FOR_DTRACE_LIB184 CPUMMICROARCH enmMicroarch;185 #else186 uint32_t enmMicroarch;187 #endif188 /** The maximum physical address width of the CPU. */189 uint8_t cMaxPhysAddrWidth;190 /** The maximum linear address width of the CPU. */191 uint8_t cMaxLinearAddrWidth;192 uint16_t uPadding;193 194 /** @name Granule sizes supported.195 * @{ */196 /** 4KiB translation granule size supported. */197 uint32_t fTGran4K : 1;198 /** 16KiB translation granule size supported. */199 uint32_t fTGran16K : 1;200 /** 64KiB translation granule size supported. */201 uint32_t fTGran64K : 1;202 /** @} */203 204 /** @name pre-2020 Architecture Extensions.205 * @{ */206 /** Supports Advanced SIMD Extension (FEAT_AdvSIMD). */207 uint32_t fAdvSimd : 1;208 /** Supports Advanced SIMD AES instructions (FEAT_AES). */209 uint32_t fAes : 1;210 /** Supports Advanced SIMD PMULL instructions (FEAT_PMULL). */211 uint32_t fPmull : 1;212 /** Supports CP15Disable2 (FEAT_CP15DISABLE2). */213 uint32_t fCp15Disable2 : 1;214 /** Supports Cache Speculation Variant 2 (FEAT_CSV2). */215 uint32_t fCsv2 : 1;216 /** Supports Cache Speculation Variant 2, version 1.1 (FEAT_CSV2_1p1). */217 uint32_t fCsv21p1 : 1;218 /** Supports Cache Speculation Variant 2, version 1.2 (FEAT_CSV2_1p2). */219 uint32_t fCsv21p2 : 1;220 /** Supports Cache Speculation Variant 3 (FEAT_CSV3). */221 uint32_t fCsv3 : 1;222 /** Supports Data Gahtering Hint (FEAT_DGH). */223 uint32_t fDgh : 1;224 /** Supports Double Lock (FEAT_DoubleLock). */225 uint32_t fDoubleLock : 1;226 /** Supports Enhanced Translation Synchronization (FEAT_ETS2). */227 uint32_t fEts2 : 1;228 /** Supports Floating Point Extensions (FEAT_FP). */229 uint32_t fFp : 1;230 /** Supports IVIPT Extensions (FEAT_IVIPT). */231 uint32_t fIvipt : 1;232 /** Supports PC Sample-based Profiling Extension (FEAT_PCSRv8). */233 uint32_t fPcsrV8 : 1;234 /** Supports Speculation Restrictions instructions (FEAT_SPECRES). */235 uint32_t fSpecres : 1;236 /** Supports Reliability, Availability, and Serviceability (RAS) Extension (FEAT_RAS). */237 uint32_t fRas : 1;238 /** Supports Speculation Barrier (FEAT_SB). */239 uint32_t fSb : 1;240 /** Supports Advanced SIMD SHA1 instructions (FEAT_SHA1). */241 uint32_t fSha1 : 1;242 /** Supports Advanced SIMD SHA256 instructions (FEAT_SHA256). */243 uint32_t fSha256 : 1;244 /** Supports Speculation Store Bypass Safe (FEAT_SSBS). */245 uint32_t fSsbs : 1;246 /** Supports MRS and MSR instructions for Speculation Store Bypass Safe version 2 (FEAT_SSBS2). */247 uint32_t fSsbs2 : 1;248 /** Supports CRC32 instructions (FEAT_CRC32). */249 uint32_t fCrc32 : 1;250 /** Supports Intermediate chacing of trnslation table walks (FEAT_nTLBPA). */251 uint32_t fNTlbpa : 1;252 /** Supports debug with VHE (FEAT_Debugv8p1). */253 uint32_t fDebugV8p1 : 1;254 /** Supports Hierarchical permission disables in translation tables (FEAT_HPDS). */255 uint32_t fHpds : 1;256 /** Supports Limited ordering regions (FEAT_LOR). */257 uint32_t fLor : 1;258 /** Supports Lare Systems Extensons (FEAT_LSE). */259 uint32_t fLse : 1;260 /** Supports Privileged access never (FEAT_PAN). */261 uint32_t fPan : 1;262 /** Supports Armv8.1 PMU extensions (FEAT_PMUv3p1). */263 uint32_t fPmuV3p1 : 1;264 /** Supports Advanced SIMD rouding double multiply accumulate instructions (FEAT_RDM). */265 uint32_t fRdm : 1;266 /** Supports hardware management of the Access flag and dirty state (FEAT_HAFDBS). */267 uint32_t fHafdbs : 1;268 /** Supports Virtualization Host Extensions (FEAT_VHE). */269 uint32_t fVhe : 1;270 /** Supports 16-bit VMID (FEAT_VMID16). */271 uint32_t fVmid16 : 1;272 /** Supports AArch32 BFloat16 instructions (FEAT_AA32BF16). */273 uint32_t fAa32Bf16 : 1;274 /** Supports AArch32 Hierarchical permission disables (FEAT_AA32HPD). */275 uint32_t fAa32Hpd : 1;276 /** Supports AArch32 Int8 matrix multiplication instructions (FEAT_AA32I8MM). */277 uint32_t fAa32I8mm : 1;278 /** Supports AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN (FEAT_PAN2). */279 uint32_t fPan2 : 1;280 /** Supports AArch64 BFloat16 instructions (FEAT_BF16). */281 uint32_t fBf16 : 1;282 /** Supports DC CVADP instruction (FEAT_DPB2). */283 uint32_t fDpb2 : 1;284 /** Supports DC VAP instruction (FEAT_DPB). */285 uint32_t fDpb : 1;286 /** Supports Debug v8.2 (FEAT_Debugv8p2). */287 uint32_t fDebugV8p2 : 1;288 /** Supports Advanced SIMD dot product instructions (FEAT_DotProd). */289 uint32_t fDotProd : 1;290 /** Supports Enhanced Virtualization Traps (FEAT_EVT). */291 uint32_t fEvt : 1;292 /** Supports Single precision Matrix Multiplication (FEAT_F32MM). */293 uint32_t fF32mm : 1;294 /** Supports Double precision Matrix Multiplication (FEAT_F64MM). */295 uint32_t fF64mm : 1;296 /** Supports Floating-point half precision multiplication instructions (FEAT_FHM). */297 uint32_t fFhm : 1;298 /** Supports Half-precision floating point data processing (FEAT_FP16). */299 uint32_t fFp16 : 1;300 /** Supports AArch64 Int8 matrix multiplication instructions (FEAT_I8MM). */301 uint32_t fI8mm : 1;302 /** Supports Implicit Error Synchronization event (FEAT_IESB). */303 uint32_t fIesb : 1;304 /** Supports Large PA and IPA support (FEAT_LPA). */305 uint32_t fLpa : 1;306 /** Supports AArch32 Load/Store Multiple instructions atomicity and ordering controls (FEAT_LSMAOC). */307 uint32_t fLsmaoc : 1;308 /** Supports Large VA support (FEAT_LVA). */309 uint32_t fLva : 1;310 /** Supports Memory Partitioning and Monitoring Extension (FEAT_MPAM). */311 uint32_t fMpam : 1;312 /** Supports PC Sample-based Profiling Extension, version 8.2 (FEAT_PCSRv8p2). */313 uint32_t fPcsrV8p2 : 1;314 /** Supports Advanced SIMD SHA3 instructions (FEAT_SHA3). */315 uint32_t fSha3 : 1;316 /** Supports Advanced SIMD SHA512 instructions (FEAT_SHA512). */317 uint32_t fSha512 : 1;318 /** Supports Advanced SIMD SM3 instructions (FEAT_SM3). */319 uint32_t fSm3 : 1;320 /** Supports Advanced SIMD SM4 instructions (FEAT_SM4). */321 uint32_t fSm4 : 1;322 /** Supports Statistical Profiling Extension (FEAT_SPE). */323 uint32_t fSpe : 1;324 /** Supports Scalable Vector Extension (FEAT_SVE). */325 uint32_t fSve : 1;326 /** Supports Translation Table Common not private translations (FEAT_TTCNP). */327 uint32_t fTtcnp : 1;328 /** Supports Hierarchical permission disables, version 2 (FEAT_HPDS2). */329 uint32_t fHpds2 : 1;330 /** Supports Translation table stage 2 Unprivileged Execute-never (FEAT_XNX). */331 uint32_t fXnx : 1;332 /** Supports Unprivileged Access Override control (FEAT_UAO). */333 uint32_t fUao : 1;334 /** Supports VMID-aware PIPT instruction cache (FEAT_VPIPT). */335 uint32_t fVpipt : 1;336 /** Supports Extended cache index (FEAT_CCIDX). */337 uint32_t fCcidx : 1;338 /** Supports Floating-point complex number instructions (FEAT_FCMA). */339 uint32_t fFcma : 1;340 /** Supports Debug over Powerdown (FEAT_DoPD). */341 uint32_t fDopd : 1;342 /** Supports Enhanced pointer authentication (FEAT_EPAC). */343 uint32_t fEpac : 1;344 /** Supports Faulting on AUT* instructions (FEAT_FPAC). */345 uint32_t fFpac : 1;346 /** Supports Faulting on combined pointer euthentication instructions (FEAT_FPACCOMBINE). */347 uint32_t fFpacCombine : 1;348 /** Supports JavaScript conversion instructions (FEAT_JSCVT). */349 uint32_t fJscvt : 1;350 /** Supports Load-Acquire RCpc instructions (FEAT_LRCPC). */351 uint32_t fLrcpc : 1;352 /** Supports Nexted Virtualization (FEAT_NV). */353 uint32_t fNv : 1;354 /** Supports QARMA5 pointer authentication algorithm (FEAT_PACQARMA5). */355 uint32_t fPacQarma5 : 1;356 /** Supports implementation defined pointer authentication algorithm (FEAT_PACIMP). */357 uint32_t fPacImp : 1;358 /** Supports Pointer authentication (FEAT_PAuth). */359 uint32_t fPAuth : 1;360 /** Supports Enhancements to pointer authentication (FEAT_PAuth2). */361 uint32_t fPAuth2 : 1;362 /** Supports Statistical Profiling Extensions version 1.1 (FEAT_SPEv1p1). */363 uint32_t fSpeV1p1 : 1;364 /** Supports Activity Monitor Extension, version 1 (FEAT_AMUv1). */365 uint32_t fAmuV1 : 1;366 /** Supports Generic Counter Scaling (FEAT_CNTSC). */367 uint32_t fCntsc : 1;368 /** Supports Debug v8.4 (FEAT_Debugv8p4). */369 uint32_t fDebugV8p4 : 1;370 /** Supports Double Fault Extension (FEAT_DoubleFault). */371 uint32_t fDoubleFault : 1;372 /** Supports Data Independent Timing instructions (FEAT_DIT). */373 uint32_t fDit : 1;374 /** Supports Condition flag manipulation isntructions (FEAT_FlagM). */375 uint32_t fFlagM : 1;376 /** Supports ID space trap handling (FEAT_IDST). */377 uint32_t fIdst : 1;378 /** Supports Load-Acquire RCpc instructions version 2 (FEAT_LRCPC2). */379 uint32_t fLrcpc2 : 1;380 /** Supports Large Sytem Extensions version 2 (FEAT_LSE2). */381 uint32_t fLse2 : 1;382 /** Supports Enhanced nested virtualization support (FEAT_NV2). */383 uint32_t fNv2 : 1;384 /** Supports Armv8.4 PMU Extensions (FEAT_PMUv3p4). */385 uint32_t fPmuV3p4 : 1;386 /** Supports RAS Extension v1.1 (FEAT_RASv1p1). */387 uint32_t fRasV1p1 : 1;388 /** Supports RAS Extension v1.1 System Architecture (FEAT_RASSAv1p1). */389 uint32_t fRassaV1p1 : 1;390 /** Supports Stage 2 forced Write-Back (FEAT_S2FWB). */391 uint32_t fS2Fwb : 1;392 /** Supports Secure El2 (FEAT_SEL2). */393 uint32_t fSecEl2 : 1;394 /** Supports TLB invalidate instructions on Outer Shareable domain (FEAT_TLBIOS). */395 uint32_t fTlbios : 1;396 /** Supports TLB invalidate range instructions (FEAT_TLBIRANGE). */397 uint32_t fTlbirange : 1;398 /** Supports Self-hosted Trace Extensions (FEAT_TRF). */399 uint32_t fTrf : 1;400 /** Supports Translation Table Level (FEAT_TTL). */401 uint32_t fTtl : 1;402 /** Supports Translation table break-before-make levels (FEAT_BBM). */403 uint32_t fBbm : 1;404 /** Supports Small translation tables (FEAT_TTST). */405 uint32_t fTtst : 1;406 /** Supports Branch Target Identification (FEAT_BTI). */407 uint32_t fBti : 1;408 /** Supports Enhancements to flag manipulation instructions (FEAT_FlagM2). */409 uint32_t fFlagM2 : 1;410 /** Supports Context synchronization and exception handling (FEAT_ExS). */411 uint32_t fExs : 1;412 /** Supports Preenting EL0 access to halves of address maps (FEAT_E0PD). */413 uint32_t fE0Pd : 1;414 /** Supports Floating-point to integer instructions (FEAT_FRINTTS). */415 uint32_t fFrintts : 1;416 /** Supports Guest translation granule size (FEAT_GTG). */417 uint32_t fGtg : 1;418 /** Supports Instruction-only Memory Tagging Extension (FEAT_MTE). */419 uint32_t fMte : 1;420 /** Supports memory Tagging Extension version 2 (FEAT_MTE2). */421 uint32_t fMte2 : 1;422 /** Supports Armv8.5 PMU Extensions (FEAT_PMUv3p5). */423 uint32_t fPmuV3p5 : 1;424 /** Supports Random number generator (FEAT_RNG). */425 uint32_t fRng : 1;426 /** Supports AMU Extensions version 1.1 (FEAT_AMUv1p1). */427 uint32_t fAmuV1p1 : 1;428 /** Supports Enhanced Counter Virtualization (FEAT_ECV). */429 uint32_t fEcv : 1;430 /** Supports Fine Grain Traps (FEAT_FGT). */431 uint32_t fFgt : 1;432 /** Supports Memory Partitioning and Monitoring version 0.1 (FEAT_MPAMv0p1). */433 uint32_t fMpamV0p1 : 1;434 /** Supports Memory Partitioning and Monitoring version 1.1 (FEAT_MPAMv1p1). */435 uint32_t fMpamV1p1 : 1;436 /** Supports Multi-threaded PMU Extensions (FEAT_MTPMU). */437 uint32_t fMtPmu : 1;438 /** Supports Delayed Trapping of WFE (FEAT_TWED). */439 uint32_t fTwed : 1;440 /** Supports Embbedded Trace Macrocell version 4 (FEAT_ETMv4). */441 uint32_t fEtmV4 : 1;442 /** Supports Embbedded Trace Macrocell version 4.1 (FEAT_ETMv4p1). */443 uint32_t fEtmV4p1 : 1;444 /** Supports Embbedded Trace Macrocell version 4.2 (FEAT_ETMv4p2). */445 uint32_t fEtmV4p2 : 1;446 /** Supports Embbedded Trace Macrocell version 4.3 (FEAT_ETMv4p3). */447 uint32_t fEtmV4p3 : 1;448 /** Supports Embbedded Trace Macrocell version 4.4 (FEAT_ETMv4p4). */449 uint32_t fEtmV4p4 : 1;450 /** Supports Embbedded Trace Macrocell version 4.5 (FEAT_ETMv4p5). */451 uint32_t fEtmV4p5 : 1;452 /** Supports Embbedded Trace Macrocell version 4.6 (FEAT_ETMv4p6). */453 uint32_t fEtmV4p6 : 1;454 /** Supports Generic Interrupt Controller version 3 (FEAT_GICv3). */455 uint32_t fGicV3 : 1;456 /** Supports Generic Interrupt Controller version 3.1 (FEAT_GICv3p1). */457 uint32_t fGicV3p1 : 1;458 /** Supports Trapping Non-secure EL1 writes to ICV_DIR (FEAT_GICv3_TDIR). */459 uint32_t fGicV3Tdir : 1;460 /** Supports Generic Interrupt Controller version 4 (FEAT_GICv4). */461 uint32_t fGicV4 : 1;462 /** Supports Generic Interrupt Controller version 4.1 (FEAT_GICv4p1). */463 uint32_t fGicV4p1 : 1;464 /** Supports PMU extension, version 3 (FEAT_PMUv3). */465 uint32_t fPmuV3 : 1;466 /** Supports Embedded Trace Extension (FEAT_ETE). */467 uint32_t fEte : 1;468 /** Supports Embedded Trace Extension, version 1.1 (FEAT_ETEv1p1). */469 uint32_t fEteV1p1 : 1;470 /** Supports Embedded Trace Extension, version 1.2 (FEAT_ETEv1p2). */471 uint32_t fEteV1p2 : 1;472 /** Supports Scalable Vector Extension version 2 (FEAT_SVE2). */473 uint32_t fSve2 : 1;474 /** Supports Scalable Vector AES instructions (FEAT_SVE_AES). */475 uint32_t fSveAes : 1;476 /** Supports Scalable Vector PMULL instructions (FEAT_SVE_PMULL128). */477 uint32_t fSvePmull128 : 1;478 /** Supports Scalable Vector Bit Permutes instructions (FEAT_SVE_BitPerm). */479 uint32_t fSveBitPerm : 1;480 /** Supports Scalable Vector SHA3 instructions (FEAT_SVE_SHA3). */481 uint32_t fSveSha3 : 1;482 /** Supports Scalable Vector SM4 instructions (FEAT_SVE_SM4). */483 uint32_t fSveSm4 : 1;484 /** Supports Transactional Memory Extension (FEAT_TME). */485 uint32_t fTme : 1;486 /** Supports Trace Buffer Extension (FEAT_TRBE). */487 uint32_t fTrbe : 1;488 /** Supports Scalable Matrix Extension (FEAT_SME). */489 uint32_t fSme : 1;490 /** @} */491 492 /** @name 2020 Architecture Extensions.493 * @{ */494 /** Supports Alternate floating-point behavior (FEAT_AFP). */495 uint32_t fAfp : 1;496 /** Supports HCRX_EL2 register (FEAT_HCX). */497 uint32_t fHcx : 1;498 /** Supports Larger phsical address for 4KiB and 16KiB translation granules (FEAT_LPA2). */499 uint32_t fLpa2 : 1;500 /** Supports 64 byte loads and stores without return (FEAT_LS64). */501 uint32_t fLs64 : 1;502 /** Supports 64 byte stores with return (FEAT_LS64_V). */503 uint32_t fLs64V : 1;504 /** Supports 64 byte EL0 stores with return (FEAT_LS64_ACCDATA). */505 uint32_t fLs64Accdata : 1;506 /** Supports MTE Asymmetric Fault Handling (FEAT_MTE3). */507 uint32_t fMte3 : 1;508 /** Supports SCTLR_ELx.EPAN (FEAT_PAN3). */509 uint32_t fPan3 : 1;510 /** Supports Armv8.7 PMU extensions (FEAT_PMUv3p7). */511 uint32_t fPmuV3p7 : 1;512 /** Supports Increased precision of Reciprocal Extimate and Reciprocal Square Root Estimate (FEAT_RPRES). */513 uint32_t fRpres : 1;514 /** Supports Realm Management Extension (FEAT_RME). */515 uint32_t fRme : 1;516 /** Supports Full A64 instruction set support in Streaming SVE mode (FEAT_SME_FA64). */517 uint32_t fSmeFA64 : 1;518 /** Supports Double-precision floating-point outer product instructions (FEAT_SME_F64F64). */519 uint32_t fSmeF64F64 : 1;520 /** Supports 16-bit to 64-bit integer widening outer product instructions (FEAT_SME_I16I64). */521 uint32_t fSmeI16I64 : 1;522 /** Supports Statistical Profiling Extensions version 1.2 (FEAT_SPEv1p2). */523 uint32_t fSpeV1p2 : 1;524 /** Supports AArch64 Extended BFloat16 instructions (FEAT_EBF16). */525 uint32_t fEbf16 : 1;526 /** Supports WFE and WFI instructions with timeout (FEAT_WFxT). */527 uint32_t fWfxt : 1;528 /** Supports XS attribute (FEAT_XS). */529 uint32_t fXs : 1;530 /** Supports branch Record Buffer Extension (FEAT_BRBE). */531 uint32_t fBrbe : 1;532 /** @} */533 534 /** @name 2021 Architecture Extensions.535 * @{ */536 /** Supports Control for cache maintenance permission (FEAT_CMOW). */537 uint32_t fCmow : 1;538 /** Supports PAC algorithm enhancement (FEAT_CONSTPACFIELD). */539 uint32_t fConstPacField : 1;540 /** Supports Debug v8.8 (FEAT_Debugv8p8). */541 uint32_t fDebugV8p8 : 1;542 /** Supports Hinted conditional branches (FEAT_HBC). */543 uint32_t fHbc : 1;544 /** Supports Setting of MDCR_EL2.HPMN to zero (FEAT_HPMN0). */545 uint32_t fHpmn0 : 1;546 /** Supports Non-Maskable Interrupts (FEAT_NMI). */547 uint32_t fNmi : 1;548 /** Supports GIC Non-Maskable Interrupts (FEAT_GICv3_NMI). */549 uint32_t fGicV3Nmi : 1;550 /** Supports Standardization of memory operations (FEAT_MOPS). */551 uint32_t fMops : 1;552 /** Supports Pointer authentication - QARMA3 algorithm (FEAT_PACQARMA3). */553 uint32_t fPacQarma3 : 1;554 /** Supports Event counting threshold (FEAT_PMUv3_TH). */555 uint32_t fPmuV3Th : 1;556 /** Supports Armv8.8 PMU extensions (FEAT_PMUv3p8). */557 uint32_t fPmuV3p8 : 1;558 /** Supports 64-bit external interface to the Performance Monitors (FEAT_PMUv3_EXT64). */559 uint32_t fPmuV3Ext64 : 1;560 /** Supports 32-bit external interface to the Performance Monitors (FEAT_PMUv3_EXT32). */561 uint32_t fPmuV3Ext32 : 1;562 /** Supports External interface to the Performance Monitors (FEAT_PMUv3_EXT). */563 uint32_t fPmuV3Ext : 1;564 /** Supports Trapping support for RNDR/RNDRRS (FEAT_RNG_TRAP). */565 uint32_t fRngTrap : 1;566 /** Supports Statistical Profiling Extension version 1.3 (FEAT_SPEv1p3). */567 uint32_t fSpeV1p3 : 1;568 /** Supports EL0 use of IMPLEMENTATION DEFINEd functionality (FEAT_TIDCP1). */569 uint32_t fTidcp1 : 1;570 /** Supports Branch Record Buffer Extension version 1.1 (FEAT_BRBEv1p1). */571 uint32_t fBrbeV1p1 : 1;572 /** @} */573 574 /** @name 2022 Architecture Extensions.575 * @{ */576 /** Supports Address Breakpoint Linking Extenions (FEAT_ABLE). */577 uint32_t fAble : 1;578 /** Supports Asynchronous Device error exceptions (FEAT_ADERR). */579 uint32_t fAderr : 1;580 /** Supports Memory Attribute Index Enhancement (FEAT_AIE). */581 uint32_t fAie : 1;582 /** Supports Asynchronous Normal error exception (FEAT_ANERR). */583 uint32_t fAnerr : 1;584 /** Supports Breakpoint Mismatch and Range Extension (FEAT_BWE). */585 uint32_t fBwe : 1;586 /** Supports Clear Branch History instruction (FEAT_CLRBHB). */587 uint32_t fClrBhb : 1;588 /** Supports Check Feature Status (FEAT_CHK). */589 uint32_t fChk : 1;590 /** Supports Common Short Sequence Compression instructions (FEAT_CSSC). */591 uint32_t fCssc : 1;592 /** Supports Cache Speculation Variant 2 version 3 (FEAT_CSV2_3). */593 uint32_t fCsv2v3 : 1;594 /** Supports 128-bit Translation Tables, 56 bit PA (FEAT_D128). */595 uint32_t fD128 : 1;596 /** Supports Debug v8.9 (FEAT_Debugv8p9). */597 uint32_t fDebugV8p9 : 1;598 /** Supports Enhancements to the Double Fault Extension (FEAT_DoubleFault2). */599 uint32_t fDoubleFault2 : 1;600 /** Supports Exception based Event Profiling (FEAT_EBEP). */601 uint32_t fEbep : 1;602 /** Supports Exploitative control using branch history information (FEAT_ECBHB). */603 uint32_t fEcBhb : 1;604 /** Supports for EDHSR (FEAT_EDHSR). */605 uint32_t fEdhsr : 1;606 /** Supports Embedded Trace Extension version 1.3 (FEAT_ETEv1p3). */607 uint32_t fEteV1p3 : 1;608 /** Supports Fine-grained traps 2 (FEAT_FGT2). */609 uint32_t fFgt2 : 1;610 /** Supports Guarded Control Stack Extension (FEAT_GCS). */611 uint32_t fGcs : 1;612 /** Supports Hardware managed Access Flag for Table descriptors (FEAT_HAFT). */613 uint32_t fHaft : 1;614 /** Supports Instrumentation Extension (FEAT_ITE). */615 uint32_t fIte : 1;616 /** Supports Load-Acquire RCpc instructions version 3 (FEAT_LRCPC3). */617 uint32_t fLrcpc3 : 1;618 /** Supports 128-bit atomics (FEAT_LSE128). */619 uint32_t fLse128 : 1;620 /** Supports 56-bit VA (FEAT_LVA3). */621 uint32_t fLva3 : 1;622 /** Supports Memory Encryption Contexts (FEAT_MEC). */623 uint32_t fMec : 1;624 /** Supports Enhanced Memory Tagging Extension (FEAT_MTE4). */625 uint32_t fMte4 : 1;626 /** Supports Canoncial Tag checking for untagged memory (FEAT_MTE_CANONCIAL_TAGS). */627 uint32_t fMteCanonicalTags : 1;628 /** Supports FAR_ELx on a Tag Check Fault (FEAT_MTE_TAGGED_FAR). */629 uint32_t fMteTaggedFar : 1;630 /** Supports Store only Tag checking (FEAT_MTE_STORE_ONLY). */631 uint32_t fMteStoreOnly : 1;632 /** Supports Memory tagging with Address tagging disabled (FEAT_MTE_NO_ADDRESS_TAGS). */633 uint32_t fMteNoAddressTags : 1;634 /** Supports Memory tagging asymmetric faults (FEAT_MTE_ASYM_FAULT). */635 uint32_t fMteAsymFault : 1;636 /** Supports Memory Tagging asynchronous faulting (FEAT_MTE_ASYNC). */637 uint32_t fMteAsync : 1;638 /** Supports Allocation tag access permission (FEAT_MTE_PERM_S1). */639 uint32_t fMtePermS1 : 1;640 /** Supports Armv8.9 PC Sample-based Profiling Extension (FEAT_PCSRv8p9). */641 uint32_t fPcsrV8p9 : 1;642 /** Supports Permission model enhancements (FEAT_S1PIE). */643 uint32_t fS1Pie : 1;644 /** Supports Permission model enhancements (FEAT_S2PIE). */645 uint32_t fS2Pie : 1;646 /** Supports Permission model enhancements (FEAT_S1POE). */647 uint32_t fS1Poe : 1;648 /** Supports Permission model enhancements (FEAT_S2POE). */649 uint32_t fS2Poe : 1;650 /** Supports Physical Fault Address Registers (FEAT_PFAR). */651 uint32_t fPfar : 1;652 /** Supports Armv8.9 PMU extensions (FEAT_PMUv3p9). */653 uint32_t fPmuV3p9 : 1;654 /** Supports PMU event edge detection (FEAT_PMUv3_EDGE). */655 uint32_t fPmuV3Edge : 1;656 /** Supports Fixed-function instruction counter (FEAT_PMUv3_ICNTR). */657 uint32_t fPmuV3Icntr : 1;658 /** Supports PMU Snapshot Extension (FEAT_PMUv3_SS). */659 uint32_t fPmuV3Ss : 1;660 /** Supports SLC traget for PRFM instructions (FEAT_PRFMSLC). */661 uint32_t fPrfmSlc : 1;662 /** Supports RAS version 2 (FEAT_RASv2). */663 uint32_t fRasV2 : 1;664 /** Supports RAS version 2 System Architecture (FEAT_RASSAv2). */665 uint32_t fRasSaV2 : 1;666 /** Supports for Range Prefetch Memory instruction (FEAT_RPRFM). */667 uint32_t fRprfm : 1;668 /** Supports extensions to SCTLR_ELx (FEAT_SCTLR2). */669 uint32_t fSctlr2 : 1;670 /** Supports Synchronous Exception-based Event Profiling (FEAT_SEBEP). */671 uint32_t fSebep : 1;672 /** Supports non-widening half-precision FP16 to FP16 arithmetic for SME2.1 (FEAT_SME_F16F16). */673 uint32_t fSmeF16F16 : 1;674 /** Supports Scalable Matrix Extension version 2 (FEAT_SME2). */675 uint32_t fSme2 : 1;676 /** Supports Scalable Matrix Extension version 2.1 (FEAT_SME2p1). */677 uint32_t fSme2p1 : 1;678 /** Supports Enhanced speculation restriction instructions (FEAT_SPECRES2). */679 uint32_t fSpecres2 : 1;680 /** Supports System Performance Monitors Extension (FEAT_SPMU). */681 uint32_t fSpmu : 1;682 /** Supports Statistical profiling Extension version 1.4 (FEAT_SPEv1p4). */683 uint32_t fSpeV1p4 : 1;684 /** Supports Call Return Branch Records (FEAT_SPE_CRR). */685 uint32_t fSpeCrr : 1;686 /** Supports Data Source Filtering (FEAT_SPE_FDS). */687 uint32_t fSpeFds : 1;688 /** Supports Scalable Vector Extension version SVE2.1 (FEAT_SVE2p1). */689 uint32_t fSve2p1 : 1;690 /** Supports Non-widening BFloat16 to BFloat16 arithmetic for SVE (FEAT_SVE_B16B16). */691 uint32_t fSveB16B16 : 1;692 /** Supports 128-bit System instructions (FEAT_SYSINSTR128). */693 uint32_t fSysInstr128 : 1;694 /** Supports 128-bit System registers (FEAT_SYSREG128). */695 uint32_t fSysReg128 : 1;696 /** Supports Extension to TCR_ELx (FEAT_TCR2). */697 uint32_t fTcr2 : 1;698 /** Supports Translation Hardening Extension (FEAT_THE). */699 uint32_t fThe : 1;700 /** Supports Trace Buffer external mode (FEAT_TRBE_EXT). */701 uint32_t fTrbeExt : 1;702 /** Supports Trace Buffer MPAM extension (FEAT_TRBE_MPAM). */703 uint32_t fTrbeMpam : 1;704 /** @} */705 706 /** Padding to the required size to match CPUMFEATURES for x86/amd64. */707 uint8_t abPadding[4];708 } CPUMFEATURES;709 #ifndef VBOX_FOR_DTRACE_LIB710 AssertCompileSize(CPUMFEATURES, 48);711 #endif712 /** Pointer to a CPU feature structure. */713 typedef CPUMFEATURES *PCPUMFEATURES;714 /** Pointer to a const CPU feature structure. */715 typedef CPUMFEATURES const *PCCPUMFEATURES;716 717 /**718 * Chameleon wrapper structure for the host CPU features.719 *720 * This is used for the globally readable g_CpumHostFeatures variable, which is721 * initialized once during VMMR0 load for ring-0 and during CPUMR3Init in722 * ring-3. To reflect this immutability after load/init, we use this wrapper723 * structure to switch it between const and non-const depending on the context.724 * Only two files sees it as non-const (CPUMR0.cpp and CPUM.cpp).725 */726 typedef struct CPUHOSTFEATURES727 {728 CPUMFEATURES729 #ifndef CPUM_WITH_NONCONST_HOST_FEATURES730 const731 #endif732 s;733 } CPUHOSTFEATURES;734 /** Pointer to a const host CPU feature structure. */735 typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES;736 737 /** Host CPU features.738 * @note In ring-3, only valid after CPUMR3Init. In ring-0, valid after739 * module init. */740 extern CPUHOSTFEATURES g_CpumHostFeatures;741 166 742 167 -
trunk/include/VBox/vmm/cpum-x86-amd64.h
r107220 r107389 753 753 754 754 /** 755 * CPU features and quirks.756 * This is mostly exploded CPUID info.757 */758 typedef struct CPUMFEATURES759 {760 /** The CPU vendor (CPUMCPUVENDOR). */761 uint8_t enmCpuVendor;762 /** The CPU family. */763 uint8_t uFamily;764 /** The CPU model. */765 uint8_t uModel;766 /** The CPU stepping. */767 uint8_t uStepping;768 /** The microarchitecture. */769 #ifndef VBOX_FOR_DTRACE_LIB770 CPUMMICROARCH enmMicroarch;771 #else772 uint32_t enmMicroarch;773 #endif774 /** The maximum physical address width of the CPU. */775 uint8_t cMaxPhysAddrWidth;776 /** The maximum linear address width of the CPU. */777 uint8_t cMaxLinearAddrWidth;778 /** Max size of the extended state (or FPU state if no XSAVE). */779 uint16_t cbMaxExtendedState;780 781 /** Supports MSRs. */782 uint32_t fMsr : 1;783 /** Supports the page size extension (4/2 MB pages). */784 uint32_t fPse : 1;785 /** Supports 36-bit page size extension (4 MB pages can map memory above786 * 4GB). */787 uint32_t fPse36 : 1;788 /** Supports physical address extension (PAE). */789 uint32_t fPae : 1;790 /** Supports page-global extension (PGE). */791 uint32_t fPge : 1;792 /** Page attribute table (PAT) support (page level cache control). */793 uint32_t fPat : 1;794 /** Supports the FXSAVE and FXRSTOR instructions. */795 uint32_t fFxSaveRstor : 1;796 /** Supports the XSAVE and XRSTOR instructions. */797 uint32_t fXSaveRstor : 1;798 /** Supports the XSAVEOPT instruction. */799 uint32_t fXSaveOpt : 1;800 /** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */801 uint32_t fOpSysXSaveRstor : 1;802 /** Supports MMX. */803 uint32_t fMmx : 1;804 /** Supports AMD extensions to MMX instructions. */805 uint32_t fAmdMmxExts : 1;806 /** Supports SSE. */807 uint32_t fSse : 1;808 /** Supports SSE2. */809 uint32_t fSse2 : 1;810 /** Supports SSE3. */811 uint32_t fSse3 : 1;812 /** Supports SSSE3. */813 uint32_t fSsse3 : 1;814 /** Supports SSE4.1. */815 uint32_t fSse41 : 1;816 /** Supports SSE4.2. */817 uint32_t fSse42 : 1;818 /** Supports AVX. */819 uint32_t fAvx : 1;820 /** Supports AVX2. */821 uint32_t fAvx2 : 1;822 /** Supports AVX512 foundation. */823 uint32_t fAvx512Foundation : 1;824 /** Supports RDTSC. */825 uint32_t fTsc : 1;826 /** Intel SYSENTER/SYSEXIT support */827 uint32_t fSysEnter : 1;828 /** Supports MTRR. */829 uint32_t fMtrr : 1;830 /** First generation APIC. */831 uint32_t fApic : 1;832 /** Second generation APIC. */833 uint32_t fX2Apic : 1;834 /** Hypervisor present. */835 uint32_t fHypervisorPresent : 1;836 /** MWAIT & MONITOR instructions supported. */837 uint32_t fMonitorMWait : 1;838 /** MWAIT Extensions present. */839 uint32_t fMWaitExtensions : 1;840 /** Supports CMPXCHG8B. */841 uint32_t fCmpXchg8b : 1;842 /** Supports CMPXCHG16B in 64-bit mode. */843 uint32_t fCmpXchg16b : 1;844 /** Supports CLFLUSH. */845 uint32_t fClFlush : 1;846 /** Supports CLFLUSHOPT. */847 uint32_t fClFlushOpt : 1;848 /** Supports IA32_PRED_CMD.IBPB. */849 uint32_t fIbpb : 1;850 /** Supports IA32_SPEC_CTRL.IBRS. */851 uint32_t fIbrs : 1;852 /** Supports IA32_SPEC_CTRL.STIBP. */853 uint32_t fStibp : 1;854 /** Supports IA32_FLUSH_CMD. */855 uint32_t fFlushCmd : 1;856 /** Supports IA32_ARCH_CAP. */857 uint32_t fArchCap : 1;858 /** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */859 uint32_t fMdsClear : 1;860 /** Supports PCID. */861 uint32_t fPcid : 1;862 /** Supports INVPCID. */863 uint32_t fInvpcid : 1;864 /** Supports read/write FSGSBASE instructions. */865 uint32_t fFsGsBase : 1;866 /** Supports BMI1 instructions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, and TZCNT). */867 uint32_t fBmi1 : 1;868 /** Supports BMI2 instructions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX,869 * and SHLX). */870 uint32_t fBmi2 : 1;871 /** Supports POPCNT instruction. */872 uint32_t fPopCnt : 1;873 /** Supports RDRAND instruction. */874 uint32_t fRdRand : 1;875 /** Supports RDSEED instruction. */876 uint32_t fRdSeed : 1;877 /** Supports Hardware Lock Elision (HLE). */878 uint32_t fHle : 1;879 /** Supports Restricted Transactional Memory (RTM - XBEGIN, XEND, XABORT). */880 uint32_t fRtm : 1;881 /** Supports PCLMULQDQ instruction. */882 uint32_t fPclMul : 1;883 /** Supports AES-NI (six AESxxx instructions). */884 uint32_t fAesNi : 1;885 /** Support MOVBE instruction. */886 uint32_t fMovBe : 1;887 /** Support SHA instructions. */888 uint32_t fSha : 1;889 /** Support ADX instructions. */890 uint32_t fAdx : 1;891 /** Supports FMA. */892 uint32_t fFma : 1;893 /** Supports F16C. */894 uint32_t fF16c : 1;895 896 /** Supports AMD 3DNow instructions. */897 uint32_t f3DNow : 1;898 /** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */899 uint32_t f3DNowPrefetch : 1;900 901 /** AMD64: Supports long mode. */902 uint32_t fLongMode : 1;903 /** AMD64: SYSCALL/SYSRET support. */904 uint32_t fSysCall : 1;905 /** AMD64: No-execute page table bit. */906 uint32_t fNoExecute : 1;907 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */908 uint32_t fLahfSahf : 1;909 /** AMD64: Supports RDTSCP. */910 uint32_t fRdTscP : 1;911 /** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */912 uint32_t fMovCr8In32Bit : 1;913 /** AMD64: Supports XOP (similar to VEX3/AVX). */914 uint32_t fXop : 1;915 /** AMD64: Supports ABM, i.e. the LZCNT instruction. */916 uint32_t fAbm : 1;917 /** AMD64: Supports TBM (BEXTR, BLCFILL, BLCI, BLCIC, BLCMSK, BLCS,918 * BLSFILL, BLSIC, T1MSKC, and TZMSK). */919 uint32_t fTbm : 1;920 921 /** Indicates that FPU instruction and data pointers may leak.922 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer923 * is only saved and restored if an exception is pending. */924 uint32_t fLeakyFxSR : 1;925 926 /** Supports VEX instruction encoding (AVX, BMI, etc.). */927 uint32_t fVex : 1;928 929 /** AMD64: Supports AMD SVM. */930 uint32_t fSvm : 1;931 932 /** Support for Intel VMX. */933 uint32_t fVmx : 1;934 935 /** Indicates that speculative execution control CPUID bits and MSRs are exposed.936 * The details are different for Intel and AMD but both have similar937 * functionality. */938 uint32_t fSpeculationControl : 1;939 940 /** MSR_IA32_ARCH_CAPABILITIES: RDCL_NO (bit 0).941 * @remarks Only safe use after CPUM ring-0 init! */942 uint32_t fArchRdclNo : 1;943 /** MSR_IA32_ARCH_CAPABILITIES: IBRS_ALL (bit 1).944 * @remarks Only safe use after CPUM ring-0 init! */945 uint32_t fArchIbrsAll : 1;946 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 2).947 * @remarks Only safe use after CPUM ring-0 init! */948 uint32_t fArchRsbOverride : 1;949 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 3).950 * @remarks Only safe use after CPUM ring-0 init! */951 uint32_t fArchVmmNeedNotFlushL1d : 1;952 /** MSR_IA32_ARCH_CAPABILITIES: MDS_NO (bit 4).953 * @remarks Only safe use after CPUM ring-0 init! */954 uint32_t fArchMdsNo : 1;955 956 /** Alignment padding / reserved for future use (96 bits total, plus 12 bytes957 * prior to the bit fields -> total of 24 bytes) */958 uint32_t fPadding0 : 19;959 960 961 /** @name SVM962 * @{ */963 /** SVM: Supports Nested-paging. */964 uint32_t fSvmNestedPaging : 1;965 /** SVM: Support LBR (Last Branch Record) virtualization. */966 uint32_t fSvmLbrVirt : 1;967 /** SVM: Supports SVM lock. */968 uint32_t fSvmSvmLock : 1;969 /** SVM: Supports Next RIP save. */970 uint32_t fSvmNextRipSave : 1;971 /** SVM: Supports TSC rate MSR. */972 uint32_t fSvmTscRateMsr : 1;973 /** SVM: Supports VMCB clean bits. */974 uint32_t fSvmVmcbClean : 1;975 /** SVM: Supports Flush-by-ASID. */976 uint32_t fSvmFlusbByAsid : 1;977 /** SVM: Supports decode assist. */978 uint32_t fSvmDecodeAssists : 1;979 /** SVM: Supports Pause filter. */980 uint32_t fSvmPauseFilter : 1;981 /** SVM: Supports Pause filter threshold. */982 uint32_t fSvmPauseFilterThreshold : 1;983 /** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */984 uint32_t fSvmAvic : 1;985 /** SVM: Supports Virtualized VMSAVE/VMLOAD. */986 uint32_t fSvmVirtVmsaveVmload : 1;987 /** SVM: Supports VGIF (Virtual Global Interrupt Flag). */988 uint32_t fSvmVGif : 1;989 /** SVM: Supports GMET (Guest Mode Execute Trap Extension). */990 uint32_t fSvmGmet : 1;991 /** SVM: Supports AVIC in x2APIC mode. */992 uint32_t fSvmX2Avic : 1;993 /** SVM: Supports SSSCheck (SVM Supervisor Shadow Stack). */994 uint32_t fSvmSSSCheck : 1;995 /** SVM: Supports SPEC_CTRL virtualization. */996 uint32_t fSvmSpecCtrl : 1;997 /** SVM: Supports Read-Only Guest Page Table feature. */998 uint32_t fSvmRoGpt : 1;999 /** SVM: Supports HOST_MCE_OVERRIDE. */1000 uint32_t fSvmHostMceOverride : 1;1001 /** SVM: Supports TlbiCtl (INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept). */1002 uint32_t fSvmTlbiCtl : 1;1003 /** SVM: Supports NMI virtualization. */1004 uint32_t fSvmVNmi : 1;1005 /** SVM: Supports IBS virtualizaiton. */1006 uint32_t fSvmIbsVirt : 1;1007 /** SVM: Supports Extended LVT AVIC access changes. */1008 uint32_t fSvmExtLvtAvicAccessChg : 1;1009 /** SVM: Supports Guest VMCB address check. */1010 uint32_t fSvmNstVirtVmcbAddrChk : 1;1011 /** SVM: Supports Bus Lock Threshold. */1012 uint32_t fSvmBusLockThreshold : 1;1013 /** SVM: Padding / reserved for future features (64 bits total w/ max ASID). */1014 uint32_t fSvmPadding0 : 7;1015 /** SVM: Maximum supported ASID. */1016 uint32_t uSvmMaxAsid;1017 /** @} */1018 1019 1020 /** VMX: Maximum physical address width. */1021 uint32_t cVmxMaxPhysAddrWidth : 8;1022 1023 /** @name VMX basic controls.1024 * @{ */1025 /** VMX: Supports INS/OUTS VM-exit instruction info. */1026 uint32_t fVmxInsOutInfo : 1;1027 /** @} */1028 1029 /** @name VMX Pin-based controls.1030 * @{ */1031 /** VMX: Supports external interrupt VM-exit. */1032 uint32_t fVmxExtIntExit : 1;1033 /** VMX: Supports NMI VM-exit. */1034 uint32_t fVmxNmiExit : 1;1035 /** VMX: Supports Virtual NMIs. */1036 uint32_t fVmxVirtNmi : 1;1037 /** VMX: Supports preemption timer. */1038 uint32_t fVmxPreemptTimer : 1;1039 /** VMX: Supports posted interrupts. */1040 uint32_t fVmxPostedInt : 1;1041 /** @} */1042 1043 /** @name VMX Processor-based controls.1044 * @{ */1045 /** VMX: Supports Interrupt-window exiting. */1046 uint32_t fVmxIntWindowExit : 1;1047 /** VMX: Supports TSC offsetting. */1048 uint32_t fVmxTscOffsetting : 1;1049 /** VMX: Supports HLT exiting. */1050 uint32_t fVmxHltExit : 1;1051 /** VMX: Supports INVLPG exiting. */1052 uint32_t fVmxInvlpgExit : 1;1053 /** VMX: Supports MWAIT exiting. */1054 uint32_t fVmxMwaitExit : 1;1055 /** VMX: Supports RDPMC exiting. */1056 uint32_t fVmxRdpmcExit : 1;1057 /** VMX: Supports RDTSC exiting. */1058 uint32_t fVmxRdtscExit : 1;1059 /** VMX: Supports CR3-load exiting. */1060 uint32_t fVmxCr3LoadExit : 1;1061 /** VMX: Supports CR3-store exiting. */1062 uint32_t fVmxCr3StoreExit : 1;1063 /** VMX: Supports tertiary processor-based VM-execution controls. */1064 uint32_t fVmxTertiaryExecCtls : 1;1065 /** VMX: Supports CR8-load exiting. */1066 uint32_t fVmxCr8LoadExit : 1;1067 /** VMX: Supports CR8-store exiting. */1068 uint32_t fVmxCr8StoreExit : 1;1069 /** VMX: Supports TPR shadow. */1070 uint32_t fVmxUseTprShadow : 1;1071 /** VMX: Supports NMI-window exiting. */1072 uint32_t fVmxNmiWindowExit : 1;1073 /** VMX: Supports Mov-DRx exiting. */1074 uint32_t fVmxMovDRxExit : 1;1075 /** VMX: Supports Unconditional I/O exiting. */1076 uint32_t fVmxUncondIoExit : 1;1077 /** VMX: Supportgs I/O bitmaps. */1078 uint32_t fVmxUseIoBitmaps : 1;1079 /** VMX: Supports Monitor Trap Flag. */1080 uint32_t fVmxMonitorTrapFlag : 1;1081 /** VMX: Supports MSR bitmap. */1082 uint32_t fVmxUseMsrBitmaps : 1;1083 /** VMX: Supports MONITOR exiting. */1084 uint32_t fVmxMonitorExit : 1;1085 /** VMX: Supports PAUSE exiting. */1086 uint32_t fVmxPauseExit : 1;1087 /** VMX: Supports secondary processor-based VM-execution controls. */1088 uint32_t fVmxSecondaryExecCtls : 1;1089 /** @} */1090 1091 /** @name VMX Secondary processor-based controls.1092 * @{ */1093 /** VMX: Supports virtualize-APIC access. */1094 uint32_t fVmxVirtApicAccess : 1;1095 /** VMX: Supports EPT (Extended Page Tables). */1096 uint32_t fVmxEpt : 1;1097 /** VMX: Supports descriptor-table exiting. */1098 uint32_t fVmxDescTableExit : 1;1099 /** VMX: Supports RDTSCP. */1100 uint32_t fVmxRdtscp : 1;1101 /** VMX: Supports virtualize-x2APIC mode. */1102 uint32_t fVmxVirtX2ApicMode : 1;1103 /** VMX: Supports VPID. */1104 uint32_t fVmxVpid : 1;1105 /** VMX: Supports WBIND exiting. */1106 uint32_t fVmxWbinvdExit : 1;1107 /** VMX: Supports Unrestricted guest. */1108 uint32_t fVmxUnrestrictedGuest : 1;1109 /** VMX: Supports APIC-register virtualization. */1110 uint32_t fVmxApicRegVirt : 1;1111 /** VMX: Supports virtual-interrupt delivery. */1112 uint32_t fVmxVirtIntDelivery : 1;1113 /** VMX: Supports Pause-loop exiting. */1114 uint32_t fVmxPauseLoopExit : 1;1115 /** VMX: Supports RDRAND exiting. */1116 uint32_t fVmxRdrandExit : 1;1117 /** VMX: Supports INVPCID. */1118 uint32_t fVmxInvpcid : 1;1119 /** VMX: Supports VM functions. */1120 uint32_t fVmxVmFunc : 1;1121 /** VMX: Supports VMCS shadowing. */1122 uint32_t fVmxVmcsShadowing : 1;1123 /** VMX: Supports RDSEED exiting. */1124 uint32_t fVmxRdseedExit : 1;1125 /** VMX: Supports PML. */1126 uint32_t fVmxPml : 1;1127 /** VMX: Supports EPT-violations \#VE. */1128 uint32_t fVmxEptXcptVe : 1;1129 /** VMX: Supports conceal VMX from PT. */1130 uint32_t fVmxConcealVmxFromPt : 1;1131 /** VMX: Supports XSAVES/XRSTORS. */1132 uint32_t fVmxXsavesXrstors : 1;1133 /** VMX: Supports PASID translation. */1134 uint32_t fVmxPasidTranslate : 1;1135 /** VMX: Supports mode-based execute control for EPT. */1136 uint32_t fVmxModeBasedExecuteEpt : 1;1137 /** VMX: Supports sub-page write permissions for EPT. */1138 uint32_t fVmxSppEpt : 1;1139 /** VMX: Supports Intel PT to output guest-physical addresses for EPT. */1140 uint32_t fVmxPtEpt : 1;1141 /** VMX: Supports TSC scaling. */1142 uint32_t fVmxUseTscScaling : 1;1143 /** VMX: Supports TPAUSE, UMONITOR, or UMWAIT. */1144 uint32_t fVmxUserWaitPause : 1;1145 /** VMX: Supports PCONFIG. */1146 uint32_t fVmxPconfig : 1;1147 /** VMX: Supports enclave (ENCLV) exiting. */1148 uint32_t fVmxEnclvExit : 1;1149 /** VMX: Supports VMM bus-lock detection. */1150 uint32_t fVmxBusLockDetect : 1;1151 /** VMX: Supports instruction timeout. */1152 uint32_t fVmxInstrTimeout : 1;1153 /** @} */1154 1155 /** @name VMX Tertiary processor-based controls.1156 * @{ */1157 /** VMX: Supports LOADIWKEY exiting. */1158 uint32_t fVmxLoadIwKeyExit : 1;1159 /** VMX: Supports hypervisor-managed linear address translation (HLAT). */1160 uint32_t fVmxHlat : 1;1161 /** VMX: Supports EPT paging-write control. */1162 uint32_t fVmxEptPagingWrite : 1;1163 /** VMX: Supports Guest-paging verification. */1164 uint32_t fVmxGstPagingVerify : 1;1165 /** VMX: Supports IPI virtualization. */1166 uint32_t fVmxIpiVirt : 1;1167 /** VMX: Supports virtualize IA32_SPEC_CTRL. */1168 uint32_t fVmxVirtSpecCtrl : 1;1169 /** @} */1170 1171 /** @name VMX VM-entry controls.1172 * @{ */1173 /** VMX: Supports load-debug controls on VM-entry. */1174 uint32_t fVmxEntryLoadDebugCtls : 1;1175 /** VMX: Supports IA32e mode guest. */1176 uint32_t fVmxIa32eModeGuest : 1;1177 /** VMX: Supports load guest EFER MSR on VM-entry. */1178 uint32_t fVmxEntryLoadEferMsr : 1;1179 /** VMX: Supports load guest PAT MSR on VM-entry. */1180 uint32_t fVmxEntryLoadPatMsr : 1;1181 /** @} */1182 1183 /** @name VMX VM-exit controls.1184 * @{ */1185 /** VMX: Supports save debug controls on VM-exit. */1186 uint32_t fVmxExitSaveDebugCtls : 1;1187 /** VMX: Supports host-address space size. */1188 uint32_t fVmxHostAddrSpaceSize : 1;1189 /** VMX: Supports acknowledge external interrupt on VM-exit. */1190 uint32_t fVmxExitAckExtInt : 1;1191 /** VMX: Supports save guest PAT MSR on VM-exit. */1192 uint32_t fVmxExitSavePatMsr : 1;1193 /** VMX: Supports load hsot PAT MSR on VM-exit. */1194 uint32_t fVmxExitLoadPatMsr : 1;1195 /** VMX: Supports save guest EFER MSR on VM-exit. */1196 uint32_t fVmxExitSaveEferMsr : 1;1197 /** VMX: Supports load host EFER MSR on VM-exit. */1198 uint32_t fVmxExitLoadEferMsr : 1;1199 /** VMX: Supports save VMX preemption timer on VM-exit. */1200 uint32_t fVmxSavePreemptTimer : 1;1201 /** VMX: Supports secondary VM-exit controls. */1202 uint32_t fVmxSecondaryExitCtls : 1;1203 /** @} */1204 1205 /** @name VMX Miscellaneous data.1206 * @{ */1207 /** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */1208 uint32_t fVmxExitSaveEferLma : 1;1209 /** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */1210 uint32_t fVmxPt : 1;1211 /** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise1212 * VMWRITE cannot modify read-only VM-exit information fields. */1213 uint32_t fVmxVmwriteAll : 1;1214 /** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero1215 * length instructions. */1216 uint32_t fVmxEntryInjectSoftInt : 1;1217 /** @} */1218 1219 /** VMX: Padding / reserved for future features. */1220 uint32_t fVmxPadding0 : 7;1221 /** VMX: Padding / reserved for future, making it a total of 128 bits. */1222 uint32_t fVmxPadding1;1223 } CPUMFEATURES;1224 #ifndef VBOX_FOR_DTRACE_LIB1225 AssertCompileSize(CPUMFEATURES, 48);1226 #endif1227 /** Pointer to a CPU feature structure. */1228 typedef CPUMFEATURES *PCPUMFEATURES;1229 /** Pointer to a const CPU feature structure. */1230 typedef CPUMFEATURES const *PCCPUMFEATURES;1231 1232 /**1233 * Chameleon wrapper structure for the host CPU features.1234 *1235 * This is used for the globally readable g_CpumHostFeatures variable, which is1236 * initialized once during VMMR0 load for ring-0 and during CPUMR3Init in1237 * ring-3. To reflect this immutability after load/init, we use this wrapper1238 * structure to switch it between const and non-const depending on the context.1239 * Only two files sees it as non-const (CPUMR0.cpp and CPUM.cpp).1240 */1241 typedef struct CPUHOSTFEATURES1242 {1243 CPUMFEATURES1244 #ifndef CPUM_WITH_NONCONST_HOST_FEATURES1245 const1246 #endif1247 s;1248 } CPUHOSTFEATURES;1249 /** Pointer to a const host CPU feature structure. */1250 typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES;1251 1252 /** Host CPU features.1253 * @note In ring-3, only valid after CPUMR3Init. In ring-0, valid after1254 * module init. */1255 extern CPUHOSTFEATURES g_CpumHostFeatures;1256 1257 1258 /**1259 755 * CPU database entry. 1260 756 */ -
trunk/include/VBox/vmm/cpum.h
r106061 r107389 349 349 350 350 351 /** 352 * Common portion of the CPU feature structures. 353 */ 354 typedef struct CPUMFEATURESCOMMON 355 { 356 /** The CPU vendor (CPUMCPUVENDOR). */ 357 uint8_t enmCpuVendor; 358 /** The CPU family. */ 359 uint8_t uFamily; 360 /** The CPU model. */ 361 uint8_t uModel; 362 /** The CPU stepping. */ 363 uint8_t uStepping; 364 /** The microarchitecture. */ 365 #ifndef VBOX_FOR_DTRACE_LIB 366 CPUMMICROARCH enmMicroarch; 367 #else 368 uint32_t enmMicroarch; 369 #endif 370 /** The maximum physical address width of the CPU. */ 371 uint8_t cMaxPhysAddrWidth; 372 /** The maximum linear address width of the CPU. */ 373 uint8_t cMaxLinearAddrWidth; 374 } CPUMFEATURESCOMMON; 375 376 /** 377 * CPU features and quirks for X86. 378 * 379 * This is mostly exploded CPUID info. 380 */ 381 typedef struct CPUMFEATURESX86 382 { 383 /** The CPU vendor (CPUMCPUVENDOR). */ 384 uint8_t enmCpuVendor; 385 /** The CPU family. */ 386 uint8_t uFamily; 387 /** The CPU model. */ 388 uint8_t uModel; 389 /** The CPU stepping. */ 390 uint8_t uStepping; 391 /** The microarchitecture. */ 392 #ifndef VBOX_FOR_DTRACE_LIB 393 CPUMMICROARCH enmMicroarch; 394 #else 395 uint32_t enmMicroarch; 396 #endif 397 /** The maximum physical address width of the CPU. */ 398 uint8_t cMaxPhysAddrWidth; 399 /** The maximum linear address width of the CPU. */ 400 uint8_t cMaxLinearAddrWidth; 401 /** Max size of the extended state (or FPU state if no XSAVE). */ 402 uint16_t cbMaxExtendedState; 403 404 /** Supports MSRs. */ 405 uint32_t fMsr : 1; 406 /** Supports the page size extension (4/2 MB pages). */ 407 uint32_t fPse : 1; 408 /** Supports 36-bit page size extension (4 MB pages can map memory above 409 * 4GB). */ 410 uint32_t fPse36 : 1; 411 /** Supports physical address extension (PAE). */ 412 uint32_t fPae : 1; 413 /** Supports page-global extension (PGE). */ 414 uint32_t fPge : 1; 415 /** Page attribute table (PAT) support (page level cache control). */ 416 uint32_t fPat : 1; 417 /** Supports the FXSAVE and FXRSTOR instructions. */ 418 uint32_t fFxSaveRstor : 1; 419 /** Supports the XSAVE and XRSTOR instructions. */ 420 uint32_t fXSaveRstor : 1; 421 /** Supports the XSAVEOPT instruction. */ 422 uint32_t fXSaveOpt : 1; 423 /** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */ 424 uint32_t fOpSysXSaveRstor : 1; 425 /** Supports MMX. */ 426 uint32_t fMmx : 1; 427 /** Supports AMD extensions to MMX instructions. */ 428 uint32_t fAmdMmxExts : 1; 429 /** Supports SSE. */ 430 uint32_t fSse : 1; 431 /** Supports SSE2. */ 432 uint32_t fSse2 : 1; 433 /** Supports SSE3. */ 434 uint32_t fSse3 : 1; 435 /** Supports SSSE3. */ 436 uint32_t fSsse3 : 1; 437 /** Supports SSE4.1. */ 438 uint32_t fSse41 : 1; 439 /** Supports SSE4.2. */ 440 uint32_t fSse42 : 1; 441 /** Supports AVX. */ 442 uint32_t fAvx : 1; 443 /** Supports AVX2. */ 444 uint32_t fAvx2 : 1; 445 /** Supports AVX512 foundation. */ 446 uint32_t fAvx512Foundation : 1; 447 /** Supports RDTSC. */ 448 uint32_t fTsc : 1; 449 /** Intel SYSENTER/SYSEXIT support */ 450 uint32_t fSysEnter : 1; 451 /** Supports MTRR. */ 452 uint32_t fMtrr : 1; 453 /** First generation APIC. */ 454 uint32_t fApic : 1; 455 /** Second generation APIC. */ 456 uint32_t fX2Apic : 1; 457 /** Hypervisor present. */ 458 uint32_t fHypervisorPresent : 1; 459 /** MWAIT & MONITOR instructions supported. */ 460 uint32_t fMonitorMWait : 1; 461 /** MWAIT Extensions present. */ 462 uint32_t fMWaitExtensions : 1; 463 /** Supports CMPXCHG8B. */ 464 uint32_t fCmpXchg8b : 1; 465 /** Supports CMPXCHG16B in 64-bit mode. */ 466 uint32_t fCmpXchg16b : 1; 467 /** Supports CLFLUSH. */ 468 uint32_t fClFlush : 1; 469 /** Supports CLFLUSHOPT. */ 470 uint32_t fClFlushOpt : 1; 471 /** Supports IA32_PRED_CMD.IBPB. */ 472 uint32_t fIbpb : 1; 473 /** Supports IA32_SPEC_CTRL.IBRS. */ 474 uint32_t fIbrs : 1; 475 /** Supports IA32_SPEC_CTRL.STIBP. */ 476 uint32_t fStibp : 1; 477 /** Supports IA32_FLUSH_CMD. */ 478 uint32_t fFlushCmd : 1; 479 /** Supports IA32_ARCH_CAP. */ 480 uint32_t fArchCap : 1; 481 /** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */ 482 uint32_t fMdsClear : 1; 483 /** Supports PCID. */ 484 uint32_t fPcid : 1; 485 /** Supports INVPCID. */ 486 uint32_t fInvpcid : 1; 487 /** Supports read/write FSGSBASE instructions. */ 488 uint32_t fFsGsBase : 1; 489 /** Supports BMI1 instructions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, and TZCNT). */ 490 uint32_t fBmi1 : 1; 491 /** Supports BMI2 instructions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX, 492 * and SHLX). */ 493 uint32_t fBmi2 : 1; 494 /** Supports POPCNT instruction. */ 495 uint32_t fPopCnt : 1; 496 /** Supports RDRAND instruction. */ 497 uint32_t fRdRand : 1; 498 /** Supports RDSEED instruction. */ 499 uint32_t fRdSeed : 1; 500 /** Supports Hardware Lock Elision (HLE). */ 501 uint32_t fHle : 1; 502 /** Supports Restricted Transactional Memory (RTM - XBEGIN, XEND, XABORT). */ 503 uint32_t fRtm : 1; 504 /** Supports PCLMULQDQ instruction. */ 505 uint32_t fPclMul : 1; 506 /** Supports AES-NI (six AESxxx instructions). */ 507 uint32_t fAesNi : 1; 508 /** Support MOVBE instruction. */ 509 uint32_t fMovBe : 1; 510 /** Support SHA instructions. */ 511 uint32_t fSha : 1; 512 /** Support ADX instructions. */ 513 uint32_t fAdx : 1; 514 /** Supports FMA. */ 515 uint32_t fFma : 1; 516 /** Supports F16C. */ 517 uint32_t fF16c : 1; 518 519 /** Supports AMD 3DNow instructions. */ 520 uint32_t f3DNow : 1; 521 /** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */ 522 uint32_t f3DNowPrefetch : 1; 523 524 /** AMD64: Supports long mode. */ 525 uint32_t fLongMode : 1; 526 /** AMD64: SYSCALL/SYSRET support. */ 527 uint32_t fSysCall : 1; 528 /** AMD64: No-execute page table bit. */ 529 uint32_t fNoExecute : 1; 530 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */ 531 uint32_t fLahfSahf : 1; 532 /** AMD64: Supports RDTSCP. */ 533 uint32_t fRdTscP : 1; 534 /** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */ 535 uint32_t fMovCr8In32Bit : 1; 536 /** AMD64: Supports XOP (similar to VEX3/AVX). */ 537 uint32_t fXop : 1; 538 /** AMD64: Supports ABM, i.e. the LZCNT instruction. */ 539 uint32_t fAbm : 1; 540 /** AMD64: Supports TBM (BEXTR, BLCFILL, BLCI, BLCIC, BLCMSK, BLCS, 541 * BLSFILL, BLSIC, T1MSKC, and TZMSK). */ 542 uint32_t fTbm : 1; 543 544 /** Indicates that FPU instruction and data pointers may leak. 545 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer 546 * is only saved and restored if an exception is pending. */ 547 uint32_t fLeakyFxSR : 1; 548 549 /** Supports VEX instruction encoding (AVX, BMI, etc.). */ 550 uint32_t fVex : 1; 551 552 /** AMD64: Supports AMD SVM. */ 553 uint32_t fSvm : 1; 554 555 /** Support for Intel VMX. */ 556 uint32_t fVmx : 1; 557 558 /** Indicates that speculative execution control CPUID bits and MSRs are exposed. 559 * The details are different for Intel and AMD but both have similar 560 * functionality. */ 561 uint32_t fSpeculationControl : 1; 562 563 /** MSR_IA32_ARCH_CAPABILITIES: RDCL_NO (bit 0). 564 * @remarks Only safe use after CPUM ring-0 init! */ 565 uint32_t fArchRdclNo : 1; 566 /** MSR_IA32_ARCH_CAPABILITIES: IBRS_ALL (bit 1). 567 * @remarks Only safe use after CPUM ring-0 init! */ 568 uint32_t fArchIbrsAll : 1; 569 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 2). 570 * @remarks Only safe use after CPUM ring-0 init! */ 571 uint32_t fArchRsbOverride : 1; 572 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 3). 573 * @remarks Only safe use after CPUM ring-0 init! */ 574 uint32_t fArchVmmNeedNotFlushL1d : 1; 575 /** MSR_IA32_ARCH_CAPABILITIES: MDS_NO (bit 4). 576 * @remarks Only safe use after CPUM ring-0 init! */ 577 uint32_t fArchMdsNo : 1; 578 579 /** Alignment padding / reserved for future use (96 bits total, plus 12 bytes 580 * prior to the bit fields -> total of 24 bytes) */ 581 uint32_t fPadding0 : 19; 582 583 584 /** @name SVM 585 * @{ */ 586 /** SVM: Supports Nested-paging. */ 587 uint32_t fSvmNestedPaging : 1; 588 /** SVM: Support LBR (Last Branch Record) virtualization. */ 589 uint32_t fSvmLbrVirt : 1; 590 /** SVM: Supports SVM lock. */ 591 uint32_t fSvmSvmLock : 1; 592 /** SVM: Supports Next RIP save. */ 593 uint32_t fSvmNextRipSave : 1; 594 /** SVM: Supports TSC rate MSR. */ 595 uint32_t fSvmTscRateMsr : 1; 596 /** SVM: Supports VMCB clean bits. */ 597 uint32_t fSvmVmcbClean : 1; 598 /** SVM: Supports Flush-by-ASID. */ 599 uint32_t fSvmFlusbByAsid : 1; 600 /** SVM: Supports decode assist. */ 601 uint32_t fSvmDecodeAssists : 1; 602 /** SVM: Supports Pause filter. */ 603 uint32_t fSvmPauseFilter : 1; 604 /** SVM: Supports Pause filter threshold. */ 605 uint32_t fSvmPauseFilterThreshold : 1; 606 /** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */ 607 uint32_t fSvmAvic : 1; 608 /** SVM: Supports Virtualized VMSAVE/VMLOAD. */ 609 uint32_t fSvmVirtVmsaveVmload : 1; 610 /** SVM: Supports VGIF (Virtual Global Interrupt Flag). */ 611 uint32_t fSvmVGif : 1; 612 /** SVM: Supports GMET (Guest Mode Execute Trap Extension). */ 613 uint32_t fSvmGmet : 1; 614 /** SVM: Supports AVIC in x2APIC mode. */ 615 uint32_t fSvmX2Avic : 1; 616 /** SVM: Supports SSSCheck (SVM Supervisor Shadow Stack). */ 617 uint32_t fSvmSSSCheck : 1; 618 /** SVM: Supports SPEC_CTRL virtualization. */ 619 uint32_t fSvmSpecCtrl : 1; 620 /** SVM: Supports Read-Only Guest Page Table feature. */ 621 uint32_t fSvmRoGpt : 1; 622 /** SVM: Supports HOST_MCE_OVERRIDE. */ 623 uint32_t fSvmHostMceOverride : 1; 624 /** SVM: Supports TlbiCtl (INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept). */ 625 uint32_t fSvmTlbiCtl : 1; 626 /** SVM: Supports NMI virtualization. */ 627 uint32_t fSvmVNmi : 1; 628 /** SVM: Supports IBS virtualizaiton. */ 629 uint32_t fSvmIbsVirt : 1; 630 /** SVM: Supports Extended LVT AVIC access changes. */ 631 uint32_t fSvmExtLvtAvicAccessChg : 1; 632 /** SVM: Supports Guest VMCB address check. */ 633 uint32_t fSvmNstVirtVmcbAddrChk : 1; 634 /** SVM: Supports Bus Lock Threshold. */ 635 uint32_t fSvmBusLockThreshold : 1; 636 /** SVM: Padding / reserved for future features (64 bits total w/ max ASID). */ 637 uint32_t fSvmPadding0 : 7; 638 /** SVM: Maximum supported ASID. */ 639 uint32_t uSvmMaxAsid; 640 /** @} */ 641 642 643 /** VMX: Maximum physical address width. */ 644 uint32_t cVmxMaxPhysAddrWidth : 8; 645 646 /** @name VMX basic controls. 647 * @{ */ 648 /** VMX: Supports INS/OUTS VM-exit instruction info. */ 649 uint32_t fVmxInsOutInfo : 1; 650 /** @} */ 651 652 /** @name VMX Pin-based controls. 653 * @{ */ 654 /** VMX: Supports external interrupt VM-exit. */ 655 uint32_t fVmxExtIntExit : 1; 656 /** VMX: Supports NMI VM-exit. */ 657 uint32_t fVmxNmiExit : 1; 658 /** VMX: Supports Virtual NMIs. */ 659 uint32_t fVmxVirtNmi : 1; 660 /** VMX: Supports preemption timer. */ 661 uint32_t fVmxPreemptTimer : 1; 662 /** VMX: Supports posted interrupts. */ 663 uint32_t fVmxPostedInt : 1; 664 /** @} */ 665 666 /** @name VMX Processor-based controls. 667 * @{ */ 668 /** VMX: Supports Interrupt-window exiting. */ 669 uint32_t fVmxIntWindowExit : 1; 670 /** VMX: Supports TSC offsetting. */ 671 uint32_t fVmxTscOffsetting : 1; 672 /** VMX: Supports HLT exiting. */ 673 uint32_t fVmxHltExit : 1; 674 /** VMX: Supports INVLPG exiting. */ 675 uint32_t fVmxInvlpgExit : 1; 676 /** VMX: Supports MWAIT exiting. */ 677 uint32_t fVmxMwaitExit : 1; 678 /** VMX: Supports RDPMC exiting. */ 679 uint32_t fVmxRdpmcExit : 1; 680 /** VMX: Supports RDTSC exiting. */ 681 uint32_t fVmxRdtscExit : 1; 682 /** VMX: Supports CR3-load exiting. */ 683 uint32_t fVmxCr3LoadExit : 1; 684 /** VMX: Supports CR3-store exiting. */ 685 uint32_t fVmxCr3StoreExit : 1; 686 /** VMX: Supports tertiary processor-based VM-execution controls. */ 687 uint32_t fVmxTertiaryExecCtls : 1; 688 /** VMX: Supports CR8-load exiting. */ 689 uint32_t fVmxCr8LoadExit : 1; 690 /** VMX: Supports CR8-store exiting. */ 691 uint32_t fVmxCr8StoreExit : 1; 692 /** VMX: Supports TPR shadow. */ 693 uint32_t fVmxUseTprShadow : 1; 694 /** VMX: Supports NMI-window exiting. */ 695 uint32_t fVmxNmiWindowExit : 1; 696 /** VMX: Supports Mov-DRx exiting. */ 697 uint32_t fVmxMovDRxExit : 1; 698 /** VMX: Supports Unconditional I/O exiting. */ 699 uint32_t fVmxUncondIoExit : 1; 700 /** VMX: Supportgs I/O bitmaps. */ 701 uint32_t fVmxUseIoBitmaps : 1; 702 /** VMX: Supports Monitor Trap Flag. */ 703 uint32_t fVmxMonitorTrapFlag : 1; 704 /** VMX: Supports MSR bitmap. */ 705 uint32_t fVmxUseMsrBitmaps : 1; 706 /** VMX: Supports MONITOR exiting. */ 707 uint32_t fVmxMonitorExit : 1; 708 /** VMX: Supports PAUSE exiting. */ 709 uint32_t fVmxPauseExit : 1; 710 /** VMX: Supports secondary processor-based VM-execution controls. */ 711 uint32_t fVmxSecondaryExecCtls : 1; 712 /** @} */ 713 714 /** @name VMX Secondary processor-based controls. 715 * @{ */ 716 /** VMX: Supports virtualize-APIC access. */ 717 uint32_t fVmxVirtApicAccess : 1; 718 /** VMX: Supports EPT (Extended Page Tables). */ 719 uint32_t fVmxEpt : 1; 720 /** VMX: Supports descriptor-table exiting. */ 721 uint32_t fVmxDescTableExit : 1; 722 /** VMX: Supports RDTSCP. */ 723 uint32_t fVmxRdtscp : 1; 724 /** VMX: Supports virtualize-x2APIC mode. */ 725 uint32_t fVmxVirtX2ApicMode : 1; 726 /** VMX: Supports VPID. */ 727 uint32_t fVmxVpid : 1; 728 /** VMX: Supports WBIND exiting. */ 729 uint32_t fVmxWbinvdExit : 1; 730 /** VMX: Supports Unrestricted guest. */ 731 uint32_t fVmxUnrestrictedGuest : 1; 732 /** VMX: Supports APIC-register virtualization. */ 733 uint32_t fVmxApicRegVirt : 1; 734 /** VMX: Supports virtual-interrupt delivery. */ 735 uint32_t fVmxVirtIntDelivery : 1; 736 /** VMX: Supports Pause-loop exiting. */ 737 uint32_t fVmxPauseLoopExit : 1; 738 /** VMX: Supports RDRAND exiting. */ 739 uint32_t fVmxRdrandExit : 1; 740 /** VMX: Supports INVPCID. */ 741 uint32_t fVmxInvpcid : 1; 742 /** VMX: Supports VM functions. */ 743 uint32_t fVmxVmFunc : 1; 744 /** VMX: Supports VMCS shadowing. */ 745 uint32_t fVmxVmcsShadowing : 1; 746 /** VMX: Supports RDSEED exiting. */ 747 uint32_t fVmxRdseedExit : 1; 748 /** VMX: Supports PML. */ 749 uint32_t fVmxPml : 1; 750 /** VMX: Supports EPT-violations \#VE. */ 751 uint32_t fVmxEptXcptVe : 1; 752 /** VMX: Supports conceal VMX from PT. */ 753 uint32_t fVmxConcealVmxFromPt : 1; 754 /** VMX: Supports XSAVES/XRSTORS. */ 755 uint32_t fVmxXsavesXrstors : 1; 756 /** VMX: Supports PASID translation. */ 757 uint32_t fVmxPasidTranslate : 1; 758 /** VMX: Supports mode-based execute control for EPT. */ 759 uint32_t fVmxModeBasedExecuteEpt : 1; 760 /** VMX: Supports sub-page write permissions for EPT. */ 761 uint32_t fVmxSppEpt : 1; 762 /** VMX: Supports Intel PT to output guest-physical addresses for EPT. */ 763 uint32_t fVmxPtEpt : 1; 764 /** VMX: Supports TSC scaling. */ 765 uint32_t fVmxUseTscScaling : 1; 766 /** VMX: Supports TPAUSE, UMONITOR, or UMWAIT. */ 767 uint32_t fVmxUserWaitPause : 1; 768 /** VMX: Supports PCONFIG. */ 769 uint32_t fVmxPconfig : 1; 770 /** VMX: Supports enclave (ENCLV) exiting. */ 771 uint32_t fVmxEnclvExit : 1; 772 /** VMX: Supports VMM bus-lock detection. */ 773 uint32_t fVmxBusLockDetect : 1; 774 /** VMX: Supports instruction timeout. */ 775 uint32_t fVmxInstrTimeout : 1; 776 /** @} */ 777 778 /** @name VMX Tertiary processor-based controls. 779 * @{ */ 780 /** VMX: Supports LOADIWKEY exiting. */ 781 uint32_t fVmxLoadIwKeyExit : 1; 782 /** VMX: Supports hypervisor-managed linear address translation (HLAT). */ 783 uint32_t fVmxHlat : 1; 784 /** VMX: Supports EPT paging-write control. */ 785 uint32_t fVmxEptPagingWrite : 1; 786 /** VMX: Supports Guest-paging verification. */ 787 uint32_t fVmxGstPagingVerify : 1; 788 /** VMX: Supports IPI virtualization. */ 789 uint32_t fVmxIpiVirt : 1; 790 /** VMX: Supports virtualize IA32_SPEC_CTRL. */ 791 uint32_t fVmxVirtSpecCtrl : 1; 792 /** @} */ 793 794 /** @name VMX VM-entry controls. 795 * @{ */ 796 /** VMX: Supports load-debug controls on VM-entry. */ 797 uint32_t fVmxEntryLoadDebugCtls : 1; 798 /** VMX: Supports IA32e mode guest. */ 799 uint32_t fVmxIa32eModeGuest : 1; 800 /** VMX: Supports load guest EFER MSR on VM-entry. */ 801 uint32_t fVmxEntryLoadEferMsr : 1; 802 /** VMX: Supports load guest PAT MSR on VM-entry. */ 803 uint32_t fVmxEntryLoadPatMsr : 1; 804 /** @} */ 805 806 /** @name VMX VM-exit controls. 807 * @{ */ 808 /** VMX: Supports save debug controls on VM-exit. */ 809 uint32_t fVmxExitSaveDebugCtls : 1; 810 /** VMX: Supports host-address space size. */ 811 uint32_t fVmxHostAddrSpaceSize : 1; 812 /** VMX: Supports acknowledge external interrupt on VM-exit. */ 813 uint32_t fVmxExitAckExtInt : 1; 814 /** VMX: Supports save guest PAT MSR on VM-exit. */ 815 uint32_t fVmxExitSavePatMsr : 1; 816 /** VMX: Supports load hsot PAT MSR on VM-exit. */ 817 uint32_t fVmxExitLoadPatMsr : 1; 818 /** VMX: Supports save guest EFER MSR on VM-exit. */ 819 uint32_t fVmxExitSaveEferMsr : 1; 820 /** VMX: Supports load host EFER MSR on VM-exit. */ 821 uint32_t fVmxExitLoadEferMsr : 1; 822 /** VMX: Supports save VMX preemption timer on VM-exit. */ 823 uint32_t fVmxSavePreemptTimer : 1; 824 /** VMX: Supports secondary VM-exit controls. */ 825 uint32_t fVmxSecondaryExitCtls : 1; 826 /** @} */ 827 828 /** @name VMX Miscellaneous data. 829 * @{ */ 830 /** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */ 831 uint32_t fVmxExitSaveEferLma : 1; 832 /** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */ 833 uint32_t fVmxPt : 1; 834 /** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise 835 * VMWRITE cannot modify read-only VM-exit information fields. */ 836 uint32_t fVmxVmwriteAll : 1; 837 /** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero 838 * length instructions. */ 839 uint32_t fVmxEntryInjectSoftInt : 1; 840 /** @} */ 841 842 /** VMX: Padding / reserved for future features. */ 843 uint32_t fVmxPadding0 : 7; 844 /** VMX: Padding / reserved for future, making it a total of 128 bits. */ 845 uint32_t fVmxPadding1; 846 } CPUMFEATURESX86; 847 #ifndef VBOX_FOR_DTRACE_LIB 848 AssertCompileSize(CPUMFEATURESX86, 48); 849 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmCpuVendor, CPUMFEATURESX86, enmCpuVendor); 850 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, uFamily, CPUMFEATURESX86, uFamily); 851 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, uModel, CPUMFEATURESX86, uModel); 852 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, uStepping, CPUMFEATURESX86, uStepping); 853 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmMicroarch, CPUMFEATURESX86, enmMicroarch); 854 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxPhysAddrWidth, CPUMFEATURESX86, cMaxPhysAddrWidth); 855 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxLinearAddrWidth, CPUMFEATURESX86, cMaxLinearAddrWidth); 856 #endif 857 858 /** 859 * CPU features and quirks for ARMv8. 860 * 861 * This is mostly exploded CPU feature register info. 862 */ 863 typedef struct CPUMFEATURESARMV8 864 { 865 /** The CPU vendor (CPUMCPUVENDOR). */ 866 uint8_t enmCpuVendor; 867 /** The CPU family. */ 868 uint8_t uFamily; 869 /** The CPU model. */ 870 uint8_t uModel; 871 /** The CPU stepping. */ 872 uint8_t uStepping; 873 /** The microarchitecture. */ 874 #ifndef VBOX_FOR_DTRACE_LIB 875 CPUMMICROARCH enmMicroarch; 876 #else 877 uint32_t enmMicroarch; 878 #endif 879 /** The maximum physical address width of the CPU. */ 880 uint8_t cMaxPhysAddrWidth; 881 /** The maximum linear address width of the CPU. */ 882 uint8_t cMaxLinearAddrWidth; 883 uint16_t uPadding; 884 885 /** @name Granule sizes supported. 886 * @{ */ 887 /** 4KiB translation granule size supported. */ 888 uint32_t fTGran4K : 1; 889 /** 16KiB translation granule size supported. */ 890 uint32_t fTGran16K : 1; 891 /** 64KiB translation granule size supported. */ 892 uint32_t fTGran64K : 1; 893 /** @} */ 894 895 /** @name pre-2020 Architecture Extensions. 896 * @{ */ 897 /** Supports Advanced SIMD Extension (FEAT_AdvSIMD). */ 898 uint32_t fAdvSimd : 1; 899 /** Supports Advanced SIMD AES instructions (FEAT_AES). */ 900 uint32_t fAes : 1; 901 /** Supports Advanced SIMD PMULL instructions (FEAT_PMULL). */ 902 uint32_t fPmull : 1; 903 /** Supports CP15Disable2 (FEAT_CP15DISABLE2). */ 904 uint32_t fCp15Disable2 : 1; 905 /** Supports Cache Speculation Variant 2 (FEAT_CSV2). */ 906 uint32_t fCsv2 : 1; 907 /** Supports Cache Speculation Variant 2, version 1.1 (FEAT_CSV2_1p1). */ 908 uint32_t fCsv21p1 : 1; 909 /** Supports Cache Speculation Variant 2, version 1.2 (FEAT_CSV2_1p2). */ 910 uint32_t fCsv21p2 : 1; 911 /** Supports Cache Speculation Variant 3 (FEAT_CSV3). */ 912 uint32_t fCsv3 : 1; 913 /** Supports Data Gahtering Hint (FEAT_DGH). */ 914 uint32_t fDgh : 1; 915 /** Supports Double Lock (FEAT_DoubleLock). */ 916 uint32_t fDoubleLock : 1; 917 /** Supports Enhanced Translation Synchronization (FEAT_ETS2). */ 918 uint32_t fEts2 : 1; 919 /** Supports Floating Point Extensions (FEAT_FP). */ 920 uint32_t fFp : 1; 921 /** Supports IVIPT Extensions (FEAT_IVIPT). */ 922 uint32_t fIvipt : 1; 923 /** Supports PC Sample-based Profiling Extension (FEAT_PCSRv8). */ 924 uint32_t fPcsrV8 : 1; 925 /** Supports Speculation Restrictions instructions (FEAT_SPECRES). */ 926 uint32_t fSpecres : 1; 927 /** Supports Reliability, Availability, and Serviceability (RAS) Extension (FEAT_RAS). */ 928 uint32_t fRas : 1; 929 /** Supports Speculation Barrier (FEAT_SB). */ 930 uint32_t fSb : 1; 931 /** Supports Advanced SIMD SHA1 instructions (FEAT_SHA1). */ 932 uint32_t fSha1 : 1; 933 /** Supports Advanced SIMD SHA256 instructions (FEAT_SHA256). */ 934 uint32_t fSha256 : 1; 935 /** Supports Speculation Store Bypass Safe (FEAT_SSBS). */ 936 uint32_t fSsbs : 1; 937 /** Supports MRS and MSR instructions for Speculation Store Bypass Safe version 2 (FEAT_SSBS2). */ 938 uint32_t fSsbs2 : 1; 939 /** Supports CRC32 instructions (FEAT_CRC32). */ 940 uint32_t fCrc32 : 1; 941 /** Supports Intermediate chacing of trnslation table walks (FEAT_nTLBPA). */ 942 uint32_t fNTlbpa : 1; 943 /** Supports debug with VHE (FEAT_Debugv8p1). */ 944 uint32_t fDebugV8p1 : 1; 945 /** Supports Hierarchical permission disables in translation tables (FEAT_HPDS). */ 946 uint32_t fHpds : 1; 947 /** Supports Limited ordering regions (FEAT_LOR). */ 948 uint32_t fLor : 1; 949 /** Supports Lare Systems Extensons (FEAT_LSE). */ 950 uint32_t fLse : 1; 951 /** Supports Privileged access never (FEAT_PAN). */ 952 uint32_t fPan : 1; 953 /** Supports Armv8.1 PMU extensions (FEAT_PMUv3p1). */ 954 uint32_t fPmuV3p1 : 1; 955 /** Supports Advanced SIMD rouding double multiply accumulate instructions (FEAT_RDM). */ 956 uint32_t fRdm : 1; 957 /** Supports hardware management of the Access flag and dirty state (FEAT_HAFDBS). */ 958 uint32_t fHafdbs : 1; 959 /** Supports Virtualization Host Extensions (FEAT_VHE). */ 960 uint32_t fVhe : 1; 961 /** Supports 16-bit VMID (FEAT_VMID16). */ 962 uint32_t fVmid16 : 1; 963 /** Supports AArch32 BFloat16 instructions (FEAT_AA32BF16). */ 964 uint32_t fAa32Bf16 : 1; 965 /** Supports AArch32 Hierarchical permission disables (FEAT_AA32HPD). */ 966 uint32_t fAa32Hpd : 1; 967 /** Supports AArch32 Int8 matrix multiplication instructions (FEAT_AA32I8MM). */ 968 uint32_t fAa32I8mm : 1; 969 /** Supports AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN (FEAT_PAN2). */ 970 uint32_t fPan2 : 1; 971 /** Supports AArch64 BFloat16 instructions (FEAT_BF16). */ 972 uint32_t fBf16 : 1; 973 /** Supports DC CVADP instruction (FEAT_DPB2). */ 974 uint32_t fDpb2 : 1; 975 /** Supports DC VAP instruction (FEAT_DPB). */ 976 uint32_t fDpb : 1; 977 /** Supports Debug v8.2 (FEAT_Debugv8p2). */ 978 uint32_t fDebugV8p2 : 1; 979 /** Supports Advanced SIMD dot product instructions (FEAT_DotProd). */ 980 uint32_t fDotProd : 1; 981 /** Supports Enhanced Virtualization Traps (FEAT_EVT). */ 982 uint32_t fEvt : 1; 983 /** Supports Single precision Matrix Multiplication (FEAT_F32MM). */ 984 uint32_t fF32mm : 1; 985 /** Supports Double precision Matrix Multiplication (FEAT_F64MM). */ 986 uint32_t fF64mm : 1; 987 /** Supports Floating-point half precision multiplication instructions (FEAT_FHM). */ 988 uint32_t fFhm : 1; 989 /** Supports Half-precision floating point data processing (FEAT_FP16). */ 990 uint32_t fFp16 : 1; 991 /** Supports AArch64 Int8 matrix multiplication instructions (FEAT_I8MM). */ 992 uint32_t fI8mm : 1; 993 /** Supports Implicit Error Synchronization event (FEAT_IESB). */ 994 uint32_t fIesb : 1; 995 /** Supports Large PA and IPA support (FEAT_LPA). */ 996 uint32_t fLpa : 1; 997 /** Supports AArch32 Load/Store Multiple instructions atomicity and ordering controls (FEAT_LSMAOC). */ 998 uint32_t fLsmaoc : 1; 999 /** Supports Large VA support (FEAT_LVA). */ 1000 uint32_t fLva : 1; 1001 /** Supports Memory Partitioning and Monitoring Extension (FEAT_MPAM). */ 1002 uint32_t fMpam : 1; 1003 /** Supports PC Sample-based Profiling Extension, version 8.2 (FEAT_PCSRv8p2). */ 1004 uint32_t fPcsrV8p2 : 1; 1005 /** Supports Advanced SIMD SHA3 instructions (FEAT_SHA3). */ 1006 uint32_t fSha3 : 1; 1007 /** Supports Advanced SIMD SHA512 instructions (FEAT_SHA512). */ 1008 uint32_t fSha512 : 1; 1009 /** Supports Advanced SIMD SM3 instructions (FEAT_SM3). */ 1010 uint32_t fSm3 : 1; 1011 /** Supports Advanced SIMD SM4 instructions (FEAT_SM4). */ 1012 uint32_t fSm4 : 1; 1013 /** Supports Statistical Profiling Extension (FEAT_SPE). */ 1014 uint32_t fSpe : 1; 1015 /** Supports Scalable Vector Extension (FEAT_SVE). */ 1016 uint32_t fSve : 1; 1017 /** Supports Translation Table Common not private translations (FEAT_TTCNP). */ 1018 uint32_t fTtcnp : 1; 1019 /** Supports Hierarchical permission disables, version 2 (FEAT_HPDS2). */ 1020 uint32_t fHpds2 : 1; 1021 /** Supports Translation table stage 2 Unprivileged Execute-never (FEAT_XNX). */ 1022 uint32_t fXnx : 1; 1023 /** Supports Unprivileged Access Override control (FEAT_UAO). */ 1024 uint32_t fUao : 1; 1025 /** Supports VMID-aware PIPT instruction cache (FEAT_VPIPT). */ 1026 uint32_t fVpipt : 1; 1027 /** Supports Extended cache index (FEAT_CCIDX). */ 1028 uint32_t fCcidx : 1; 1029 /** Supports Floating-point complex number instructions (FEAT_FCMA). */ 1030 uint32_t fFcma : 1; 1031 /** Supports Debug over Powerdown (FEAT_DoPD). */ 1032 uint32_t fDopd : 1; 1033 /** Supports Enhanced pointer authentication (FEAT_EPAC). */ 1034 uint32_t fEpac : 1; 1035 /** Supports Faulting on AUT* instructions (FEAT_FPAC). */ 1036 uint32_t fFpac : 1; 1037 /** Supports Faulting on combined pointer euthentication instructions (FEAT_FPACCOMBINE). */ 1038 uint32_t fFpacCombine : 1; 1039 /** Supports JavaScript conversion instructions (FEAT_JSCVT). */ 1040 uint32_t fJscvt : 1; 1041 /** Supports Load-Acquire RCpc instructions (FEAT_LRCPC). */ 1042 uint32_t fLrcpc : 1; 1043 /** Supports Nexted Virtualization (FEAT_NV). */ 1044 uint32_t fNv : 1; 1045 /** Supports QARMA5 pointer authentication algorithm (FEAT_PACQARMA5). */ 1046 uint32_t fPacQarma5 : 1; 1047 /** Supports implementation defined pointer authentication algorithm (FEAT_PACIMP). */ 1048 uint32_t fPacImp : 1; 1049 /** Supports Pointer authentication (FEAT_PAuth). */ 1050 uint32_t fPAuth : 1; 1051 /** Supports Enhancements to pointer authentication (FEAT_PAuth2). */ 1052 uint32_t fPAuth2 : 1; 1053 /** Supports Statistical Profiling Extensions version 1.1 (FEAT_SPEv1p1). */ 1054 uint32_t fSpeV1p1 : 1; 1055 /** Supports Activity Monitor Extension, version 1 (FEAT_AMUv1). */ 1056 uint32_t fAmuV1 : 1; 1057 /** Supports Generic Counter Scaling (FEAT_CNTSC). */ 1058 uint32_t fCntsc : 1; 1059 /** Supports Debug v8.4 (FEAT_Debugv8p4). */ 1060 uint32_t fDebugV8p4 : 1; 1061 /** Supports Double Fault Extension (FEAT_DoubleFault). */ 1062 uint32_t fDoubleFault : 1; 1063 /** Supports Data Independent Timing instructions (FEAT_DIT). */ 1064 uint32_t fDit : 1; 1065 /** Supports Condition flag manipulation isntructions (FEAT_FlagM). */ 1066 uint32_t fFlagM : 1; 1067 /** Supports ID space trap handling (FEAT_IDST). */ 1068 uint32_t fIdst : 1; 1069 /** Supports Load-Acquire RCpc instructions version 2 (FEAT_LRCPC2). */ 1070 uint32_t fLrcpc2 : 1; 1071 /** Supports Large Sytem Extensions version 2 (FEAT_LSE2). */ 1072 uint32_t fLse2 : 1; 1073 /** Supports Enhanced nested virtualization support (FEAT_NV2). */ 1074 uint32_t fNv2 : 1; 1075 /** Supports Armv8.4 PMU Extensions (FEAT_PMUv3p4). */ 1076 uint32_t fPmuV3p4 : 1; 1077 /** Supports RAS Extension v1.1 (FEAT_RASv1p1). */ 1078 uint32_t fRasV1p1 : 1; 1079 /** Supports RAS Extension v1.1 System Architecture (FEAT_RASSAv1p1). */ 1080 uint32_t fRassaV1p1 : 1; 1081 /** Supports Stage 2 forced Write-Back (FEAT_S2FWB). */ 1082 uint32_t fS2Fwb : 1; 1083 /** Supports Secure El2 (FEAT_SEL2). */ 1084 uint32_t fSecEl2 : 1; 1085 /** Supports TLB invalidate instructions on Outer Shareable domain (FEAT_TLBIOS). */ 1086 uint32_t fTlbios : 1; 1087 /** Supports TLB invalidate range instructions (FEAT_TLBIRANGE). */ 1088 uint32_t fTlbirange : 1; 1089 /** Supports Self-hosted Trace Extensions (FEAT_TRF). */ 1090 uint32_t fTrf : 1; 1091 /** Supports Translation Table Level (FEAT_TTL). */ 1092 uint32_t fTtl : 1; 1093 /** Supports Translation table break-before-make levels (FEAT_BBM). */ 1094 uint32_t fBbm : 1; 1095 /** Supports Small translation tables (FEAT_TTST). */ 1096 uint32_t fTtst : 1; 1097 /** Supports Branch Target Identification (FEAT_BTI). */ 1098 uint32_t fBti : 1; 1099 /** Supports Enhancements to flag manipulation instructions (FEAT_FlagM2). */ 1100 uint32_t fFlagM2 : 1; 1101 /** Supports Context synchronization and exception handling (FEAT_ExS). */ 1102 uint32_t fExs : 1; 1103 /** Supports Preenting EL0 access to halves of address maps (FEAT_E0PD). */ 1104 uint32_t fE0Pd : 1; 1105 /** Supports Floating-point to integer instructions (FEAT_FRINTTS). */ 1106 uint32_t fFrintts : 1; 1107 /** Supports Guest translation granule size (FEAT_GTG). */ 1108 uint32_t fGtg : 1; 1109 /** Supports Instruction-only Memory Tagging Extension (FEAT_MTE). */ 1110 uint32_t fMte : 1; 1111 /** Supports memory Tagging Extension version 2 (FEAT_MTE2). */ 1112 uint32_t fMte2 : 1; 1113 /** Supports Armv8.5 PMU Extensions (FEAT_PMUv3p5). */ 1114 uint32_t fPmuV3p5 : 1; 1115 /** Supports Random number generator (FEAT_RNG). */ 1116 uint32_t fRng : 1; 1117 /** Supports AMU Extensions version 1.1 (FEAT_AMUv1p1). */ 1118 uint32_t fAmuV1p1 : 1; 1119 /** Supports Enhanced Counter Virtualization (FEAT_ECV). */ 1120 uint32_t fEcv : 1; 1121 /** Supports Fine Grain Traps (FEAT_FGT). */ 1122 uint32_t fFgt : 1; 1123 /** Supports Memory Partitioning and Monitoring version 0.1 (FEAT_MPAMv0p1). */ 1124 uint32_t fMpamV0p1 : 1; 1125 /** Supports Memory Partitioning and Monitoring version 1.1 (FEAT_MPAMv1p1). */ 1126 uint32_t fMpamV1p1 : 1; 1127 /** Supports Multi-threaded PMU Extensions (FEAT_MTPMU). */ 1128 uint32_t fMtPmu : 1; 1129 /** Supports Delayed Trapping of WFE (FEAT_TWED). */ 1130 uint32_t fTwed : 1; 1131 /** Supports Embbedded Trace Macrocell version 4 (FEAT_ETMv4). */ 1132 uint32_t fEtmV4 : 1; 1133 /** Supports Embbedded Trace Macrocell version 4.1 (FEAT_ETMv4p1). */ 1134 uint32_t fEtmV4p1 : 1; 1135 /** Supports Embbedded Trace Macrocell version 4.2 (FEAT_ETMv4p2). */ 1136 uint32_t fEtmV4p2 : 1; 1137 /** Supports Embbedded Trace Macrocell version 4.3 (FEAT_ETMv4p3). */ 1138 uint32_t fEtmV4p3 : 1; 1139 /** Supports Embbedded Trace Macrocell version 4.4 (FEAT_ETMv4p4). */ 1140 uint32_t fEtmV4p4 : 1; 1141 /** Supports Embbedded Trace Macrocell version 4.5 (FEAT_ETMv4p5). */ 1142 uint32_t fEtmV4p5 : 1; 1143 /** Supports Embbedded Trace Macrocell version 4.6 (FEAT_ETMv4p6). */ 1144 uint32_t fEtmV4p6 : 1; 1145 /** Supports Generic Interrupt Controller version 3 (FEAT_GICv3). */ 1146 uint32_t fGicV3 : 1; 1147 /** Supports Generic Interrupt Controller version 3.1 (FEAT_GICv3p1). */ 1148 uint32_t fGicV3p1 : 1; 1149 /** Supports Trapping Non-secure EL1 writes to ICV_DIR (FEAT_GICv3_TDIR). */ 1150 uint32_t fGicV3Tdir : 1; 1151 /** Supports Generic Interrupt Controller version 4 (FEAT_GICv4). */ 1152 uint32_t fGicV4 : 1; 1153 /** Supports Generic Interrupt Controller version 4.1 (FEAT_GICv4p1). */ 1154 uint32_t fGicV4p1 : 1; 1155 /** Supports PMU extension, version 3 (FEAT_PMUv3). */ 1156 uint32_t fPmuV3 : 1; 1157 /** Supports Embedded Trace Extension (FEAT_ETE). */ 1158 uint32_t fEte : 1; 1159 /** Supports Embedded Trace Extension, version 1.1 (FEAT_ETEv1p1). */ 1160 uint32_t fEteV1p1 : 1; 1161 /** Supports Embedded Trace Extension, version 1.2 (FEAT_ETEv1p2). */ 1162 uint32_t fEteV1p2 : 1; 1163 /** Supports Scalable Vector Extension version 2 (FEAT_SVE2). */ 1164 uint32_t fSve2 : 1; 1165 /** Supports Scalable Vector AES instructions (FEAT_SVE_AES). */ 1166 uint32_t fSveAes : 1; 1167 /** Supports Scalable Vector PMULL instructions (FEAT_SVE_PMULL128). */ 1168 uint32_t fSvePmull128 : 1; 1169 /** Supports Scalable Vector Bit Permutes instructions (FEAT_SVE_BitPerm). */ 1170 uint32_t fSveBitPerm : 1; 1171 /** Supports Scalable Vector SHA3 instructions (FEAT_SVE_SHA3). */ 1172 uint32_t fSveSha3 : 1; 1173 /** Supports Scalable Vector SM4 instructions (FEAT_SVE_SM4). */ 1174 uint32_t fSveSm4 : 1; 1175 /** Supports Transactional Memory Extension (FEAT_TME). */ 1176 uint32_t fTme : 1; 1177 /** Supports Trace Buffer Extension (FEAT_TRBE). */ 1178 uint32_t fTrbe : 1; 1179 /** Supports Scalable Matrix Extension (FEAT_SME). */ 1180 uint32_t fSme : 1; 1181 /** @} */ 1182 1183 /** @name 2020 Architecture Extensions. 1184 * @{ */ 1185 /** Supports Alternate floating-point behavior (FEAT_AFP). */ 1186 uint32_t fAfp : 1; 1187 /** Supports HCRX_EL2 register (FEAT_HCX). */ 1188 uint32_t fHcx : 1; 1189 /** Supports Larger phsical address for 4KiB and 16KiB translation granules (FEAT_LPA2). */ 1190 uint32_t fLpa2 : 1; 1191 /** Supports 64 byte loads and stores without return (FEAT_LS64). */ 1192 uint32_t fLs64 : 1; 1193 /** Supports 64 byte stores with return (FEAT_LS64_V). */ 1194 uint32_t fLs64V : 1; 1195 /** Supports 64 byte EL0 stores with return (FEAT_LS64_ACCDATA). */ 1196 uint32_t fLs64Accdata : 1; 1197 /** Supports MTE Asymmetric Fault Handling (FEAT_MTE3). */ 1198 uint32_t fMte3 : 1; 1199 /** Supports SCTLR_ELx.EPAN (FEAT_PAN3). */ 1200 uint32_t fPan3 : 1; 1201 /** Supports Armv8.7 PMU extensions (FEAT_PMUv3p7). */ 1202 uint32_t fPmuV3p7 : 1; 1203 /** Supports Increased precision of Reciprocal Extimate and Reciprocal Square Root Estimate (FEAT_RPRES). */ 1204 uint32_t fRpres : 1; 1205 /** Supports Realm Management Extension (FEAT_RME). */ 1206 uint32_t fRme : 1; 1207 /** Supports Full A64 instruction set support in Streaming SVE mode (FEAT_SME_FA64). */ 1208 uint32_t fSmeFA64 : 1; 1209 /** Supports Double-precision floating-point outer product instructions (FEAT_SME_F64F64). */ 1210 uint32_t fSmeF64F64 : 1; 1211 /** Supports 16-bit to 64-bit integer widening outer product instructions (FEAT_SME_I16I64). */ 1212 uint32_t fSmeI16I64 : 1; 1213 /** Supports Statistical Profiling Extensions version 1.2 (FEAT_SPEv1p2). */ 1214 uint32_t fSpeV1p2 : 1; 1215 /** Supports AArch64 Extended BFloat16 instructions (FEAT_EBF16). */ 1216 uint32_t fEbf16 : 1; 1217 /** Supports WFE and WFI instructions with timeout (FEAT_WFxT). */ 1218 uint32_t fWfxt : 1; 1219 /** Supports XS attribute (FEAT_XS). */ 1220 uint32_t fXs : 1; 1221 /** Supports branch Record Buffer Extension (FEAT_BRBE). */ 1222 uint32_t fBrbe : 1; 1223 /** @} */ 1224 1225 /** @name 2021 Architecture Extensions. 1226 * @{ */ 1227 /** Supports Control for cache maintenance permission (FEAT_CMOW). */ 1228 uint32_t fCmow : 1; 1229 /** Supports PAC algorithm enhancement (FEAT_CONSTPACFIELD). */ 1230 uint32_t fConstPacField : 1; 1231 /** Supports Debug v8.8 (FEAT_Debugv8p8). */ 1232 uint32_t fDebugV8p8 : 1; 1233 /** Supports Hinted conditional branches (FEAT_HBC). */ 1234 uint32_t fHbc : 1; 1235 /** Supports Setting of MDCR_EL2.HPMN to zero (FEAT_HPMN0). */ 1236 uint32_t fHpmn0 : 1; 1237 /** Supports Non-Maskable Interrupts (FEAT_NMI). */ 1238 uint32_t fNmi : 1; 1239 /** Supports GIC Non-Maskable Interrupts (FEAT_GICv3_NMI). */ 1240 uint32_t fGicV3Nmi : 1; 1241 /** Supports Standardization of memory operations (FEAT_MOPS). */ 1242 uint32_t fMops : 1; 1243 /** Supports Pointer authentication - QARMA3 algorithm (FEAT_PACQARMA3). */ 1244 uint32_t fPacQarma3 : 1; 1245 /** Supports Event counting threshold (FEAT_PMUv3_TH). */ 1246 uint32_t fPmuV3Th : 1; 1247 /** Supports Armv8.8 PMU extensions (FEAT_PMUv3p8). */ 1248 uint32_t fPmuV3p8 : 1; 1249 /** Supports 64-bit external interface to the Performance Monitors (FEAT_PMUv3_EXT64). */ 1250 uint32_t fPmuV3Ext64 : 1; 1251 /** Supports 32-bit external interface to the Performance Monitors (FEAT_PMUv3_EXT32). */ 1252 uint32_t fPmuV3Ext32 : 1; 1253 /** Supports External interface to the Performance Monitors (FEAT_PMUv3_EXT). */ 1254 uint32_t fPmuV3Ext : 1; 1255 /** Supports Trapping support for RNDR/RNDRRS (FEAT_RNG_TRAP). */ 1256 uint32_t fRngTrap : 1; 1257 /** Supports Statistical Profiling Extension version 1.3 (FEAT_SPEv1p3). */ 1258 uint32_t fSpeV1p3 : 1; 1259 /** Supports EL0 use of IMPLEMENTATION DEFINEd functionality (FEAT_TIDCP1). */ 1260 uint32_t fTidcp1 : 1; 1261 /** Supports Branch Record Buffer Extension version 1.1 (FEAT_BRBEv1p1). */ 1262 uint32_t fBrbeV1p1 : 1; 1263 /** @} */ 1264 1265 /** @name 2022 Architecture Extensions. 1266 * @{ */ 1267 /** Supports Address Breakpoint Linking Extenions (FEAT_ABLE). */ 1268 uint32_t fAble : 1; 1269 /** Supports Asynchronous Device error exceptions (FEAT_ADERR). */ 1270 uint32_t fAderr : 1; 1271 /** Supports Memory Attribute Index Enhancement (FEAT_AIE). */ 1272 uint32_t fAie : 1; 1273 /** Supports Asynchronous Normal error exception (FEAT_ANERR). */ 1274 uint32_t fAnerr : 1; 1275 /** Supports Breakpoint Mismatch and Range Extension (FEAT_BWE). */ 1276 uint32_t fBwe : 1; 1277 /** Supports Clear Branch History instruction (FEAT_CLRBHB). */ 1278 uint32_t fClrBhb : 1; 1279 /** Supports Check Feature Status (FEAT_CHK). */ 1280 uint32_t fChk : 1; 1281 /** Supports Common Short Sequence Compression instructions (FEAT_CSSC). */ 1282 uint32_t fCssc : 1; 1283 /** Supports Cache Speculation Variant 2 version 3 (FEAT_CSV2_3). */ 1284 uint32_t fCsv2v3 : 1; 1285 /** Supports 128-bit Translation Tables, 56 bit PA (FEAT_D128). */ 1286 uint32_t fD128 : 1; 1287 /** Supports Debug v8.9 (FEAT_Debugv8p9). */ 1288 uint32_t fDebugV8p9 : 1; 1289 /** Supports Enhancements to the Double Fault Extension (FEAT_DoubleFault2). */ 1290 uint32_t fDoubleFault2 : 1; 1291 /** Supports Exception based Event Profiling (FEAT_EBEP). */ 1292 uint32_t fEbep : 1; 1293 /** Supports Exploitative control using branch history information (FEAT_ECBHB). */ 1294 uint32_t fEcBhb : 1; 1295 /** Supports for EDHSR (FEAT_EDHSR). */ 1296 uint32_t fEdhsr : 1; 1297 /** Supports Embedded Trace Extension version 1.3 (FEAT_ETEv1p3). */ 1298 uint32_t fEteV1p3 : 1; 1299 /** Supports Fine-grained traps 2 (FEAT_FGT2). */ 1300 uint32_t fFgt2 : 1; 1301 /** Supports Guarded Control Stack Extension (FEAT_GCS). */ 1302 uint32_t fGcs : 1; 1303 /** Supports Hardware managed Access Flag for Table descriptors (FEAT_HAFT). */ 1304 uint32_t fHaft : 1; 1305 /** Supports Instrumentation Extension (FEAT_ITE). */ 1306 uint32_t fIte : 1; 1307 /** Supports Load-Acquire RCpc instructions version 3 (FEAT_LRCPC3). */ 1308 uint32_t fLrcpc3 : 1; 1309 /** Supports 128-bit atomics (FEAT_LSE128). */ 1310 uint32_t fLse128 : 1; 1311 /** Supports 56-bit VA (FEAT_LVA3). */ 1312 uint32_t fLva3 : 1; 1313 /** Supports Memory Encryption Contexts (FEAT_MEC). */ 1314 uint32_t fMec : 1; 1315 /** Supports Enhanced Memory Tagging Extension (FEAT_MTE4). */ 1316 uint32_t fMte4 : 1; 1317 /** Supports Canoncial Tag checking for untagged memory (FEAT_MTE_CANONCIAL_TAGS). */ 1318 uint32_t fMteCanonicalTags : 1; 1319 /** Supports FAR_ELx on a Tag Check Fault (FEAT_MTE_TAGGED_FAR). */ 1320 uint32_t fMteTaggedFar : 1; 1321 /** Supports Store only Tag checking (FEAT_MTE_STORE_ONLY). */ 1322 uint32_t fMteStoreOnly : 1; 1323 /** Supports Memory tagging with Address tagging disabled (FEAT_MTE_NO_ADDRESS_TAGS). */ 1324 uint32_t fMteNoAddressTags : 1; 1325 /** Supports Memory tagging asymmetric faults (FEAT_MTE_ASYM_FAULT). */ 1326 uint32_t fMteAsymFault : 1; 1327 /** Supports Memory Tagging asynchronous faulting (FEAT_MTE_ASYNC). */ 1328 uint32_t fMteAsync : 1; 1329 /** Supports Allocation tag access permission (FEAT_MTE_PERM_S1). */ 1330 uint32_t fMtePermS1 : 1; 1331 /** Supports Armv8.9 PC Sample-based Profiling Extension (FEAT_PCSRv8p9). */ 1332 uint32_t fPcsrV8p9 : 1; 1333 /** Supports Permission model enhancements (FEAT_S1PIE). */ 1334 uint32_t fS1Pie : 1; 1335 /** Supports Permission model enhancements (FEAT_S2PIE). */ 1336 uint32_t fS2Pie : 1; 1337 /** Supports Permission model enhancements (FEAT_S1POE). */ 1338 uint32_t fS1Poe : 1; 1339 /** Supports Permission model enhancements (FEAT_S2POE). */ 1340 uint32_t fS2Poe : 1; 1341 /** Supports Physical Fault Address Registers (FEAT_PFAR). */ 1342 uint32_t fPfar : 1; 1343 /** Supports Armv8.9 PMU extensions (FEAT_PMUv3p9). */ 1344 uint32_t fPmuV3p9 : 1; 1345 /** Supports PMU event edge detection (FEAT_PMUv3_EDGE). */ 1346 uint32_t fPmuV3Edge : 1; 1347 /** Supports Fixed-function instruction counter (FEAT_PMUv3_ICNTR). */ 1348 uint32_t fPmuV3Icntr : 1; 1349 /** Supports PMU Snapshot Extension (FEAT_PMUv3_SS). */ 1350 uint32_t fPmuV3Ss : 1; 1351 /** Supports SLC traget for PRFM instructions (FEAT_PRFMSLC). */ 1352 uint32_t fPrfmSlc : 1; 1353 /** Supports RAS version 2 (FEAT_RASv2). */ 1354 uint32_t fRasV2 : 1; 1355 /** Supports RAS version 2 System Architecture (FEAT_RASSAv2). */ 1356 uint32_t fRasSaV2 : 1; 1357 /** Supports for Range Prefetch Memory instruction (FEAT_RPRFM). */ 1358 uint32_t fRprfm : 1; 1359 /** Supports extensions to SCTLR_ELx (FEAT_SCTLR2). */ 1360 uint32_t fSctlr2 : 1; 1361 /** Supports Synchronous Exception-based Event Profiling (FEAT_SEBEP). */ 1362 uint32_t fSebep : 1; 1363 /** Supports non-widening half-precision FP16 to FP16 arithmetic for SME2.1 (FEAT_SME_F16F16). */ 1364 uint32_t fSmeF16F16 : 1; 1365 /** Supports Scalable Matrix Extension version 2 (FEAT_SME2). */ 1366 uint32_t fSme2 : 1; 1367 /** Supports Scalable Matrix Extension version 2.1 (FEAT_SME2p1). */ 1368 uint32_t fSme2p1 : 1; 1369 /** Supports Enhanced speculation restriction instructions (FEAT_SPECRES2). */ 1370 uint32_t fSpecres2 : 1; 1371 /** Supports System Performance Monitors Extension (FEAT_SPMU). */ 1372 uint32_t fSpmu : 1; 1373 /** Supports Statistical profiling Extension version 1.4 (FEAT_SPEv1p4). */ 1374 uint32_t fSpeV1p4 : 1; 1375 /** Supports Call Return Branch Records (FEAT_SPE_CRR). */ 1376 uint32_t fSpeCrr : 1; 1377 /** Supports Data Source Filtering (FEAT_SPE_FDS). */ 1378 uint32_t fSpeFds : 1; 1379 /** Supports Scalable Vector Extension version SVE2.1 (FEAT_SVE2p1). */ 1380 uint32_t fSve2p1 : 1; 1381 /** Supports Non-widening BFloat16 to BFloat16 arithmetic for SVE (FEAT_SVE_B16B16). */ 1382 uint32_t fSveB16B16 : 1; 1383 /** Supports 128-bit System instructions (FEAT_SYSINSTR128). */ 1384 uint32_t fSysInstr128 : 1; 1385 /** Supports 128-bit System registers (FEAT_SYSREG128). */ 1386 uint32_t fSysReg128 : 1; 1387 /** Supports Extension to TCR_ELx (FEAT_TCR2). */ 1388 uint32_t fTcr2 : 1; 1389 /** Supports Translation Hardening Extension (FEAT_THE). */ 1390 uint32_t fThe : 1; 1391 /** Supports Trace Buffer external mode (FEAT_TRBE_EXT). */ 1392 uint32_t fTrbeExt : 1; 1393 /** Supports Trace Buffer MPAM extension (FEAT_TRBE_MPAM). */ 1394 uint32_t fTrbeMpam : 1; 1395 /** @} */ 1396 1397 /** Padding to the required size to match CPUMFEATURES for x86/amd64. */ 1398 uint8_t abPadding[4]; 1399 } CPUMFEATURESARMV8; 1400 #ifndef VBOX_FOR_DTRACE_LIB 1401 AssertCompileSize(CPUMFEATURESARMV8, 48); 1402 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmCpuVendor, CPUMFEATURESARMV8, enmCpuVendor); 1403 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, uFamily, CPUMFEATURESARMV8, uFamily); 1404 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, uModel, CPUMFEATURESARMV8, uModel); 1405 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, uStepping, CPUMFEATURESARMV8, uStepping); 1406 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmMicroarch, CPUMFEATURESARMV8, enmMicroarch); 1407 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxPhysAddrWidth, CPUMFEATURESARMV8, cMaxPhysAddrWidth); 1408 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxLinearAddrWidth, CPUMFEATURESARMV8, cMaxLinearAddrWidth); 1409 #endif 1410 1411 1412 /** 1413 * Chameleon wrapper structure for the host CPU features. 1414 * 1415 * This is used for the globally readable g_CpumHostFeatures variable, which is 1416 * initialized once during VMMR0 load for ring-0 and during CPUMR3Init in 1417 * ring-3. To reflect this immutability after load/init, we use this wrapper 1418 * structure to switch it between const and non-const depending on the context. 1419 * Only two files sees it as non-const (CPUMR0.cpp and CPUM.cpp). 1420 */ 1421 typedef union CPUHOSTFEATURES 1422 { 1423 /** Fields common to all CPU types. */ 1424 CPUMFEATURESCOMMON Common; 1425 /** The host specific structure. */ 1426 #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) 1427 CPUMFEATURESX86 1428 #elif defined(RT_ARCH_ARM64) 1429 CPUMFEATURESARMV8 1430 #else 1431 # error "port me" 1432 #endif 1433 #ifndef CPUM_WITH_NONCONST_HOST_FEATURES 1434 const 1435 #endif 1436 s; 1437 } CPUHOSTFEATURES; 1438 /** Pointer to a const host CPU feature structure. */ 1439 typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES; 1440 1441 /** Host CPU features. 1442 * @note In ring-3, only valid after CPUMR3Init. In ring-0, valid after 1443 * module init. */ 1444 extern CPUHOSTFEATURES g_CpumHostFeatures; 1445 1446 1447 /** The target CPU feature structure. 1448 * @todo this should have a chameleon wrapper as well (ring-0). */ 1449 #ifndef VBOX_VMM_TARGET_ARMV8 1450 typedef CPUMFEATURESX86 CPUMFEATURES; 1451 #else 1452 typedef CPUMFEATURESARMV8 CPUMFEATURES; 1453 #endif 1454 /** Pointer to a CPU feature structure. */ 1455 typedef CPUMFEATURES *PCPUMFEATURES; 1456 /** Pointer to a const CPU feature structure. */ 1457 typedef CPUMFEATURES const *PCCPUMFEATURES; 1458 1459 351 1460 /* 352 1461 * Include the target specific header. … … 358 1467 # include <VBox/vmm/cpum-armv8.h> 359 1468 #endif 1469 360 1470 361 1471
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