Changeset 108791 in vbox for trunk/include

Timestamp:

Mar 28, 2025 9:58:31 PM (3 weeks ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

168226

Message:

VMM/IEM: More ARM target work. jiraref:VBP-1598

Location:

trunk/include

Files:

• VBox/vmm/pgm.h (modified) (5 diffs)
• iprt/armv8.h (modified) (1 diff)

trunk/include/VBox/vmm/pgm.h

@@ -580 +580 @@
  * attributes as well as a myriade of feature dependent field interpretations.
  *
- * The stage 1 effective access attributes are placed in bits 47:32, with some
- * room reserved for new stuff. A set of leaf bits are copied raw, but NSE had
- * to be shifted down due to nG confusion.
+ * The stage 1 effective access attributes are placed in bits 41:32.  A set of
+ * leaf bits are copied raw, but NSE had to be shifted down due to nG confusion.
  *
  * The stage 2 effective access attributes are placed in bit 31:24.  Bits taken
@@ -641 +640 @@
 #define PGM_PTATTRS_S2_TL1_SHIFT                    30
 #define PGM_PTATTRS_S2_TL1_MASK                     RT_BIT_64(PGM_PTATTRS_S2_TL1_SHIFT)
+/** Stage 2: Device memory type. */
+#define PGM_PTATTRS_S2_DEVICE_SHIFT                 31
+#define PGM_PTATTRS_S2_DEVICE_MASK                  RT_BIT_64(PGM_PTATTRS_S2_DEVICE_SHIFT)
 
 /** Stage 1: Privileged read access. */
@@ -654 +656 @@
 #define PGM_PTATTRS_PGCS_SHIFT                      35
 #define PGM_PTATTRS_PGCS_MASK                       RT_BIT_64(PGM_PTATTRS_PGCS_SHIFT)
+/** Stage 1:  Unprivileged read access. */
+#define PGM_PTATTRS_UR_SHIFT                        36
+#define PGM_PTATTRS_UR_MASK                         RT_BIT_64(PGM_PTATTRS_UR_SHIFT)
+/** Stage 1:  Unprivileged write access. */
+#define PGM_PTATTRS_UW_SHIFT                        37
+#define PGM_PTATTRS_UW_MASK                         RT_BIT_64(PGM_PTATTRS_UW_SHIFT)
+/** Stage 1:  Unprivileged execute access. */
+#define PGM_PTATTRS_UX_SHIFT                        38
+#define PGM_PTATTRS_UX_MASK                         RT_BIT_64(PGM_PTATTRS_UX_SHIFT)
+/** Stage 1:  Unprivileged guarded control stack (GCS) access. */
+#define PGM_PTATTRS_UGCS_SHIFT                      39
+#define PGM_PTATTRS_UGCS_MASK                       RT_BIT_64(PGM_PTATTRS_UGCS_SHIFT)
 /** Stage 1:  Privileged write-implies-no-execute access.
  * @todo not sure if we need expose this bit.  */
-#define PGM_PTATTRS_PWXN_SHIFT                      36
+#define PGM_PTATTRS_PWXN_SHIFT                      40
 #define PGM_PTATTRS_PWXN_MASK                       RT_BIT_64(PGM_PTATTRS_PWXN_SHIFT)
-
-/** Stage 1:  Unprivileged read access. */
-#define PGM_PTATTRS_UR_SHIFT                        40
-#define PGM_PTATTRS_UR_MASK                         RT_BIT_64(PGM_PTATTRS_UR_SHIFT)
-/** Stage 1:  Unprivileged write access. */
-#define PGM_PTATTRS_UW_SHIFT                        41
-#define PGM_PTATTRS_UW_MASK                         RT_BIT_64(PGM_PTATTRS_UW_SHIFT)
-/** Stage 1:  Unprivileged execute access. */
-#define PGM_PTATTRS_UX_SHIFT                        42
-#define PGM_PTATTRS_UX_MASK                         RT_BIT_64(PGM_PTATTRS_UX_SHIFT)
-/** Stage 1:  Unprivileged guarded control stack (GCS) access. */
-#define PGM_PTATTRS_UGCS_SHIFT                      43
-#define PGM_PTATTRS_UGCS_MASK                       RT_BIT_64(PGM_PTATTRS_UGCS_SHIFT)
 /** Stage 1:  Unprivileged write-implies-no-execute access.
  * @todo not sure if we need expose this bit. */
-#define PGM_PTATTRS_UWXN_SHIFT                      44
+#define PGM_PTATTRS_UWXN_SHIFT                      41
 #define PGM_PTATTRS_UWXN_MASK                       RT_BIT_64(PGM_PTATTRS_UWXN_SHIFT)
+/** Stage 1: Device memory type. */
+#define PGM_PTATTRS_DEVICE_SHIFT                    42
+#define PGM_PTATTRS_DEVICE_MASK                     RT_BIT_64(PGM_PTATTRS_DEVICE_SHIFT)
 
 /** Page/block level: Guarded page */
@@ -916 +920 @@
 /** The query is for a user mode access, so don't set leaf A or D bits
  * unless the effective access allows usermode access.
- * Assume supervisor access when not set. */
+ * Assume supervisor (priveleged) access when not set. */
 #define PGMQPAGE_F_USER_MODE    RT_BIT_32(3)
-/** Treat CR0.WP as zero when evalutating the access.
+#if defined( VBOX_VMM_TARGET_X86) || defined(DOXYGEN_RUNNING)
+/** X86: Treat CR0.WP as zero when evalutating the access.
  * @note Same value as X86_CR0_WP.  */
-#define PGMQPAGE_F_CR0_WP0      RT_BIT_32(16)
+# define PGMQPAGE_F_CR0_WP0     RT_BIT_32(16)
+#endif
+/** @todo ARM: security, s2, GCS, ++ */
 /** The valid flag mask.   */
-#define PGMQPAGE_F_VALID_MASK   UINT32_C(0x0001000f)
+#if defined( VBOX_VMM_TARGET_X86) || defined(DOXYGEN_RUNNING)
+# define PGMQPAGE_F_VALID_MASK  UINT32_C(0x0001000f)
+#else
+# define PGMQPAGE_F_VALID_MASK  UINT32_C(0x0000000f)
+#endif
 /** @} */
 VMM_INT_DECL(int)   PGMGstQueryPageFast(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags, PPGMPTWALKFAST pWalkFast);
@@ -1192 +1203 @@
 /** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
  * @{ */
-#define PGMIEMGCPHYS2PTR_F_NO_WRITE     RT_BIT_32(3)    /**< Not writable (IEMTLBE_F_PG_NO_WRITE). */
-#define PGMIEMGCPHYS2PTR_F_NO_READ      RT_BIT_32(4)    /**< Not readable (IEMTLBE_F_PG_NO_READ). */
-#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(8)    /**< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). */
-#define PGMIEMGCPHYS2PTR_F_UNASSIGNED   RT_BIT_32(9)    /**< Unassgined memory (IEMTLBE_F_PG_UNASSIGNED). */
-#define PGMIEMGCPHYS2PTR_F_CODE_PAGE    RT_BIT_32(10)    /**< Write monitored IEM code page (IEMTLBE_F_PG_CODE_PAGE). */
+/** @def PGMIEMGCPHYS2PTR_F_NO_WRITE
+ * Not writable (IEMTLBE_F_PG_NO_WRITE). */
+/** @def PGMIEMGCPHYS2PTR_F_NO_READ
+ * Not readable (IEMTLBE_F_PG_NO_READ). */
+/** @def PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3
+ * No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). */
+/** @def PGMIEMGCPHYS2PTR_F_UNASSIGNED
+ * Unassigned memory (IEMTLBE_F_PG_UNASSIGNED). */
+/** @def PGMIEMGCPHYS2PTR_F_CODE_PAGE
+ * Write monitored IEM code page (IEMTLBE_F_PG_CODE_PAGE). */
+#if defined(VBOX_VMM_TARGET_X86) || defined(DOXYGEN_RUNNING)
+# define PGMIEMGCPHYS2PTR_F_NO_WRITE     RT_BIT_32(3)
+# define PGMIEMGCPHYS2PTR_F_NO_READ      RT_BIT_32(4)
+# define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(8)
+# define PGMIEMGCPHYS2PTR_F_UNASSIGNED   RT_BIT_32(9)
+# define PGMIEMGCPHYS2PTR_F_CODE_PAGE    RT_BIT_32(10)
+#elif defined(VBOX_VMM_TARGET_ARMV8)
+# define PGMIEMGCPHYS2PTR_F_NO_READ      RT_BIT_32(13)
+# define PGMIEMGCPHYS2PTR_F_NO_WRITE     RT_BIT_32(14)
+# define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(15)
+# define PGMIEMGCPHYS2PTR_F_UNASSIGNED   RT_BIT_32(16)
+# define PGMIEMGCPHYS2PTR_F_CODE_PAGE    RT_BIT_32(17)
+#endif
 /** @} */
 

trunk/include/iprt/armv8.h

@@ -1254 +1254 @@
 # define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE              3
 /** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
-#define ARMV8_TCR_EL1_AARCH64_TG0                               (RT_BIT_64(14) | RT_BIT_64(15))
-#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr)                    (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14)
+#define ARMV8_TCR_EL1_AARCH64_TG0_MASK                          (RT_BIT_64(14) | RT_BIT_64(15))
+#define ARMV8_TCR_EL1_AARCH64_TG0_SHIFT                         14
+#define ARMV8_TCR_EL1_AARCH64_TG0                               ARMV8_TCR_EL1_AARCH64_TG0_MASK
+#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr)                    (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> ARMV8_TCR_EL1_AARCH64_TG0_SHIFT)
 /** Invalid granule size. */
 # define ARMV8_TCR_EL1_AARCH64_TG0_INVALID                      0
-/** 16KiB granule size. */
+/** 16KiB granule size (shifted down). */
 # define ARMV8_TCR_EL1_AARCH64_TG0_16KB                         1
-/** 4KiB granule size. */
+/** 4KiB granule size (shifted down). */
 # define ARMV8_TCR_EL1_AARCH64_TG0_4KB                          2
-/** 64KiB granule size. */
+/** 64KiB granule size (shifted down). */
 # define ARMV8_TCR_EL1_AARCH64_TG0_64KB                         3
 /** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */