Changeset 13232 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Oct 13, 2008 8:03:48 PM (16 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

37813

Message:

#1865: changed some validation into pure assertions or assert-return. added some todos, update a comment or five and adjusted lots of whitespace.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• PGMAll.cpp (modified) (21 diffs)
• PGMAllBth.h (modified) (32 diffs)
• PGMAllGst.h (modified) (7 diffs)
• PGMAllHandler.cpp (modified) (11 diffs)
• PGMAllMap.cpp (modified) (3 diffs)
• PGMAllShw.h (modified) (13 diffs)

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -403 +403 @@
             STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVReserved);
     }
-#endif
+#endif /* VBOX_WITH_STATISTICS */
 
     /*
@@ -476 +476 @@
  * @param   cbSize      Access size
  * @param   fAccess     Access type (r/w, user/supervisor (X86_PTE_*))
+ * @remarks Current not in use.
  */
 VMMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
@@ -531 +532 @@
 VMMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
 {
-    /*
-     * Validate input.
-     */
-    if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
-    {
-        AssertMsgFailed(("PGMVerifyAccess: invalid access type %08x\n", fAccess));
-        return VERR_INVALID_PARAMETER;
-    }
-
+    AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
+
+    /*
+     * Get going.
+     */
     uint64_t fPageGst;
     int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
@@ -567 +564 @@
     {
         /*
-        * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
-        */
+         * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
+         */
         rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
         if (    rc == VERR_PAGE_NOT_PRESENT
@@ -678 +675 @@
      * Inform CSAM about the flush
      */
-    /** @note this is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
+    /* note: This is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
     CSAMR3FlushPage(pVM, GCPtrPage);
 # endif
@@ -753 +750 @@
  * @remark  You must use PGMMapModifyPage() for pages in a mapping.
  */
-VMMDECL(int)  PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
-{
-    /*
-     * Validate input.
-     */
-    if (fFlags & X86_PTE_PAE_PG_MASK)
-    {
-        AssertMsgFailed(("fFlags=%#llx\n", fFlags));
-        return VERR_INVALID_PARAMETER;
-    }
-    if (!cb)
-    {
-        AssertFailed();
-        return VERR_INVALID_PARAMETER;
-    }
+VMMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
+{
+    AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
+    Assert(cb);
 
     /*
@@ -870 +856 @@
 }
 
-
 #ifndef IN_GC
+
 /**
  * Syncs the SHADOW page directory pointer for the specified address. Allocates
@@ -909 +895 @@
             PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
 
-            rc = pgmPoolAlloc(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e, &pShwPage);
+            rc = pgmPoolAlloc(pVM, pPml4eGst->u & X86_PML4E_PG_MASK,
+                              PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e, &pShwPage);
         }
         else
-            rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
+            rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(63) /* hack: make the address unique */,
+                              PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
 
         if (rc == VERR_PGM_POOL_FLUSHED)
@@ -978 +966 @@
 }
 
+
 /**
  * Gets the SHADOW page directory pointer for the specified address.
@@ -1018 +1007 @@
     return VINF_SUCCESS;
 }
+
 
 /**
@@ -1106 +1096 @@
 }
 
-#endif
+#endif /* IN_GC */
 
 /**
@@ -1179 +1169 @@
      * Validate input.
      */
-    if (fFlags & X86_PTE_PAE_PG_MASK)
-    {
-        AssertMsgFailed(("fFlags=%#llx\n", fFlags));
-        STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
-        return VERR_INVALID_PARAMETER;
-    }
-
-    if (!cb)
-    {
-        AssertFailed();
-        STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
-        return VERR_INVALID_PARAMETER;
-    }
+    AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
+    Assert(cb);
 
     LogFlow(("PGMGstModifyPage %VGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
@@ -1211 +1190 @@
 }
 
+
 /**
  * Gets the specified page directory pointer table entry.
@@ -1258 +1238 @@
 }
 
+
 /**
  * Gets the current CR3 register value for the nested memory context.
@@ -1284 +1265 @@
 }
 
+
 /**
  * Gets the current CR3 register value for the EPT paging memory context.
@@ -1293 +1275 @@
     return pVM->pgm.s.HCPhysNestedRoot;
 }
+
 
 /**
@@ -1360 +1343 @@
 
 /**
- * Gets the current CR3 register value for the GC intermediate memory context.
+ * Gets the current CR3 register value for the RC intermediate memory context.
  * @returns CR3 value.
  * @param   pVM         The VM handle.
  */
-VMMDECL(RTHCPHYS) PGMGetInterGCCR3(PVM pVM)
+VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM)
 {
     switch (pVM->pgm.s.enmShadowMode)
@@ -1494 +1477 @@
 }
 
-/**
- * Performs and schedules necessary updates following a CR3 load or reload,
- * without actually flushing the TLB as with PGMFlushTLB.
+
+/**
+ * Performs and schedules necessary updates following a CR3 load or reload when
+ * using nested or extended paging.
+ *
+ * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
+ * TLB and triggering a SyncCR3.
  *
  * This will normally involve mapping the guest PD or nPDPT
@@ -1535 +1522 @@
     return rc;
 }
+
 
 /**
@@ -1934 +1922 @@
 
 #else  /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
+    /** @todo @bugref{3202}: Implement ring-0 mapping cache similar to the one in
+     *        RC. To begin with, a simple but expensive one based on
+     *        RTR0MemObjEnterPhys can be used to get things started. Later a
+     *        global cache with mappings per CPU (to avoid shootdown) should be
+     *        employed. */
     AssertFailed();
     return VERR_NOT_IMPLEMENTED;
@@ -1961 +1954 @@
 
 #endif /* IN_GC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
-
 #ifdef VBOX_STRICT
 

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -99 +99 @@
      * Get PDs.
      */
-    int       rc;
+    int             rc;
 #  if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
 #   if PGM_GST_TYPE == PGM_TYPE_32BIT
@@ -677 +677 @@
                         }
 #    ifdef CSAM_DETECT_NEW_CODE_PAGES
-                        else
-                        if (    uErr == X86_TRAP_PF_RW
-                            &&  pRegFrame->ecx >= 0x100         /* early check for movswd count */
-                            &&  pRegFrame->ecx < 0x10000
-                           )
+                        else if (    uErr == X86_TRAP_PF_RW
+                                 &&  pRegFrame->ecx >= 0x100         /* early check for movswd count */
+                                 &&  pRegFrame->ecx < 0x10000)
                         {
                             /* In case of a write to a non-present supervisor shadow page, we'll take special precautions
@@ -885 +883 @@
     && PGM_SHW_TYPE != PGM_TYPE_NESTED \
     && PGM_SHW_TYPE != PGM_TYPE_EPT
-    int rc;
+    int             rc;
 
     LogFlow(("InvalidatePage %VGv\n", GCPtrPage));
@@ -1965 +1963 @@
 
 
-
 #if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
-
 /**
  * Investigate page fault and handle write protection page faults caused by
@@ -2019 +2015 @@
     {
         uPageFaultLevel = 0;
-        goto UpperLevelPageFault;
+        goto l_UpperLevelPageFault;
     }
     Assert(pPdpeSrc);
@@ -2040 +2036 @@
     {
         uPageFaultLevel = 1;
-        goto UpperLevelPageFault;
+        goto l_UpperLevelPageFault;
     }
 # endif
@@ -2056 +2052 @@
     {
         uPageFaultLevel = 2;
-        goto UpperLevelPageFault;
+        goto l_UpperLevelPageFault;
     }
 
@@ -2233 +2229 @@
 
 
-UpperLevelPageFault:
-    /* Pagefault detected while checking the PML4E, PDPE or PDE.
+l_UpperLevelPageFault:
+    /*
+     * Pagefault detected while checking the PML4E, PDPE or PDE.
      * Single exit handler to get rid of duplicate code paths.
      */
@@ -2274 +2271 @@
     return VINF_EM_RAW_GUEST_TRAP;
 }
-
 #endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
 
@@ -2303 +2299 @@
     && PGM_SHW_TYPE != PGM_TYPE_EPT
 
-    int rc = VINF_SUCCESS;
+    int             rc = VINF_SUCCESS;
 
     /*
@@ -2703 +2699 @@
     PX86PDPAE       pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
 # elif PGM_SHW_TYPE == PGM_TYPE_AMD64
-    const unsigned  iPdpte   = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
-    const unsigned  iPDDst   = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
+    const unsigned  iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
+    const unsigned  iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
     PX86PDPAE       pPDDst;
     PX86PDPT        pPdptDst;
@@ -2712 +2708 @@
 
     /* Fetch the pgm pool shadow descriptor. */
-    PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
+    PPGMPOOLPAGE    pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
     Assert(pShwPde);
 # elif PGM_SHW_TYPE == PGM_TYPE_EPT
@@ -2853 +2849 @@
 #  if PGM_GST_TYPE == PGM_TYPE_PROT
         /* AMD-V nested paging */
-        X86PML4E     Pml4eSrc;
-        X86PDPE      PdpeSrc;
-        PX86PML4E    pPml4eSrc = &Pml4eSrc;
+        X86PML4E        Pml4eSrc;
+        X86PDPE         PdpeSrc;
+        PX86PML4E       pPml4eSrc = &Pml4eSrc;
 
         /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
@@ -2889 +2885 @@
     }
     return rc;
+
 #elif PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
     return VINF_SUCCESS; /* ignore */
@@ -2924 +2921 @@
     }
 # endif
+
     /*
      * Get guest PD and index.
      */
-
 # if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
 #  if PGM_GST_TYPE == PGM_TYPE_32BIT
@@ -2956 +2953 @@
     const unsigned  iPDSrc = 0;
 # endif
-    int         rc = VINF_SUCCESS;
+    int             rc = VINF_SUCCESS;
 
     /*
@@ -2962 +2959 @@
      */
 # if PGM_SHW_TYPE == PGM_TYPE_32BIT
-    PX86PDE     pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
+    PX86PDE         pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
-    PX86PDEPAE  pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
+    PX86PDEPAE      pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
 # elif PGM_SHW_TYPE == PGM_TYPE_AMD64
     const unsigned  iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
@@ -2972 +2969 @@
 #  if PGM_GST_TYPE == PGM_TYPE_PROT
     /* AMD-V nested paging */
-    X86PML4E     Pml4eSrc;
-    X86PDPE      PdpeSrc;
-    PX86PML4E    pPml4eSrc = &Pml4eSrc;
+    X86PML4E        Pml4eSrc;
+    X86PDPE         PdpeSrc;
+    PX86PML4E       pPml4eSrc = &Pml4eSrc;
 
     /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
@@ -3369 +3366 @@
                     Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
 #  endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) || PGM_WITHOUT_MAPPINGS */
+
                     /*
-                    * Sync page directory entry.
-                    *
-                    * The current approach is to allocated the page table but to set
-                    * the entry to not-present and postpone the page table synching till
-                    * it's actually used.
-                    */
+                     * Sync page directory entry.
+                     *
+                     * The current approach is to allocated the page table but to set
+                     * the entry to not-present and postpone the page table synching till
+                     * it's actually used.
+                     */
 #  if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
                     for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
@@ -3475 +3473 @@
                 {
                     /*
-                    * Check if there is any page directory to mark not present here.
-                    */
+                     * Check if there is any page directory to mark not present here.
+                     */
 #  if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
                     for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
@@ -3625 +3623 @@
 
 #if PGM_GST_TYPE == PGM_TYPE_PAE
-    /* @todo currently broken; crashes below somewhere */
+    /** @todo currently broken; crashes below somewhere */
     AssertFailed();
 #endif
@@ -3634 +3632 @@
 
 #  if PGM_GST_TYPE == PGM_TYPE_AMD64
-    bool        fBigPagesSupported = true;
+    bool            fBigPagesSupported = true;
 #  else
-    bool        fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
-#  endif
-    PPGM        pPGM = &pVM->pgm.s;
-    RTGCPHYS    GCPhysGst;              /* page address derived from the guest page tables. */
-    RTHCPHYS    HCPhysShw;              /* page address derived from the shadow page tables. */
+    bool            fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
+#  endif
+    PPGM            pPGM = &pVM->pgm.s;
+    RTGCPHYS        GCPhysGst;              /* page address derived from the guest page tables. */
+    RTHCPHYS        HCPhysShw;              /* page address derived from the shadow page tables. */
 # ifndef IN_RING0
-    RTHCPHYS    HCPhys;                 /* general usage. */
-# endif
-    int         rc;
+    RTHCPHYS        HCPhys;                 /* general usage. */
+# endif
+    int             rc;
 
     /*
@@ -3675 +3673 @@
 # if PGM_SHW_TYPE == PGM_TYPE_32BIT
     unsigned        cPDEs       = X86_PG_ENTRIES;
-    unsigned        ulIncrement = X86_PG_ENTRIES * PAGE_SIZE;
+    unsigned        cIncrement  = X86_PG_ENTRIES * PAGE_SIZE;
 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
 #  if PGM_GST_TYPE == PGM_TYPE_32BIT
@@ -3682 +3680 @@
     unsigned        cPDEs       = X86_PG_PAE_ENTRIES;
 #  endif
-    unsigned        ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
+    unsigned        cIncrement  = X86_PG_PAE_ENTRIES * PAGE_SIZE;
 # elif PGM_SHW_TYPE == PGM_TYPE_AMD64
     unsigned        cPDEs       = X86_PG_PAE_ENTRIES;
-    unsigned        ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
+    unsigned        cIncrement  = X86_PG_PAE_ENTRIES * PAGE_SIZE;
 # endif
     if (cb != ~(RTGCUINTPTR)0)
@@ -3693 +3691 @@
 
 # if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
-    PPGMPOOL    pPool         = pVM->pgm.s.CTX_SUFF(pPool);
+    PPGMPOOL        pPool       = pVM->pgm.s.CTX_SUFF(pPool);
 # endif
 
@@ -3701 +3699 @@
     for (; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
     {
-        PPGMPOOLPAGE pShwPdpt = NULL;
-        PX86PML4E    pPml4eSrc, pPml4eDst;
-        RTGCPHYS     GCPhysPdptSrc;
+        PPGMPOOLPAGE    pShwPdpt = NULL;
+        PX86PML4E       pPml4eSrc;
+        PX86PML4E       pPml4eDst;
+        RTGCPHYS        GCPhysPdptSrc;
 
         pPml4eSrc     = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
@@ -3711 +3710 @@
         if (!pPml4eDst->n.u1Present)
         {
-            GCPtr += UINT64_C(_2M * 512 * 512);
+            GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
             continue;
         }
@@ -3725 +3724 @@
         {
             AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
-            GCPtr += UINT64_C(_2M * 512 * 512);
+            GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
             cErrors++;
             continue;
@@ -3733 +3732 @@
         {
             AssertMsgFailed(("Physical address doesn't match! iPml4e %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
-            GCPtr += UINT64_C(_2M * 512 * 512);
+            GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
             cErrors++;
             continue;
@@ -3743 +3742 @@
         {
             AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
-            GCPtr += UINT64_C(_2M * 512 * 512);
+            GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
             cErrors++;
             continue;
@@ -3833 +3832 @@
 # endif
 # if PGM_GST_TYPE == PGM_TYPE_32BIT
-            const GSTPD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
+            const GSTPD    *pPDSrc = CTXSUFF(pPGM->pGuestPD);
 #  if PGM_SHW_TYPE == PGM_TYPE_32BIT
-            const X86PD    *pPDDst = pPGM->CTXMID(p,32BitPD);
+            PCX86PD         pPDDst = pPGM->CTXMID(p,32BitPD);
 #  else
-            const PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];       /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
+            PCX86PDPAE      pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
 #  endif
 # endif
@@ -3848 +3847 @@
             for (;
                 iPDDst < cPDEs;
-                iPDDst++, GCPtr += ulIncrement)
+                iPDDst++, GCPtr += cIncrement)
             {
                 const SHWPDE PdeDst = pPDDst->a[iPDDst];

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -60 +60 @@
 # define PGSTPDE                    PSHWPDE
 # define GST_PTE_PG_MASK            SHW_PTE_PG_MASK
+
 #elif PGM_GST_TYPE == PGM_TYPE_32BIT
 # define GSTPT                      X86PT
@@ -81 +82 @@
 # define GST_PT_MASK                X86_PT_MASK
 # define GST_CR3_PAGE_MASK          X86_CR3_PAGE_MASK
+
 #elif   PGM_GST_TYPE == PGM_TYPE_PAE \
      || PGM_GST_TYPE == PGM_TYPE_AMD64
@@ -503 +505 @@
 
                 Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
-try_again:
+l_try_again:
                 rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.pHCShwAmd64CR3);
                 if (rc == VERR_PGM_POOL_FLUSHED)
@@ -511 +513 @@
                     rc = pgmPoolSyncCR3(pVM);
                     AssertRC(rc);
-                    goto try_again;
+                    goto l_try_again;
                 }
                 pVM->pgm.s.pHCPaePML4    = (PX86PML4)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.pHCShwAmd64CR3);
@@ -649 +651 @@
         pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
     }
+
     /*
      * Do the 4 PDs.
@@ -783 +786 @@
 #endif
 
-    unsigned    offPage = GCPtr & PAGE_OFFSET_MASK;
-    unsigned    iPage = 0;
+    unsigned        offPage = GCPtr & PAGE_OFFSET_MASK;
+    unsigned        iPage = 0;
     while (iPage < pCur->cPages)
     {
@@ -1043 +1046 @@
 
 #endif /* PGM_TYPE_32BIT && !IN_RING3 */
-
-
 #if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
 

trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp

@@ -92 +92 @@
      * Validate input.
      */
-    if (GCPhys >= GCPhysLast)
-    {
-        AssertMsgFailed(("GCPhys >= GCPhysLast (%#x >= %#x)\n", GCPhys, GCPhysLast));
-        return VERR_INVALID_PARAMETER;
-    }
+    AssertMsgReturn(GCPhys < GCPhysLast, ("GCPhys >= GCPhysLast (%#x >= %#x)\n", GCPhys, GCPhysLast), VERR_INVALID_PARAMETER);
     switch (enmType)
     {
@@ -107 +103 @@
             return VERR_INVALID_PARAMETER;
     }
-    if (    (RTRCUINTPTR)pvUserRC >= 0x10000
-        &&  MMHyperR3ToRC(pVM, MMHyperRCToR3(pVM, pvUserRC)) != pvUserRC)
-    {
-        AssertMsgFailed(("Not RC pointer! pvUserRC=%RRv\n", pvUserRC));
-        return VERR_INVALID_PARAMETER;
-    }
+    AssertMsgReturn(    (RTRCUINTPTR)pvUserRC < 0x10000
+                    ||  MMHyperR3ToRC(pVM, MMHyperRCToR3(pVM, pvUserRC)) == pvUserRC,
+                    ("Not RC pointer! pvUserRC=%RRv\n", pvUserRC),
+                    VERR_INVALID_PARAMETER);
     AssertReturn(pfnHandlerR3 || pfnHandlerR0 || pfnHandlerRC, VERR_INVALID_PARAMETER);
 
@@ -659 +653 @@
     pgmLock(pVM);
     PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
-    if (pCur)
-    {
-        if (GCPhysSplit <= pCur->Core.KeyLast)
+    if (RT_LIKELY(pCur))
+    {
+        if (RT_LIKELY(GCPhysSplit <= pCur->Core.KeyLast))
         {
             /*
@@ -673 +667 @@
             pCur->cPages        = (pCur->Core.KeyLast - (pCur->Core.Key & X86_PTE_PAE_PG_MASK) + PAGE_SIZE) >> PAGE_SHIFT;
 
-            if (RTAvlroGCPhysInsert(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, &pNew->Core))
+            if (RT_LIKELY(RTAvlroGCPhysInsert(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, &pNew->Core)))
             {
                 LogFlow(("PGMHandlerPhysicalSplit: %VGp-%VGp and %VGp-%VGp\n",
@@ -716 +710 @@
     pgmLock(pVM);
     PPGMPHYSHANDLER pCur1 = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys1);
-    if (pCur1)
+    if (RT_LIKELY(pCur1))
     {
         PPGMPHYSHANDLER pCur2 = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys2);
-        if (pCur2)
+        if (RT_LIKELY(pCur2))
         {
             /*
              * Make sure that they are adjacent, and that they've got the same callbacks.
              */
-            if (pCur1->Core.KeyLast + 1 == pCur2->Core.Key)
+            if (RT_LIKELY(pCur1->Core.KeyLast + 1 == pCur2->Core.Key))
             {
-                if (    pCur1->pfnHandlerRC == pCur2->pfnHandlerRC
-                    &&  pCur1->pfnHandlerR0 == pCur2->pfnHandlerR0
-                    &&  pCur1->pfnHandlerR3 == pCur2->pfnHandlerR3)
+                if (RT_LIKELY(    pCur1->pfnHandlerRC == pCur2->pfnHandlerRC
+                              &&  pCur1->pfnHandlerR0 == pCur2->pfnHandlerR0
+                              &&  pCur1->pfnHandlerR3 == pCur2->pfnHandlerR3))
                 {
                     PPGMPHYSHANDLER pCur3 = (PPGMPHYSHANDLER)RTAvlroGCPhysRemove(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys2);
-                    if (pCur3 == pCur2)
+                    if (RT_LIKELY(pCur3 == pCur2))
                     {
                         pCur1->Core.KeyLast  = pCur2->Core.KeyLast;
@@ -794 +788 @@
     int rc;
     PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
-    if (pCur)
+    if (RT_LIKELY(pCur))
     {
         /*
@@ -871 +865 @@
      */
     PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
-    if (pCur)
-    {
-        if (    GCPhysPage >= pCur->Core.Key
-            &&  GCPhysPage <= pCur->Core.KeyLast)
+    if (RT_LIKELY(pCur))
+    {
+        if (RT_LIKELY(    GCPhysPage >= pCur->Core.Key
+                      &&  GCPhysPage <= pCur->Core.KeyLast))
         {
             Assert(!(pCur->Core.Key & PAGE_OFFSET_MASK));
@@ -925 +919 @@
      */
     PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
-    if (pCur)
-    {
-        if (    GCPhysPage >= pCur->Core.Key
-            &&  GCPhysPage <= pCur->Core.KeyLast)
+    if (RT_LIKELY(pCur))
+    {
+        if (RT_LIKELY(    GCPhysPage >= pCur->Core.Key
+                      &&  GCPhysPage <= pCur->Core.KeyLast))
         {
             Assert(!(pCur->Core.Key & PAGE_OFFSET_MASK));
@@ -961 +955 @@
  *
  * @returns boolean
- * @param   pVM         VM Handle
+ * @param   pVM         VM Handle.
  * @param   GCPhys      Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
  */
@@ -1143 +1137 @@
 }
 
-
 #if defined(VBOX_STRICT) || defined(LOG_ENABLED)
+
 /**
  * Worker for pgmHandlerVirtualDumpPhysPages.
@@ -1172 +1166 @@
                            pgmHandlerVirtualDumpPhysPagesCallback, 0);
 }
+
 #endif /* VBOX_STRICT || LOG_ENABLED */
-
 #ifdef VBOX_STRICT
 

trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp

@@ -55 +55 @@
     AssertMsg(cbPages > 0 && RT_ALIGN_32(cbPages, PAGE_SIZE) == cbPages, ("Invalid cbPages=%#x\n",  cbPages));
     AssertMsg(!(fFlags & X86_PDE_PG_MASK), ("Invalid flags %#x\n", fFlags));
-    //Assert(HCPhys < _4G); ---  Don't *EVER* try 32-bit shadow mode on a PAE/AMD64 box with memory above 4G !!!
 
     /* hypervisor defaults */
@@ -148 +147 @@
      * Validate input.
      */
-    if (fFlags & X86_PTE_PAE_PG_MASK)
-    {
-        AssertMsgFailed(("fFlags=%#x\n", fFlags));
-        return VERR_INVALID_PARAMETER;
-    }
-    if (!cb)
-    {
-        AssertFailed();
-        return VERR_INVALID_PARAMETER;
-    }
+    AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#x\n", fFlags));
+    Assert(cb);
 
     /*
@@ -175 +166 @@
         if (off < pCur->cb)
         {
-            if (off + cb > pCur->cb)
-            {
-                AssertMsgFailed(("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
-                                 GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast));
-                return VERR_INVALID_PARAMETER;
-            }
+            AssertMsgReturn(off + cb <= pCur->cb,
+                            ("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
+                             GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast),
+                            VERR_INVALID_PARAMETER);
 
             /*

trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

@@ -60 +60 @@
 # define SHW_PT_MASK            X86_PT_MASK
 # define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_PD
+
 #elif PGM_SHW_TYPE == PGM_TYPE_EPT
 # define SHWPT                  EPTPT
@@ -80 +81 @@
 # define SHW_TOTAL_PD_ENTRIES   (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
 # define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_NESTED_ROOT      /* do not use! exception is real mode & protected mode without paging. */
+
 #else
 # define SHWPT                  X86PTPAE
@@ -95 +97 @@
 # define SHW_PT_SHIFT           X86_PT_PAE_SHIFT
 # define SHW_PT_MASK            X86_PT_PAE_MASK
-#if PGM_SHW_TYPE == PGM_TYPE_AMD64
-# define SHW_PDPT_SHIFT         X86_PDPT_SHIFT
-# define SHW_PDPT_MASK          X86_PDPT_MASK_AMD64
-# define SHW_PDPE_PG_MASK       X86_PDPE_PG_MASK
-# define SHW_TOTAL_PD_ENTRIES   (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
-# define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_PAE_PD      /* do not use! exception is real mode & protected mode without paging. */
-#else /* 32 bits PAE mode */
-# define SHW_PDPT_SHIFT         X86_PDPT_SHIFT
-# define SHW_PDPT_MASK          X86_PDPT_MASK_PAE
-# define SHW_PDPE_PG_MASK       X86_PDPE_PG_MASK
-# define SHW_TOTAL_PD_ENTRIES   (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
-# define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_PAE_PD
-#endif
+# if PGM_SHW_TYPE == PGM_TYPE_AMD64
+#  define SHW_PDPT_SHIFT        X86_PDPT_SHIFT
+#  define SHW_PDPT_MASK         X86_PDPT_MASK_AMD64
+#  define SHW_PDPE_PG_MASK      X86_PDPE_PG_MASK
+#  define SHW_TOTAL_PD_ENTRIES  (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
+#  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_PAE_PD      /* do not use! exception is real mode & protected mode without paging. */
+# else /* 32 bits PAE mode */
+#  define SHW_PDPT_SHIFT        X86_PDPT_SHIFT
+#  define SHW_PDPT_MASK         X86_PDPT_MASK_PAE
+#  define SHW_PDPE_PG_MASK      X86_PDPE_PG_MASK
+#  define SHW_TOTAL_PD_ENTRIES  (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
+#  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_PAE_PD
+# endif
 #endif
 
@@ -143 +145 @@
      */
 # if PGM_SHW_TYPE == PGM_TYPE_AMD64
-    bool      fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
+    bool            fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
     X86PDEPAE Pde;
 
     /* PML4 */
-    const unsigned iPml4  = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
+    const unsigned  iPml4  = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
     if (!Pml4e.n.u1Present)
@@ -153 +155 @@
 
     /* PDPT */
-    PX86PDPT pPDPT;
+    PX86PDPT        pPDPT;
     int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
     if (VBOX_FAILURE(rc))
         return rc;
-    const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
-    X86PDPE Pdpe = pPDPT->a[iPDPT];
+    const unsigned  iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
+    X86PDPE         Pdpe = pPDPT->a[iPDPT];
     if (!Pdpe.n.u1Present)
         return VERR_PAGE_TABLE_NOT_PRESENT;
 
     /* PD */
-    PX86PDPAE pPd;
+    PX86PDPAE       pPd;
     rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
     if (VBOX_FAILURE(rc))
         return rc;
-    const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
+    const unsigned  iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
     Pde = pPd->a[iPd];
 
@@ -177 +179 @@
 
 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
-    bool           fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
-    const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
-    const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
-    X86PDEPAE      Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
+    bool            fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
+    const unsigned  iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
+    const unsigned  iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
+    X86PDEPAE       Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
+
 # elif PGM_SHW_TYPE == PGM_TYPE_EPT
     const unsigned  iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
@@ -194 +197 @@
     Assert(pPDDst);
     Pde = pPDDst->a[iPd];
+
 # else /* PGM_TYPE_32BIT */
-    const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
-    X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
+    const unsigned  iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
+    X86PDE          Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
 # endif
     if (!Pde.n.u1Present)
@@ -206 +210 @@
      * Get PT entry.
      */
-    PSHWPT pPT;
+    PSHWPT          pPT;
     if (!(Pde.u & PGM_PDFLAGS_MAPPING))
     {
@@ -230 +234 @@
 # endif
     }
-    const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
-    SHWPTE Pte = pPT->a[iPt];
+    const unsigned  iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
+    SHWPTE          Pte = pPT->a[iPt];
     if (!Pte.n.u1Present)
         return VERR_PAGE_NOT_PRESENT;
@@ -290 +294 @@
          */
 # if PGM_SHW_TYPE == PGM_TYPE_AMD64
-        X86PDEPAE Pde;
+        X86PDEPAE       Pde;
         /* PML4 */
-        const unsigned iPml4  = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
-        X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
+        const unsigned  iPml4  = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
+        X86PML4E        Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
         if (!Pml4e.n.u1Present)
             return VERR_PAGE_TABLE_NOT_PRESENT;
 
         /* PDPT */
-        PX86PDPT pPDPT;
+        PX86PDPT        pPDPT;
         rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
         if (VBOX_FAILURE(rc))
             return rc;
-        const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
-        X86PDPE Pdpe = pPDPT->a[iPDPT];
+        const unsigned  iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
+        X86PDPE         Pdpe = pPDPT->a[iPDPT];
         if (!Pdpe.n.u1Present)
             return VERR_PAGE_TABLE_NOT_PRESENT;
 
         /* PD */
-        PX86PDPAE pPd;
+        PX86PDPAE       pPd;
         rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
         if (VBOX_FAILURE(rc))
@@ -316 +320 @@
 
 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
-        const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
-        const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
+        const unsigned  iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
+        const unsigned  iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
         X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
 
@@ -333 +337 @@
         Assert(pPDDst);
         Pde = pPDDst->a[iPd];
+
 # else /* PGM_TYPE_32BIT */
-        const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
-        X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
+        const unsigned  iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
+        X86PDE          Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
 # endif
         if (!Pde.n.u1Present)
@@ -343 +348 @@
          * Map the page table.
          */
-        PSHWPT pPT;
+        PSHWPT          pPT;
         rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
         if (VBOX_FAILURE(rc))
             return rc;
 
-        unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
+        unsigned        iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
         while (iPTE < RT_ELEMENTS(pPT->a))
         {