Changeset 18927 in vbox for trunk/src/VBox/VMM/VMMGC/TRPMGCHandlers.cpp

Timestamp:

Apr 16, 2009 11:41:38 AM (16 years ago)

Author:

vboxsync

Message:

Big step to separate VMM data structures for guest SMP. (pgm, em)

File:

• trunk/src/VBox/VMM/VMMGC/TRPMGCHandlers.cpp (modified) (23 diffs)

trunk/src/VBox/VMM/VMMGC/TRPMGCHandlers.cpp

@@ -37 +37 @@
 #include "TRPMInternal.h"
 #include <VBox/vm.h>
+#include <VBox/vmm.h>
 #include <VBox/param.h>
 
@@ -134 +135 @@
 static int trpmGCExitTrap(PVM pVM, int rc, PCPUMCTXCORE pRegFrame)
 {
+    PVMCPU   pVCpu = VMMGetCpu0(pVM);
     uint32_t uOldActiveVector = pVM->trpm.s.uActiveVector;
     NOREF(uOldActiveVector);
@@ -166 +168 @@
     if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
     {
-        Log2(("VM_FF_INHIBIT_INTERRUPTS at %08RX32 successor %RGv\n", pRegFrame->eip, EMGetInhibitInterruptsPC(pVM)));
-        if (pRegFrame->eip != EMGetInhibitInterruptsPC(pVM))
+        Log2(("VM_FF_INHIBIT_INTERRUPTS at %08RX32 successor %RGv\n", pRegFrame->eip, EMGetInhibitInterruptsPC(pVM, pVCpu)));
+        if (pRegFrame->eip != EMGetInhibitInterruptsPC(pVM, pVCpu))
         {
             /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
@@ -227 +229 @@
         else if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
 #if 1
-            rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
+            rc = PGMSyncCR3(pVM, pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
 #else
             rc = VINF_PGM_SYNC_CR3;
@@ -258 +260 @@
 {
     RTGCUINTREG uDr6 = ASMGetAndClearDR6();
-    PVM pVM = TRPM2VM(pTrpm);
+    PVM         pVM = TRPM2VM(pTrpm);
+    PVMCPU      pVCpu = VMMGetCpu0(pVM);
+
     LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs, pRegFrame->eip, uDr6));
 
@@ -268 +272 @@
     {
         AssertReleaseMsgFailed(("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
-                                ASMGetDR7(), CPUMGetHyperDR7(pVM), uDr6));
+                                ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6));
         return VERR_NOT_IMPLEMENTED;
     }
@@ -279 +283 @@
     int rc = DBGFGCTrap01Handler(pVM, pRegFrame, uDr6);
     if (rc == VINF_EM_RAW_GUEST_TRAP)
-        CPUMSetGuestDR6(pVM, uDr6);
+        CPUMSetGuestDR6(pVCpu, uDr6);
 
     rc = trpmGCExitTrap(pVM, rc, pRegFrame);
@@ -361 +365 @@
 {
     LogFlow(("TRPMGC06: %04x:%08x efl=%x\n", pRegFrame->cs, pRegFrame->eip, pRegFrame->eflags.u32));
-    PVM pVM = TRPM2VM(pTrpm);
-    int rc;
-
-    if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
+    PVM     pVM = TRPM2VM(pTrpm);
+    PVMCPU  pVCpu = VMMGetCpu0(pVM);
+    int     rc;
+
+    if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
     {
         /*
@@ -381 +386 @@
         DISCPUSTATE Cpu;
         uint32_t    cbOp;
-        rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
+        rc = EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
         if (RT_FAILURE(rc))
         {
@@ -429 +434 @@
         {
             uint32_t cbIgnored;
-            rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, PC, &cbIgnored);
+            rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, pRegFrame, PC, &cbIgnored);
             if (RT_LIKELY(RT_SUCCESS(rc)))
                 pRegFrame->eip += Cpu.opsize;
@@ -465 +470 @@
 {
     LogFlow(("TRPMGC07: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
-    PVM pVM = TRPM2VM(pTrpm);
-
-    int rc = CPUMHandleLazyFPU(pVM, VMMGetCpu(pVM));
+    PVM     pVM   = TRPM2VM(pTrpm);
+    PVMCPU  pVCpu = VMMGetCpu0(pVM);
+
+    int rc = CPUMHandleLazyFPU(pVCpu);
     rc = trpmGCExitTrap(pVM, rc, pRegFrame);
     Log6(("TRPMGC07: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
@@ -586 +592 @@
 static int trpmGCTrap0dHandlerRing0(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
 {
-    int rc;
+    int     rc;
+    PVMCPU  pVCpu = VMMGetCpu0(pVM);
 
     /*
@@ -661 +668 @@
         {
             uint32_t cbIgnored;
-            rc = EMInterpretInstructionCPU(pVM, pCpu, pRegFrame, PC, &cbIgnored);
+            rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, &cbIgnored);
             if (RT_SUCCESS(rc))
                 pRegFrame->eip += pCpu->opsize;
@@ -688 +695 @@
 static int trpmGCTrap0dHandlerRing3(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
 {
-    int rc;
+    int     rc;
+    PVMCPU  pVCpu = VMMGetCpu0(pVM);
 
     Assert(!pRegFrame->eflags.Bits.u1VM);
@@ -740 +748 @@
         {
             uint32_t cbIgnored;
-            rc = EMInterpretInstructionCPU(pVM, pCpu, pRegFrame, PC, &cbIgnored);
+            rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, &cbIgnored);
             if (RT_SUCCESS(rc))
                 pRegFrame->eip += pCpu->opsize;
@@ -754 +762 @@
         case OP_CLI:
         {
-            uint32_t efl = CPUMRawGetEFlags(pVM, pRegFrame);
+            uint32_t efl = CPUMRawGetEFlags(pVCpu, pRegFrame);
             if (X86_EFL_GET_IOPL(efl) >= (unsigned)(pRegFrame->ss & X86_SEL_RPL))
             {
@@ -783 +791 @@
 DECLINLINE(int) trpmGCTrap0dHandlerRdTsc(PVM pVM, PCPUMCTXCORE pRegFrame)
 {
+    PVMCPU pVCpu = VMMGetCpu0(pVM);
+
     STAM_COUNTER_INC(&pVM->trpm.s.StatTrap0dRdTsc);
 
-    if (CPUMGetGuestCR4(pVM) & X86_CR4_TSD)
+    if (CPUMGetGuestCR4(pVCpu) & X86_CR4_TSD)
         return trpmGCExitTrap(pVM, VINF_EM_RAW_EMULATE_INSTR, pRegFrame); /* will trap (optimize later). */
 
@@ -809 +819 @@
 static int trpmGCTrap0dHandler(PVM pVM, PTRPM pTrpm, PCPUMCTXCORE pRegFrame)
 {
+    PVMCPU pVCpu = VMMGetCpu0(pVM);
+
     LogFlow(("trpmGCTrap0dHandler: cs:eip=%RTsel:%08RX32 uErr=%RGv\n", pRegFrame->ss, pRegFrame->eip, pTrpm->uActiveErrorCode));
 
@@ -861 +873 @@
         &&  (Cpu.pCurInstr->optype & OPTYPE_PORTIO))
     {
-        rc = EMInterpretPortIO(pVM, pRegFrame, &Cpu, cbOp);
+        rc = EMInterpretPortIO(pVM, pVCpu, pRegFrame, &Cpu, cbOp);
         return trpmGCExitTrap(pVM, rc, pRegFrame);
     }
@@ -887 +899 @@
      */
     X86EFLAGS eflags;
-    eflags.u32 = CPUMRawGetEFlags(pVM, pRegFrame); /* Get the correct value. */
+    eflags.u32 = CPUMRawGetEFlags(pVCpu, pRegFrame); /* Get the correct value. */
     Log3(("TRPM #GP V86: cs:eip=%04x:%08x IOPL=%d efl=%08x\n", pRegFrame->cs, pRegFrame->eip, eflags.Bits.u2IOPL, eflags.u));
     if (eflags.Bits.u2IOPL != 3)
@@ -971 +983 @@
 {
     LogFlow(("TRPMGC0e: %04x:%08x err=%x cr2=%08x\n", pRegFrame->cs, pRegFrame->eip, (uint32_t)pTrpm->uActiveErrorCode, (uint32_t)pTrpm->uActiveCR2));
-    PVM pVM = TRPM2VM(pTrpm);
+    PVM     pVM = TRPM2VM(pTrpm);
+    PVMCPU  pVCpu = VMMGetCpu0(pVM);
 
 
@@ -977 +990 @@
      * This is all PGM stuff.
      */
-    int rc = PGMTrap0eHandler(pVM, pTrpm->uActiveErrorCode, pRegFrame, (RTGCPTR)pTrpm->uActiveCR2);
+    int rc = PGMTrap0eHandler(pVM, pVCpu, pTrpm->uActiveErrorCode, pRegFrame, (RTGCPTR)pTrpm->uActiveCR2);
     switch (rc)
     {
@@ -1235 +1248 @@
 
 
-        CPUMSetGuestCtxCore(pVM, &CtxCore);
+        CPUMSetGuestCtxCore(VMMGetCpu0(pVM), &CtxCore);
         TRPMGCHyperReturnToHost(pVM, rc);
     }