- Timestamp:
- May 7, 2009 9:03:15 AM (16 years ago)
- Location:
- trunk
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/pdmdev.h
r19437 r19468 1159 1159 DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCpuId,(PPDMDEVINS pDevIns)); 1160 1160 1161 /**1162 * Sends SIPI to given virtual CPU.1163 *1164 * @param pDevIns The APIC device instance.1165 * @param idCpu Virtual CPU to perform SIPI on1166 * @param iVector SIPI vector1167 */1168 DECLRCCALLBACKMEMBER(void, pfnSendSipi,(PPDMDEVINS pDevIns, VMCPUID idCpu, int iVector));1169 1170 1161 /** Just a safety precaution. */ 1171 1162 uint32_t u32TheEnd; … … 1236 1227 DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCpuId,(PPDMDEVINS pDevIns)); 1237 1228 1238 /**1239 * Sends SIPI to given virtual CPU.1240 *1241 * @param pDevIns The APIC device instance.1242 * @param idCpu Virtual CPU to perform SIPI on1243 * @param iVector SIPI vector1244 */1245 DECLR0CALLBACKMEMBER(void, pfnSendSipi,(PPDMDEVINS pDevIns, VMCPUID idCpu, int iVector));1246 1247 1229 /** Just a safety precaution. */ 1248 1230 uint32_t u32TheEnd; … … 1319 1301 * @param iVector SIPI vector 1320 1302 */ 1321 DECLR3CALLBACKMEMBER(void, pfnSendSipi,(PPDMDEVINS pDevIns, VMCPUID idCpu, int iVector));1303 DECLR3CALLBACKMEMBER(void, pfnSendSipi,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t uVector)); 1322 1304 1323 1305 /** -
trunk/include/VBox/vmm.h
r19454 r19468 117 117 VMMDECL(uint32_t) VMMGetSvnRev(void); 118 118 VMMDECL(VMMSWITCHER) VMMGetSwitcher(PVM pVM); 119 VMMDECL(void) VMMSendSipi(PVM pVM, VMCPUID idCpu, int iVector);120 119 121 120 /** @def VMMIsHwVirtExtForced … … 160 159 VMMR3DECL(void) VMMR3YieldStop(PVM pVM); 161 160 VMMR3DECL(void) VMMR3YieldResume(PVM pVM); 161 VMMR3DECL(void) VMMR3SendSipi(PVM pVM, VMCPUID idCpu, uint32_t uVector); 162 162 /** @} */ 163 163 #endif /* IN_RING3 */ -
trunk/src/VBox/Devices/PC/DevAPIC.cpp
r19443 r19468 320 320 321 321 static void apic_eoi(APICDeviceInfo *dev, APICState* s); 322 static voidapic_deliver(APICDeviceInfo* dev, APICState *s,323 324 325 322 static int apic_deliver(APICDeviceInfo* dev, APICState *s, 323 uint8_t dest, uint8_t dest_mode, 324 uint8_t delivery_mode, uint8_t vector_num, 325 uint8_t polarity, uint8_t trigger_mode); 326 326 static void apic_timer_update(APICDeviceInfo* dev, APICState *s, 327 327 int64_t current_time); … … 363 363 getCpuFromLapic(dev, s)); 364 364 } 365 365 #ifdef IN_RING3 366 366 DECLINLINE(void) cpuSendSipi(APICDeviceInfo* dev, APICState *s, int vector) 367 367 { 368 368 Log2(("apic: send SIPI vector=%d\n", vector)); 369 dev->CTX_SUFF(pApicHlp)->pfnSendSipi(dev->CTX_SUFF(pDevIns), 370 getCpuFromLapic(dev, s),371 vector);372 } 373 374 369 370 dev->pApicHlpR3->pfnSendSipi(dev->pDevInsR3, 371 getCpuFromLapic(dev, s), 372 vector); 373 } 374 #endif 375 375 376 376 DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev) … … 672 672 { 673 673 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *); 674 int rv = VINF_SUCCESS; 674 675 675 676 if (dev->enmVersion < PDMAPICVERSION_X2APIC) … … 677 678 678 679 uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff; 679 //LogRel(("nike: WRMSR on %d: to %x written %llx\n", idCpu, index, u64Value));680 680 681 681 APICState* apic = getLapicById(dev, idCpu); … … 718 718 apic->icr[0] = (uint32_t)u64Value; 719 719 apic->icr[1] = (uint32_t)(u64Value >> 32); 720 apic_deliver(dev, apic, (apic->icr[1] >> 24) & 0xff, (apic->icr[0] >> 11) & 1,721 (apic->icr[0] >> 8) & 7, (apic->icr[0] & 0xff),722 (apic->icr[0] >> 14) & 1, (apic->icr[0] >> 15) & 1);720 rv = apic_deliver(dev, apic, (apic->icr[1] >> 24) & 0xff, (apic->icr[0] >> 11) & 1, 721 (apic->icr[0] >> 8) & 7, (apic->icr[0] & 0xff), 722 (apic->icr[0] >> 14) & 1, (apic->icr[0] >> 15) & 1); 723 723 break; 724 724 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: … … 764 764 } 765 765 766 return VINF_SUCCESS;766 return rv; 767 767 } 768 768 PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value) … … 774 774 775 775 uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff; 776 //LogRel(("nike: RDMSR on %d: read from %x\n", idCpu, index));777 776 APICState* apic = getLapicById(dev, idCpu); 778 777 uint64_t val = 0; … … 1081 1080 } 1082 1081 1083 1082 #ifdef IN_RING3 1084 1083 /* send a SIPI message to the CPU to start it */ 1085 1084 static void apic_startup(APICDeviceInfo* dev, APICState *s, int vector_num) … … 1099 1098 #endif 1100 1099 } 1101 static void apic_deliver(APICDeviceInfo* dev, APICState *s, 1100 #endif 1101 1102 static int apic_deliver(APICDeviceInfo* dev, APICState *s, 1102 1103 uint8_t dest, uint8_t dest_mode, 1103 1104 uint8_t delivery_mode, uint8_t vector_num, … … 1144 1145 foreach_apic(dev, deliver_bitmask, 1145 1146 apic->arb_id = apic->id); 1147 return VINF_SUCCESS; 1146 1148 #else /* !VBOX */ 1147 1149 for (apic_iter = first_local_apic; apic_iter != NULL; … … 1151 1153 } 1152 1154 } 1155 return; 1153 1156 #endif /* !VBOX */ 1154 return;1155 1157 } 1156 1158 } … … 1166 1168 } 1167 1169 } 1170 return; 1168 1171 #else 1172 # ifdef IN_RING3 1173 1169 1174 foreach_apic(dev, deliver_bitmask, 1170 1175 apic_startup(dev, apic, vector_num)); 1176 return VINF_SUCCESS; 1177 # else 1178 /* We shall send SIPI only in R3, R0 calls should be 1179 rescheduled to R3 */ 1180 return VINF_IOM_HC_MMIO_WRITE; 1181 # endif 1171 1182 #endif /* !VBOX */ 1172 return;1173 1183 } 1174 1184 … … 1179 1189 apic_bus_deliver(dev, deliver_bitmask, delivery_mode, vector_num, polarity, 1180 1190 trigger_mode); 1191 return VINF_SUCCESS; 1181 1192 #endif /* VBOX */ 1182 1193 } … … 1445 1456 static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr, uint32_t val) 1446 1457 { 1458 int rv = VINF_SUCCESS; 1447 1459 #endif /* VBOX */ 1448 1460 int index; … … 1508 1520 case 0x30: 1509 1521 s->icr[0] = val; 1510 apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, 1511 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), 1512 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); 1522 rv = apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff, 1523 (s->icr[0] >> 11) & 1, 1524 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), 1525 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); 1513 1526 break; 1514 1527 case 0x31: … … 1557 1570 } 1558 1571 #ifdef VBOX 1559 return VINF_SUCCESS;1572 return rv; 1560 1573 #endif 1561 1574 } … … 2162 2175 { 2163 2176 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *); 2164 #ifdef VBOX_WITH_SMP_GUESTS2165 LogRel(("[SMP]: relocate apic on %llx\n", offDelta));2166 #endif2167 2177 dev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 2168 2178 dev->pApicHlpRC = dev->pApicHlpR3->pfnGetRCHelpers(pDevIns); … … 2737 2747 #endif /* IN_RING3 */ 2738 2748 #endif /* !VBOX_DEVICE_STRUCT_TESTCASE */ 2739 -
trunk/src/VBox/VMM/PDMDevMiscHlp.cpp
r19456 r19468 232 232 233 233 /** @copydoc PDMAPICHLPR3::pfnSendSipi */ 234 static DECLCALLBACK(void) pdmR3ApicHlp_SendSipi(PPDMDEVINS pDevIns, VMCPUID idCpu, int iVector) /** @todo why signed? */ 235 { 236 PDMDEV_ASSERT_DEVINS(pDevIns); 237 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 238 239 PVM pVM = pDevIns->Internal.s.pVMR3; 240 PVMCPU pCpu = VMMGetCpuById(pVM, idCpu); 241 CPUMSetGuestCS(pCpu, iVector * 0x100); 242 CPUMSetGuestEIP(pCpu, 0); 243 /** @todo: how do I unhalt VCPU? 244 * bird: See VMMSendSipi. */ 245 234 static DECLCALLBACK(void) pdmR3ApicHlp_SendSipi(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t uVector) 235 { 236 PDMDEV_ASSERT_DEVINS(pDevIns); 237 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 238 VMMR3SendSipi(pDevIns->Internal.s.pVMR3, idCpu, uVector); 246 239 } 247 240 -
trunk/src/VBox/VMM/VMMAll/VMMAll.cpp
r19450 r19468 99 99 # endif 100 100 } 101 #endif /* IN_RING3 */102 103 101 104 102 /** … … 108 106 * @param pVM The VM to operate on. 109 107 * @param idCpu Virtual CPU to perform SIPI on 110 * @param iVector SIPI vector111 */ 112 VMM DECL(void) VMMSendSipi(PVM pVM, VMCPUID idCpu, int iVector) /** @todo why is iVector signed? */108 * @param uVector SIPI vector 109 */ 110 VMMR3DECL(void) VMMR3SendSipi(PVM pVM, VMCPUID idCpu, uint32_t uVector) 113 111 { 114 112 AssertReturnVoid(idCpu < pVM->cCPUs); 115 113 116 #ifdef IN_RING3117 114 PVMREQ pReq; 118 115 int rc = VMR3ReqCallU(pVM->pUVM, idCpu, &pReq, RT_INDEFINITE_WAIT, 0, 119 (PFNRT)vmmR3SendSipi, 3, pVM, idCpu, (uint32_t)iVector);116 (PFNRT)vmmR3SendSipi, 3, pVM, idCpu, uVector); 120 117 AssertRC(rc); 121 118 VMR3ReqFree(pReq); 122 #else 123 AssertMsgFailed(("has to be done in ring-3, fix the code.\n")); 124 #endif 125 } 119 } 120 #endif /* IN_RING3 */ 126 121 127 122 -
trunk/src/VBox/VMM/VMMGC/PDMGCDevice.cpp
r19447 r19468 92 92 static DECLCALLBACK(void) pdmRCApicHlp_Unlock(PPDMDEVINS pDevIns); 93 93 static DECLCALLBACK(VMCPUID) pdmRCApicHlp_GetCpuId(PPDMDEVINS pDevIns); 94 static DECLCALLBACK(void) pdmRCApicHlp_SendSipi(PPDMDEVINS pDevIns, VMCPUID idCpu, int iVector);95 94 /** @} */ 96 95 … … 168 167 pdmRCApicHlp_Unlock, 169 168 pdmRCApicHlp_GetCpuId, 170 pdmRCApicHlp_SendSipi,171 169 PDM_APICHLPRC_VERSION 172 170 }; … … 490 488 return VMMGetCpuId(pDevIns->Internal.s.pVMRC); 491 489 } 492 493 494 /** @copydoc PDMAPICHLPRC::pfnSendSipi */495 static DECLCALLBACK(void) pdmRCApicHlp_SendSipi(PPDMDEVINS pDevIns, VMCPUID idCpu, int iVector)496 {497 /* we shall never send a SIPI in raw mode */498 AssertFailed();499 }500 501 502 503 490 504 491 /** @copydoc PDMIOAPICHLPRC::pfnApicBusDeliver */ -
trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp
r19446 r19468 94 94 static DECLCALLBACK(void) pdmR0ApicHlp_Unlock(PPDMDEVINS pDevIns); 95 95 static DECLCALLBACK(VMCPUID) pdmR0ApicHlp_GetCpuId(PPDMDEVINS pDevIns); 96 static DECLCALLBACK(void) pdmR0ApicHlp_SendSipi(PPDMDEVINS pDevIns, VMCPUID idCpu, int iVector);97 96 /** @} */ 98 97 … … 171 170 pdmR0ApicHlp_Unlock, 172 171 pdmR0ApicHlp_GetCpuId, 173 pdmR0ApicHlp_SendSipi,174 172 PDM_APICHLPR0_VERSION 175 173 }; … … 504 502 return VMMGetCpuId(pDevIns->Internal.s.pVMR0); 505 503 } 506 507 508 /** @copydoc PDMAPICHLPR0::pfnSendSipi */509 static DECLCALLBACK(void) pdmR0ApicHlp_SendSipi(PPDMDEVINS pDevIns, VMCPUID idCpu, int iVector)510 {511 PDMDEV_ASSERT_DEVINS(pDevIns);512 return VMMSendSipi(pDevIns->Internal.s.pVMR0, idCpu, iVector);513 }514 515 516 517 518 504 519 505 /** @copydoc PDMIOAPICHLPR0::pfnApicBusDeliver */
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