Changeset 19812 in vbox for trunk/src

Timestamp:

May 19, 2009 11:54:55 AM (16 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

47462

Message:

Implemented HWACCMFlushAllTLBs

Location:

trunk/src/VBox/VMM

Files:

• HWACCM.cpp (modified) (1 diff)
• HWACCMInternal.h (modified) (1 diff)
• VMMAll/HWACCMAll.cpp (modified) (1 diff)
• VMMR0/HWSVMR0.cpp (modified) (4 diffs)
• VMMR0/HWVMXR0.cpp (modified) (5 diffs)

trunk/src/VBox/VMM/HWACCM.cpp

@@ -351 +351 @@
         HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID,              "/HWACCM/CPU%d/Flush/TLB/ASID");
         HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga,        "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
-        HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown,           "/HWACCM/CPU%d/Flush/TLB/Shootdown");
+        HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown,           "/HWACCM/CPU%d/Flush/Shootdown/Page");
+        HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush,      "/HWACCM/CPU%d/Flush/Shootdown/TLB");
         
         HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset,              "/HWACCM/CPU%d/TSC/Offset");

trunk/src/VBox/VMM/HWACCMInternal.h

@@ -641 +641 @@
     STAMCOUNTER             StatFlushTLBInvlpga;
     STAMCOUNTER             StatTlbShootdown;
+    STAMCOUNTER             StatTlbShootdownFlush;
 
     STAMCOUNTER             StatSwitchGuestIrq;

trunk/src/VBox/VMM/VMMAll/HWACCMAll.cpp

@@ -80 +80 @@
 }
 
+#ifndef IN_RC
+/**
+ * Flush the TLBs of all VCPUs
+ *
+ * @returns VBox status code.
+ * @param   pVM       The VM to operate on.
+ */
+VMMDECL(int) HWACCMFlushAllTLBs(PVM pVM)
+{
+    if (pVM->cCPUs == 1)
+        return HWACCMFlushTLB(&pVM->aCpus[0]);
+
+    VMCPUID idThisCpu = VMMGetCpuId(pVM);
+
+    for (unsigned idCpu = 0; idCpu < pVM->cCPUs; idCpu++)
+    {
+        PVMCPU pVCpu = &pVM->aCpus[idCpu];
+
+        VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
+        if (idThisCpu == idCpu)
+            continue;
+
+        if (VMCPU_GET_STATE(pVCpu) == VMCPUSTATE_STARTED_EXEC)
+        {
+            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdownFlush);
+#ifdef IN_RING0
+            RTMpPokeCpu(idCpu);
+#else
+            VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
+#endif
+        }
+        else
+            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBManual);
+    }
+    return VINF_SUCCESS;
+}
+#endif
+
 /**
  * Checks if nested paging is enabled

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -914 +914 @@
     }
 
-    VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
-
     /* When external interrupts are pending, we should exit the VM when IF is set. */
     /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
@@ -987 +985 @@
         goto end;
     }
+
+    /* Disable interrupts to make sure a poke will interrupt execution. 
+     * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
+     */
+    RTCCUINTREG uFlags = ASMIntDisableFlags();
+    VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
 
     pCpu = HWACCMR0GetCurrentCpu();
@@ -1002 +1006 @@
 
     pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
+
+    /* Check for tlb shootdown flushes. */
+    if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
+        pVCpu->hwaccm.s.fForceTLBFlush = true;
 
     /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
@@ -1073 +1081 @@
     TMNotifyEndOfExecution(pVCpu);
     VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
+    ASMSetFlags(uFlags);
     STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
 

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -1828 +1828 @@
         Assert(!pCpu->fFlushTLB);
 
+    /* Check for tlb shootdown flushes. */
+    if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
+        pVCpu->hwaccm.s.fForceTLBFlush = true;
+
     pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
     pCpu->fFlushTLB           = false;
@@ -1887 +1891 @@
 
     pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
+
+    /* Check for tlb shootdown flushes. */
+    if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
+        pVCpu->hwaccm.s.fForceTLBFlush = true;
 
     /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
@@ -2107 +2115 @@
     /** @todo check timers?? */
 
-    VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
-
     /* TPR caching using CR8 is only available in 64 bits mode */
     /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
@@ -2185 +2191 @@
     if (rc != VINF_SUCCESS)
         goto end;
+
+    /* Disable interrupts to make sure a poke will interrupt execution. 
+     * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
+     */
+    RTCCUINTREG uFlags = ASMIntDisableFlags();
+    VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
 
     /* Deal with tagged TLB setup and invalidation. */
@@ -2224 +2236 @@
     TMNotifyEndOfExecution(pVCpu);
     VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
+    ASMSetFlags(uFlags);
 
     AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));