Changeset 26157 in vbox for trunk/src/VBox
- Timestamp:
- Feb 2, 2010 6:02:15 PM (15 years ago)
- svn:sync-xref-src-repo-rev:
- 57171
- Location:
- trunk/src/VBox
- Files:
-
- 23 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r25780 r26157 2105 2105 if (fGCEnabled) 2106 2106 { 2107 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");2107 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)"); 2108 2108 if (RT_FAILURE(rc)) 2109 2109 return rc; 2110 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");2110 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)"); 2111 2111 if (RT_FAILURE(rc)) 2112 2112 return rc; -
trunk/src/VBox/Devices/EFI/DevEFI.cpp
r26110 r26157 318 318 LogRel(("EFI Panic: Unexpected trap!!\n")); 319 319 #ifdef VBOX_STRICT 320 return PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "EFI Panic: Unexpected trap during early bootstrap!\n");320 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "EFI Panic: Unexpected trap during early bootstrap!\n"); 321 321 #else 322 322 AssertReleaseMsgFailed(("Unexpected trap during early EFI bootstrap!!\n")); … … 332 332 LogRel(("EFI Panic: %s\n", pThis->szPanicMsg)); 333 333 #ifdef VBOX_STRICT 334 return PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "EFI Panic: %s\n", pThis->szPanicMsg);334 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "EFI Panic: %s\n", pThis->szPanicMsg); 335 335 #else 336 336 return VERR_INTERNAL_ERROR; … … 432 432 FwCommonPlantMpsTable(pDevIns, 433 433 pThis->au8DMIPage + VBOX_DMI_TABLE_SIZE, 434 pThis->cCpus); 434 pThis->cCpus); 435 435 436 436 /* -
trunk/src/VBox/Devices/Graphics/DevVGA.cpp
r26001 r26157 6056 6056 if (pThis->fGCEnabled) 6057 6057 { 6058 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x3c0, 16, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3c0 (GC)");6058 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x3c0, 16, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3c0 (GC)"); 6059 6059 if (RT_FAILURE(rc)) 6060 6060 return rc; 6061 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x3b4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3b4 (GC)");6061 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x3b4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3b4 (GC)"); 6062 6062 if (RT_FAILURE(rc)) 6063 6063 return rc; 6064 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x3ba, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3ba (GC)");6064 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x3ba, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3ba (GC)"); 6065 6065 if (RT_FAILURE(rc)) 6066 6066 return rc; 6067 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x3d4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3d4 (GC)");6067 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x3d4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3d4 (GC)"); 6068 6068 if (RT_FAILURE(rc)) 6069 6069 return rc; 6070 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x3da, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3da (GC)");6070 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x3da, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3da (GC)"); 6071 6071 if (RT_FAILURE(rc)) 6072 6072 return rc; 6073 6073 #ifdef CONFIG_BOCHS_VBE 6074 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x1ce, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", NULL, NULL, "VGA/VBE - Index (GC)");6074 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x1ce, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", NULL, NULL, "VGA/VBE - Index (GC)"); 6075 6075 if (RT_FAILURE(rc)) 6076 6076 return rc; 6077 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x1cf, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", NULL, NULL, "VGA/VBE - Data (GC)");6077 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x1cf, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", NULL, NULL, "VGA/VBE - Data (GC)"); 6078 6078 if (RT_FAILURE(rc)) 6079 6079 return rc; … … 6083 6083 and try to map other devices there */ 6084 6084 /* Old Bochs. */ 6085 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0xff80, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", "VGA/VBE - Index Old (GC)");6085 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0xff80, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", "VGA/VBE - Index Old (GC)"); 6086 6086 if (RT_FAILURE(rc)) 6087 6087 return rc; 6088 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0xff81, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", "VGA/VBE - Index Old (GC)");6088 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0xff81, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", "VGA/VBE - Index Old (GC)"); 6089 6089 if (RT_FAILURE(rc)) 6090 6090 return rc; … … 6141 6141 if (pThis->fGCEnabled) 6142 6142 { 6143 rc = PDMDevHlpMMIORegister GC(pDevIns, 0x000a0000, 0x00020000, 0, "vgaMMIOWrite", "vgaMMIORead", "vgaMMIOFill");6143 rc = PDMDevHlpMMIORegisterRC(pDevIns, 0x000a0000, 0x00020000, 0, "vgaMMIOWrite", "vgaMMIORead", "vgaMMIOFill"); 6144 6144 if (RT_FAILURE(rc)) 6145 6145 return rc; -
trunk/src/VBox/Devices/Input/DevPS2.cpp
r26001 r26157 1647 1647 if (fGCEnabled) 1648 1648 { 1649 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x60, 1, 0, "kbdIOPortDataWrite", "kbdIOPortDataRead", NULL, NULL, "PC Keyboard - Data");1649 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x60, 1, 0, "kbdIOPortDataWrite", "kbdIOPortDataRead", NULL, NULL, "PC Keyboard - Data"); 1650 1650 if (RT_FAILURE(rc)) 1651 1651 return rc; 1652 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x64, 1, 0, "kbdIOPortCommandWrite", "kbdIOPortStatusRead", NULL, NULL, "PC Keyboard - Command / Status");1652 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x64, 1, 0, "kbdIOPortCommandWrite", "kbdIOPortStatusRead", NULL, NULL, "PC Keyboard - Command / Status"); 1653 1653 if (RT_FAILURE(rc)) 1654 1654 return rc; -
trunk/src/VBox/Devices/Network/DevE1000.cpp
r26001 r26157 1342 1342 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=\n", 1343 1343 INSTANCE(pState), RT_SRC_POS_ARGS, rc)); 1344 PDMDev iceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,1344 PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS, 1345 1345 "%s Failed to enter critical section, rc=%Rrc\n", 1346 1346 INSTANCE(pState), rc); … … 3665 3665 case 4: mask = 0xFFFFFFFF; break; 3666 3666 default: 3667 return PDMDev iceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,3667 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS, 3668 3668 "%s e1kRegRead: unsupported op size: offset=%#10x cb=%#10x\n", 3669 3669 szInst, uOffset, cb); … … 3677 3677 mask <<= shift; 3678 3678 if (!mask) 3679 return PDMDev iceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,3679 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS, 3680 3680 "%s e1kRegRead: Zero mask: offset=%#10x cb=%#10x\n", 3681 3681 szInst, uOffset, cb); … … 3846 3846 { 3847 3847 E1kLog(("%s e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x", pDevIns, uOffset, cb)); 3848 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", uOffset, cb);3848 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", uOffset, cb); 3849 3849 } 3850 3850 else … … 3879 3879 { 3880 3880 E1kLog(("%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x", szInst, port, cb)); 3881 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);3881 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb); 3882 3882 } 3883 3883 else … … 3930 3930 { 3931 3931 E1kLog(("%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb)); 3932 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);3932 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb); 3933 3933 } 3934 3934 else … … 3953 3953 * bird: VINF_SUCCESS is fine for unhandled cases of an OUT handler. (If you're curious 3954 3954 * about the guest code and a bit adventuresome, try rc = PDMDeviceDBGFStop(...);) */ 3955 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "e1kIOPortOut: invalid port %#010x\n", port);3955 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kIOPortOut: invalid port %#010x\n", port); 3956 3956 } 3957 3957 } … … 4041 4041 if (pState->fGCEnabled) 4042 4042 { 4043 rc = PDMDevHlpIOPortRegister GC(pPciDev->pDevIns, pState->addrIOPort, cb, 0,4043 rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pState->addrIOPort, cb, 0, 4044 4044 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000"); 4045 4045 } … … 4058 4058 if (pState->fGCEnabled) 4059 4059 { 4060 rc = PDMDevHlpMMIORegister GC(pPciDev->pDevIns, GCPhysAddress, cb, 0,4060 rc = PDMDevHlpMMIORegisterRC(pPciDev->pDevIns, GCPhysAddress, cb, 0, 4061 4061 "e1kMMIOWrite", "e1kMMIORead", NULL); 4062 4062 } … … 5175 5175 5176 5176 /* Create transmit queue */ 5177 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,5178 5177 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0, 5178 e1kTxQueueConsumer, true, "E1000-Xmit", &pState->pTxQueueR3); 5179 5179 if (RT_FAILURE(rc)) 5180 5180 return rc; … … 5183 5183 5184 5184 /* Create the RX notifier signaller. */ 5185 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,5186 5185 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0, 5186 e1kCanRxQueueConsumer, true, "E1000-Rcv", &pState->pCanRxQueueR3); 5187 5187 if (RT_FAILURE(rc)) 5188 5188 return rc; … … 5283 5283 e1kHardReset(pState); 5284 5284 5285 rc = PDMDevHlp PDMThreadCreate(pDevIns, &pState->pTxThread, pState, e1kTxThread, e1kTxThreadWakeUp, 0, RTTHREADTYPE_IO, "E1000_TX");5285 rc = PDMDevHlpThreadCreate(pDevIns, &pState->pTxThread, pState, e1kTxThread, e1kTxThreadWakeUp, 0, RTTHREADTYPE_IO, "E1000_TX"); 5286 5286 if (RT_FAILURE(rc)) 5287 5287 return rc; -
trunk/src/VBox/Devices/Network/DevPCNet.cpp
r26001 r26157 3664 3664 case 4: *pu32 = pcnetIoportReadU32(pThis, Port, &rc); break; 3665 3665 default: 3666 rc = PDMDev iceDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,3666 rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, 3667 3667 "pcnetIOPortRead: unsupported op size: offset=%#10x cb=%u\n", 3668 3668 Port, cb); … … 3707 3707 case 4: rc = pcnetIoportWriteU32(pThis, Port, u32); break; 3708 3708 default: 3709 rc = PDMDev iceDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,3709 rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, 3710 3710 "pcnetIOPortWrite: unsupported op size: offset=%#10x cb=%u\n", 3711 3711 Port, cb); … … 3755 3755 case 4: *(uint32_t *)pv = pcnetMMIOReadU32(pThis, GCPhysAddr); break; 3756 3756 default: 3757 rc = PDMDev iceDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,3757 rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, 3758 3758 "pcnetMMIORead: unsupported op size: address=%RGp cb=%u\n", 3759 3759 GCPhysAddr, cb); … … 3808 3808 case 4: pcnetMMIOWriteU32(pThis, GCPhysAddr, *(uint32_t *)pv); break; 3809 3809 default: 3810 rc = PDMDev iceDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,3810 rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, 3811 3811 "pcnetMMIOWrite: unsupported op size: address=%RGp cb=%u\n", 3812 3812 GCPhysAddr, cb); … … 3936 3936 if (pThis->fGCEnabled) 3937 3937 { 3938 rc = PDMDevHlpIOPortRegister GC(pDevIns, Port, 0x10, 0, "pcnetIOPortAPromWrite",3938 rc = PDMDevHlpIOPortRegisterRC(pDevIns, Port, 0x10, 0, "pcnetIOPortAPromWrite", 3939 3939 "pcnetIOPortAPromRead", NULL, NULL, "PCNet aprom"); 3940 3940 if (RT_FAILURE(rc)) 3941 3941 return rc; 3942 rc = PDMDevHlpIOPortRegister GC(pDevIns, Port + 0x10, 0x10, 0, "pcnetIOPortWrite",3942 rc = PDMDevHlpIOPortRegisterRC(pDevIns, Port + 0x10, 0x10, 0, "pcnetIOPortWrite", 3943 3943 "pcnetIOPortRead", NULL, NULL, "PCNet"); 3944 3944 if (RT_FAILURE(rc)) … … 5160 5160 * Create the transmit queue. 5161 5161 */ 5162 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,5163 5162 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0, 5163 pcnetXmitQueueConsumer, true, "PCNet-Xmit", &pThis->pXmitQueueR3); 5164 5164 if (RT_FAILURE(rc)) 5165 5165 return rc; … … 5170 5170 * Create the RX notifer signaller. 5171 5171 */ 5172 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,5173 5172 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0, 5173 pcnetCanRxQueueConsumer, true, "PCNet-Rcv", &pThis->pCanRxQueueR3); 5174 5174 if (RT_FAILURE(rc)) 5175 5175 return rc; … … 5230 5230 5231 5231 /* Create asynchronous thread */ 5232 rc = PDMDevHlp PDMThreadCreate(pDevIns, &pThis->pSendThread, pThis, pcnetAsyncSendThread, pcnetAsyncSendThreadWakeUp, 0, RTTHREADTYPE_IO, "PCNET_TX");5232 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->pSendThread, pThis, pcnetAsyncSendThread, pcnetAsyncSendThreadWakeUp, 0, RTTHREADTYPE_IO, "PCNET_TX"); 5233 5233 AssertRCReturn(rc, rc); 5234 5234 -
trunk/src/VBox/Devices/Network/DevVirtioNet.cpp
r26055 r26157 1428 1428 NULL, NULL, "VirtioNet"); 1429 1429 AssertRCReturn(rc, rc); 1430 rc = PDMDevHlpIOPortRegister GC(pPciDev->pDevIns, pState->VPCI.addrIOPort,1430 rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pState->VPCI.addrIOPort, 1431 1431 cb, 0, "vnetIOPortOut", "vnetIOPortIn", 1432 1432 NULL, NULL, "VirtioNet"); … … 1711 1711 1712 1712 /* Create the RX notifier signaller. */ 1713 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,1714 1713 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0, 1714 vnetCanRxQueueConsumer, true, "VNet-Rcv", &pState->pCanRxQueueR3); 1715 1715 if (RT_FAILURE(rc)) 1716 1716 return rc; -
trunk/src/VBox/Devices/PC/DevACPI.cpp
r26115 r26157 471 471 [14] reserved 472 472 [13] COUNT_SIZE_CAP counter size 473 [12:8] number of comparators in first timer block 473 [12:8] number of comparators in first timer block 474 474 [7:0] hardware rev ID */ 475 475 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */ … … 1790 1790 #undef R 1791 1791 1792 /* register GC stuff */1792 /* register RC stuff */ 1793 1793 if (pThis->fGCEnabled) 1794 1794 { 1795 rc = PDMDevHlpIOPortRegister GC(pThis->pDevIns, acpiPmPort(pThis, PM_TMR_OFFSET),1795 rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, acpiPmPort(pThis, PM_TMR_OFFSET), 1796 1796 1, 0, NULL, "acpiPMTmrRead", 1797 1797 NULL, NULL, "ACPI PM Timer"); -
trunk/src/VBox/Devices/PC/DevAPIC.cpp
r25058 r26157 2914 2914 pThis->pCritSectRC = pThis->pApicHlpR3->pfnGetRCCritSect(pDevIns); 2915 2915 2916 rc = PDMDevHlpMMIORegister GC(pDevIns, ApicBase, 0x1000, 0,2916 rc = PDMDevHlpMMIORegisterRC(pDevIns, ApicBase, 0x1000, 0, 2917 2917 "apicMMIOWrite", "apicMMIORead", NULL); 2918 2918 if (RT_FAILURE(rc)) … … 3269 3269 s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns); 3270 3270 3271 rc = PDMDevHlpMMIORegister GC(pDevIns, 0xfec00000, 0x1000, 0,3271 rc = PDMDevHlpMMIORegisterRC(pDevIns, 0xfec00000, 0x1000, 0, 3272 3272 "ioapicMMIOWrite", "ioapicMMIORead", NULL); 3273 3273 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/PC/DevPIC.cpp
r24012 r26157 991 991 if (fGCEnabled) 992 992 { 993 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");993 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0"); 994 994 if (RT_FAILURE(rc)) 995 995 return rc; 996 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");996 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1"); 997 997 if (RT_FAILURE(rc)) 998 998 return rc; … … 1019 1019 { 1020 1020 RTRCPTR pDataRC = PDMINS_2_DATA_RCPTR(pDevIns); 1021 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x4d0, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[0]),1021 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d0, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[0]), 1022 1022 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr"); 1023 1023 if (RT_FAILURE(rc)) 1024 1024 return rc; 1025 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x4d1, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[1]),1025 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d1, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[1]), 1026 1026 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr"); 1027 1027 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/PC/DevPcArch.c
r25647 r26157 64 64 int rc; 65 65 NOREF(pvUser); NOREF(pDevIns); NOREF(pu32); 66 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d\n", Port, cb);66 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d\n", Port, cb); 67 67 if (rc == VINF_SUCCESS) 68 68 rc = VERR_IOM_IOPORT_UNUSED; … … 115 115 case 0xfc: 116 116 default: 117 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d u32=%#x\n", Port, cb, u32);117 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d u32=%#x\n", Port, cb, u32); 118 118 break; 119 119 } … … 122 122 } 123 123 else 124 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d u32=%#x\n", Port, cb, u32);124 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d u32=%#x\n", Port, cb, u32); 125 125 return rc; 126 126 } … … 177 177 return VINF_SUCCESS; 178 178 } 179 return PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d\n", Port, cb);179 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d\n", Port, cb); 180 180 } 181 181 … … 210 210 return VINF_SUCCESS; 211 211 } 212 return PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d u32=%#x\n", Port, cb, u32);212 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d u32=%#x\n", Port, cb, u32); 213 213 } 214 214 -
trunk/src/VBox/Devices/PC/DevPit-i8254.cpp
r24265 r26157 1052 1052 if (fGCEnabled) 1053 1053 { 1054 rc = PDMDevHlpIOPortRegister GC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");1054 rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer"); 1055 1055 if (RT_FAILURE(rc)) 1056 1056 return rc; … … 1070 1070 if (fGCEnabled) 1071 1071 { 1072 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");1072 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker"); 1073 1073 if (RT_FAILURE(rc)) 1074 1074 return rc; -
trunk/src/VBox/Devices/PC/DevRTC.cpp
r25127 r26157 962 962 if (fGCEnabled) 963 963 { 964 rc = PDMDevHlpIOPortRegister GC(pDevIns, pThis->IOPortBase, 2, 0,964 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBase, 2, 0, 965 965 "rtcIOPortWrite", "rtcIOPortRead", NULL, NULL, "MC146818 RTC/CMOS"); 966 966 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/Parallel/DevParallel.cpp
r26001 r26157 791 791 if (pThis->fGCEnabled) 792 792 { 793 rc = PDMDevHlpIOPortRegister GC(pDevIns, io_base, 8, 0, "parallelIOPortWrite",793 rc = PDMDevHlpIOPortRegisterRC(pDevIns, io_base, 8, 0, "parallelIOPortWrite", 794 794 "parallelIOPortRead", NULL, NULL, "Parallel"); 795 795 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/Samples/VBoxSampleDevice.cpp
r22985 r26157 58 58 */ 59 59 AssertMsgReturn(pDevIns->u32Version == PDM_DEVINS_VERSION, ("%#x, expected %#x\n", pDevIns->u32Version, PDM_DEVINS_VERSION), VERR_VERSION_MISMATCH); 60 AssertMsgReturn(pDevIns->pDevHlpR3->u32Version == PDM_DEVHLP _VERSION, ("%#x, expected %#x\n", pDevIns->pDevHlpR3->u32Version, PDM_DEVHLP_VERSION), VERR_VERSION_MISMATCH);60 AssertMsgReturn(pDevIns->pDevHlpR3->u32Version == PDM_DEVHLPR3_VERSION, ("%#x, expected %#x\n", pDevIns->pDevHlpR3->u32Version, PDM_DEVHLPR3_VERSION), VERR_VERSION_MISMATCH); 61 61 62 62 return VINF_SUCCESS; … … 70 70 */ 71 71 AssertLogRelMsgReturn(pDevIns->u32Version == PDM_DEVINS_VERSION, ("%#x, expected %#x\n", pDevIns->u32Version, PDM_DEVINS_VERSION), VERR_VERSION_MISMATCH); 72 AssertLogRelMsgReturn(pDevIns->pDevHlpR3->u32Version == PDM_DEVHLP _VERSION, ("%#x, expected %#x\n", pDevIns->pDevHlpR3->u32Version, PDM_DEVHLP_VERSION), VERR_VERSION_MISMATCH);72 AssertLogRelMsgReturn(pDevIns->pDevHlpR3->u32Version == PDM_DEVHLPR3_VERSION, ("%#x, expected %#x\n", pDevIns->pDevHlpR3->u32Version, PDM_DEVHLPR3_VERSION), VERR_VERSION_MISMATCH); 73 73 74 74 /* -
trunk/src/VBox/Devices/Serial/DevSerial.cpp
r26001 r26157 922 922 if (pThis->fGCEnabled) 923 923 { 924 rc = PDMDevHlpIOPortRegister GC(pDevIns, io_base, 8, 0, "serialIOPortWrite",924 rc = PDMDevHlpIOPortRegisterRC(pDevIns, io_base, 8, 0, "serialIOPortWrite", 925 925 "serialIOPortRead", NULL, NULL, "Serial"); 926 926 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/Storage/DevAHCI.cpp
r26001 r26157 2315 2315 if (pThis->fGCEnabled) 2316 2316 { 2317 rc = PDMDevHlpMMIORegister GC(pDevIns, GCPhysAddress, cb, 0,2317 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, 0, 2318 2318 "ahciMMIOWrite", "ahciMMIORead", NULL); 2319 2319 if (RT_FAILURE(rc)) … … 2354 2354 if (pThis->fGCEnabled) 2355 2355 { 2356 rc = PDMDevHlpIOPortRegister GC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,2356 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0, 2357 2357 "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake"); 2358 2358 if (RT_FAILURE(rc)) … … 6377 6377 6378 6378 /* Create the async IO thread. */ 6379 rc = PDMDevHlp PDMThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0,6380 6379 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0, 6380 RTTHREADTYPE_IO, szName); 6381 6381 if (RT_FAILURE(rc)) 6382 6382 { … … 6641 6641 * Create the transmit queue. 6642 6642 */ 6643 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(DEVPORTNOTIFIERQUEUEITEM), 30*32 /*Maximum of 30 ports multiplied with 32 tasks each port*/, 0,6644 6643 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(DEVPORTNOTIFIERQUEUEITEM), 30*32 /*Maximum of 30 ports multiplied with 32 tasks each port*/, 0, 6644 ahciNotifyQueueConsumer, true, "AHCI-Xmit", &pThis->pNotifierQueueR3); 6645 6645 if (RT_FAILURE(rc)) 6646 6646 return rc; … … 6832 6832 6833 6833 6834 rc = PDMDevHlp PDMThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0,6835 6834 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0, 6835 RTTHREADTYPE_IO, szName); 6836 6836 AssertMsgRC(rc, ("%s: Async IO Thread creation for %s failed rc=%Rrc\n", szName, rc)); 6837 6837 } … … 6931 6931 if (pThis->fGCEnabled) 6932 6932 { 6933 rc = PDMDevHlpIOPortRegister GC(pDevIns, pCtl->IOPortBase1, 8, (RTGCPTR)i,6933 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pCtl->IOPortBase1, 8, (RTGCPTR)i, 6934 6934 "ahciIOPortWrite1", "ahciIOPortRead1", NULL, NULL, "AHCI GC"); 6935 6935 if (RT_FAILURE(rc)) … … 6952 6952 if (pThis->fGCEnabled) 6953 6953 { 6954 rc = PDMDevHlpIOPortRegister GC(pDevIns, pCtl->IOPortBase2, 1, (RTGCPTR)i,6954 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pCtl->IOPortBase2, 1, (RTGCPTR)i, 6955 6955 "ahciIOPortWrite2", "ahciIOPortRead2", NULL, NULL, "AHCI GC"); 6956 6956 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/Storage/DevATA.cpp
r26049 r26157 5225 5225 if (pThis->fGCEnabled) 5226 5226 { 5227 rc2 = PDMDevHlpIOPortRegister GC(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8,5227 rc2 = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8, 5228 5228 (RTGCPTR)i, "ataBMDMAIOPortWrite", "ataBMDMAIOPortRead", NULL, NULL, "ATA Bus Master DMA"); 5229 5229 AssertRC(rc2); … … 6694 6694 if (fGCEnabled) 6695 6695 { 6696 rc = PDMDevHlpIOPortRegister GC(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTGCPTR)i,6696 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTGCPTR)i, 6697 6697 "ataIOPortWrite1", "ataIOPortRead1", "ataIOPortWriteStr1", "ataIOPortReadStr1", "ATA I/O Base 1"); 6698 6698 if (RT_FAILURE(rc)) … … 6720 6720 if (fGCEnabled) 6721 6721 { 6722 rc = PDMDevHlpIOPortRegister GC(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTGCPTR)i,6722 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTGCPTR)i, 6723 6723 "ataIOPortWrite2", "ataIOPortRead2", NULL, NULL, "ATA I/O Base 2"); 6724 6724 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/Storage/DevBusLogic.cpp
r26001 r26157 1920 1920 if (pThis->fGCEnabled) 1921 1921 { 1922 rc = PDMDevHlpMMIORegister GC(pDevIns, GCPhysAddress, cb, 0,1922 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, 0, 1923 1923 "buslogicMMIOWrite", "buslogicMMIORead", NULL); 1924 1924 if (RT_FAILURE(rc)) … … 1945 1945 if (pThis->fGCEnabled) 1946 1946 { 1947 rc = PDMDevHlpIOPortRegister GC(pDevIns, (RTIOPORT)GCPhysAddress, 32,1947 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, 32, 1948 1948 0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic"); 1949 1949 if (RT_FAILURE(rc)) … … 2608 2608 2609 2609 /* Intialize task queue. */ 2610 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 5, 0,2611 2610 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 5, 0, 2611 buslogicNotifyQueueConsumer, true, "BugLogicTask", &pThis->pNotifierQueueR3); 2612 2612 if (RT_FAILURE(rc)) 2613 2613 return rc; -
trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp
r26001 r26157 3666 3666 if (pThis->fGCEnabled) 3667 3667 { 3668 rc = PDMDevHlpMMIORegister GC(pDevIns, GCPhysAddress, cb, 0,3668 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, 0, 3669 3669 "lsilogicMMIOWrite", "lsilogicMMIORead", NULL); 3670 3670 if (RT_FAILURE(rc)) … … 3692 3692 if (pThis->fGCEnabled) 3693 3693 { 3694 rc = PDMDevHlpMMIORegister GC(pDevIns, GCPhysAddress, cb, 0,3694 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, 0, 3695 3695 "lsilogicDiagnosticWrite", "lsilogicDiagnosticRead", NULL); 3696 3696 if (RT_FAILURE(rc)) … … 3715 3715 if (pThis->fGCEnabled) 3716 3716 { 3717 rc = PDMDevHlpIOPortRegister GC(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,3717 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE, 3718 3718 0, "lsilogicIOPortWrite", "lsilogicIOPortRead", NULL, NULL, "LsiLogic"); 3719 3719 if (RT_FAILURE(rc)) … … 4501 4501 4502 4502 /* Intialize task queue. */ 4503 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 2, 0,4504 4503 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 2, 0, 4504 lsilogicNotifyQueueConsumer, true, "LsiLogic-Task", &pThis->pNotificationQueueR3); 4505 4505 if (RT_FAILURE(rc)) 4506 4506 return rc; -
trunk/src/VBox/Devices/Storage/VBoxSCSI.cpp
r21321 r26157 192 192 /* This is a read from the device. */ 193 193 ASMAtomicXchgBool(&pVBoxSCSI->fBusy, true); 194 rc = VERR_MORE_DATA; /* @todo:Better return value to indicate ready command? */194 rc = VERR_MORE_DATA; /** @todo Better return value to indicate ready command? */ 195 195 } 196 196 } … … 308 308 RTGCPTR GCDst = *pGCPtrDst; 309 309 uint32_t cbTransfer = *pcTransfer * cb; 310 int rc = VINF_SUCCESS;311 310 312 311 LogFlowFunc(("pDevIns=%#p pVBoxSCSI=%#p iRegister=%d cTransfer=%u cb=%u\n", … … 317 316 Assert(pVBoxSCSI->pBuf); 318 317 319 rc = PGMPhysSimpleDirtyWriteGCPtr(PDMDevHlpGetVMCPU(pDevIns), GCDst, pVBoxSCSI->pBuf, cbTransfer);318 int rc = PGMPhysSimpleDirtyWriteGCPtr(PDMDevHlpGetVMCPU(pDevIns), GCDst, pVBoxSCSI->pBuf, cbTransfer); 320 319 AssertRC(rc); 321 320 … … 337 336 338 337 int vboxscsiWriteString(PPDMDEVINS pDevIns, PVBOXSCSI pVBoxSCSI, uint8_t iRegister, 339 RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb)338 RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb) 340 339 { 341 340 RTGCPTR GCSrc = *pGCPtrSrc; 342 341 uint32_t cbTransfer = *pcTransfer * cb; 343 int rc = VINF_SUCCESS;344 342 345 343 /* Read string only valid for data in register. */ … … 347 345 AssertMsg(cbTransfer == 512, ("Only 512 byte transfers are allowed\n")); 348 346 349 rc = PGMPhysSimpleReadGCPtr(PDMDevHlpGetVMCPU(pDevIns), pVBoxSCSI->pBuf, GCSrc, cbTransfer); 347 348 int rc = PDMDevHlpPhysReadGCVirt(pDevIns, pVBoxSCSI->pBuf, GCSrc, cbTransfer); 350 349 AssertRC(rc); 351 350 -
trunk/src/VBox/Devices/VirtIO/Virtio.cpp
r25985 r26157 378 378 { 379 379 *pu32 = 0xFFFFFFFF; 380 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: "380 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: " 381 381 "no valid port at offset port=%RTiop " 382 382 "cb=%08x\n", szInst, port, cb); … … 513 513 rc = pfnSetConfig(pState, port - VPCI_CONFIG, cb, &u32); 514 514 else 515 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset port=%RTiop cb=%08x\n", szInst, port, cb);515 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset port=%RTiop cb=%08x\n", szInst, port, cb); 516 516 break; 517 517 } -
trunk/src/VBox/VMM/PDMDevHlp.cpp
r26152 r26157 88 88 89 89 90 /** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegister GC} */91 static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegister GC(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts, RTRCPTR pvUser,90 /** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegisterRC} */ 91 static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterRC(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts, RTRCPTR pvUser, 92 92 const char *pszOut, const char *pszIn, 93 93 const char *pszOutStr, const char *pszInStr, const char *pszDesc) … … 95 95 PDMDEV_ASSERT_DEVINS(pDevIns); 96 96 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 97 LogFlow(("pdmR3DevHlp_IOPortRegister : caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance,97 LogFlow(("pdmR3DevHlp_IOPortRegisterRC: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, 98 98 Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc)); 99 99 … … 150 150 } 151 151 152 LogFlow(("pdmR3DevHlp_IOPortRegister GC: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));152 LogFlow(("pdmR3DevHlp_IOPortRegisterRC: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 153 153 return rc; 154 154 } … … 255 255 256 256 257 /** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegister GC} */258 static DECLCALLBACK(int) pdmR3DevHlp_MMIORegister GC(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTGCPTR pvUser,257 /** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegisterRC} */ 258 static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterRC(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTGCPTR pvUser, 259 259 const char *pszWrite, const char *pszRead, const char *pszFill, 260 260 const char *pszDesc) … … 262 262 PDMDEV_ASSERT_DEVINS(pDevIns); 263 263 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 264 LogFlow(("pdmR3DevHlp_MMIORegister GC: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n",264 LogFlow(("pdmR3DevHlp_MMIORegisterRC: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n", 265 265 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill)); 266 266 … … 308 308 } 309 309 310 LogFlow(("pdmR3DevHlp_MMIORegister GC: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));310 LogFlow(("pdmR3DevHlp_MMIORegisterRC: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 311 311 return rc; 312 312 } … … 382 382 383 383 384 /** 385 * @copydoc PDMDEVHLPR3::pfnMMIO2Register 386 */ 387 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Register(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc) 388 { 389 PDMDEV_ASSERT_DEVINS(pDevIns); 390 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 391 LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: iRegion=%#x cb=%#RGp fFlags=%RX32 ppv=%p pszDescp=%p:{%s}\n", 392 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, cb, fFlags, ppv, pszDesc, pszDesc)); 393 394 /** @todo PGMR3PhysMMIO2Register mangles the description, move it here and 395 * use a real string cache. */ 396 int rc = PGMR3PhysMMIO2Register(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, cb, fFlags, ppv, pszDesc); 397 398 LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 399 return rc; 400 } 401 402 403 /** 404 * @copydoc PDMDEVHLPR3::pfnMMIO2Deregister 405 */ 406 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Deregister(PPDMDEVINS pDevIns, uint32_t iRegion) 407 { 408 PDMDEV_ASSERT_DEVINS(pDevIns); 409 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 410 LogFlow(("pdmR3DevHlp_MMIO2Deregister: caller='%s'/%d: iRegion=%#x\n", 411 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion)); 412 413 AssertReturn(iRegion == UINT32_MAX, VERR_INVALID_PARAMETER); 414 415 int rc = PGMR3PhysMMIO2Deregister(pDevIns->Internal.s.pVMR3, pDevIns, iRegion); 416 417 LogFlow(("pdmR3DevHlp_MMIO2Deregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 418 return rc; 419 } 420 421 422 /** 423 * @copydoc PDMDEVHLPR3::pfnMMIO2Map 424 */ 425 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Map(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys) 426 { 427 PDMDEV_ASSERT_DEVINS(pDevIns); 428 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 429 LogFlow(("pdmR3DevHlp_MMIO2Map: caller='%s'/%d: iRegion=%#x GCPhys=%#RGp\n", 430 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, GCPhys)); 431 432 int rc = PGMR3PhysMMIO2Map(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, GCPhys); 433 434 LogFlow(("pdmR3DevHlp_MMIO2Map: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 435 return rc; 436 } 437 438 439 /** 440 * @copydoc PDMDEVHLPR3::pfnMMIO2Unmap 441 */ 442 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Unmap(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys) 443 { 444 PDMDEV_ASSERT_DEVINS(pDevIns); 445 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 446 LogFlow(("pdmR3DevHlp_MMIO2Unmap: caller='%s'/%d: iRegion=%#x GCPhys=%#RGp\n", 447 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, GCPhys)); 448 449 int rc = PGMR3PhysMMIO2Unmap(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, GCPhys); 450 451 LogFlow(("pdmR3DevHlp_MMIO2Unmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 452 return rc; 453 } 454 455 456 /** 457 * @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2 458 */ 459 static DECLCALLBACK(int) pdmR3DevHlp_MMHyperMapMMIO2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, 460 const char *pszDesc, PRTRCPTR pRCPtr) 461 { 462 PDMDEV_ASSERT_DEVINS(pDevIns); 463 PVM pVM = pDevIns->Internal.s.pVMR3; 464 VM_ASSERT_EMT(pVM); 465 LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: iRegion=%#x off=%RGp cb=%RGp pszDesc=%p:{%s} pRCPtr=%p\n", 466 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, off, cb, pszDesc, pszDesc, pRCPtr)); 467 468 if (pDevIns->iInstance > 0) 469 { 470 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance); 471 if (pszDesc2) 472 pszDesc = pszDesc2; 473 } 474 475 int rc = MMR3HyperMapMMIO2(pVM, pDevIns, iRegion, off, cb, pszDesc, pRCPtr); 476 477 LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: returns %Rrc *pRCPtr=%RRv\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, *pRCPtr)); 478 return rc; 479 } 480 481 482 /** 483 * @copydoc PDMDEVHLPR3::pfnMMIO2MapKernel 484 */ 485 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2MapKernel(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, 486 const char *pszDesc, PRTR0PTR pR0Ptr) 487 { 488 PDMDEV_ASSERT_DEVINS(pDevIns); 489 PVM pVM = pDevIns->Internal.s.pVMR3; 490 VM_ASSERT_EMT(pVM); 491 LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: iRegion=%#x off=%RGp cb=%RGp pszDesc=%p:{%s} pR0Ptr=%p\n", 492 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, off, cb, pszDesc, pszDesc, pR0Ptr)); 493 494 if (pDevIns->iInstance > 0) 495 { 496 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance); 497 if (pszDesc2) 498 pszDesc = pszDesc2; 499 } 500 501 int rc = PGMR3PhysMMIO2MapKernel(pVM, pDevIns, iRegion, off, cb, pszDesc, pR0Ptr); 502 503 LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: returns %Rrc *pR0Ptr=%RHv\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, *pR0Ptr)); 504 return rc; 505 } 506 507 384 508 /** @interface_method_impl{PDMDEVHLPR3,pfnROMRegister} */ 385 509 static DECLCALLBACK(int) pdmR3DevHlp_ROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, const void *pvBinary, uint32_t fFlags, const char *pszDesc) … … 394 518 395 519 LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 520 return rc; 521 } 522 523 524 /** @interface_method_impl{PDMDEVHLPR3,pfnROMProtectShadow} */ 525 static DECLCALLBACK(int) pdmR3DevHlp_ROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, PGMROMPROT enmProt) 526 { 527 PDMDEV_ASSERT_DEVINS(pDevIns); 528 LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x enmProt=%d\n", 529 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange, enmProt)); 530 531 int rc = PGMR3PhysRomProtect(pDevIns->Internal.s.pVMR3, GCPhysStart, cbRange, enmProt); 532 533 LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 396 534 return rc; 397 535 } … … 444 582 LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 445 583 return rc; 584 } 585 586 587 /** @interface_method_impl{PDMDEVHLPR3,pfnUTCNow} */ 588 static DECLCALLBACK(PRTTIMESPEC) pdmR3DevHlp_UTCNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime) 589 { 590 PDMDEV_ASSERT_DEVINS(pDevIns); 591 LogFlow(("pdmR3DevHlp_UTCNow: caller='%s'/%d: pTime=%p\n", 592 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pTime)); 593 594 pTime = TMR3UTCNow(pDevIns->Internal.s.pVMR3, pTime); 595 596 LogFlow(("pdmR3DevHlp_UTCNow: caller='%s'/%d: returns %RU64\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, RTTimeSpecGetNano(pTime))); 597 return pTime; 598 } 599 600 601 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysRead} */ 602 static DECLCALLBACK(int) pdmR3DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead) 603 { 604 PDMDEV_ASSERT_DEVINS(pDevIns); 605 PVM pVM = pDevIns->Internal.s.pVMR3; 606 LogFlow(("pdmR3DevHlp_PhysRead: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n", 607 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, pvBuf, cbRead)); 608 609 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 610 if (!VM_IS_EMT(pVM)) 611 { 612 char szNames[128]; 613 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames)); 614 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames)); 615 } 616 #endif 617 618 int rc; 619 if (VM_IS_EMT(pVM)) 620 rc = PGMPhysRead(pVM, GCPhys, pvBuf, cbRead); 621 else 622 rc = PGMR3PhysReadExternal(pVM, GCPhys, pvBuf, cbRead); 623 624 Log(("pdmR3DevHlp_PhysRead: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 625 return rc; 626 } 627 628 629 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysWrite} */ 630 static DECLCALLBACK(int) pdmR3DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite) 631 { 632 PDMDEV_ASSERT_DEVINS(pDevIns); 633 PVM pVM = pDevIns->Internal.s.pVMR3; 634 LogFlow(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n", 635 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, pvBuf, cbWrite)); 636 637 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 638 if (!VM_IS_EMT(pVM)) 639 { 640 char szNames[128]; 641 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames)); 642 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames)); 643 } 644 #endif 645 646 int rc; 647 if (VM_IS_EMT(pVM)) 648 rc = PGMPhysWrite(pVM, GCPhys, pvBuf, cbWrite); 649 else 650 rc = PGMR3PhysWriteExternal(pVM, GCPhys, pvBuf, cbWrite, pDevIns->pDevReg->szDeviceName); 651 652 Log(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 653 return rc; 654 } 655 656 657 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtr} */ 658 static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock) 659 { 660 PDMDEV_ASSERT_DEVINS(pDevIns); 661 PVM pVM = pDevIns->Internal.s.pVMR3; 662 LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n", 663 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock)); 664 AssertReturn(!fFlags, VERR_INVALID_PARAMETER); 665 666 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 667 if (!VM_IS_EMT(pVM)) 668 { 669 char szNames[128]; 670 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames)); 671 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames)); 672 } 673 #endif 674 675 int rc = PGMR3PhysGCPhys2CCPtrExternal(pVM, GCPhys, ppv, pLock); 676 677 Log(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 678 return rc; 679 } 680 681 682 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtrReadOnly} */ 683 static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, const void **ppv, PPGMPAGEMAPLOCK pLock) 684 { 685 PDMDEV_ASSERT_DEVINS(pDevIns); 686 PVM pVM = pDevIns->Internal.s.pVMR3; 687 LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n", 688 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock)); 689 AssertReturn(!fFlags, VERR_INVALID_PARAMETER); 690 691 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 692 if (!VM_IS_EMT(pVM)) 693 { 694 char szNames[128]; 695 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames)); 696 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames)); 697 } 698 #endif 699 700 int rc = PGMR3PhysGCPhys2CCPtrReadOnlyExternal(pVM, GCPhys, ppv, pLock); 701 702 Log(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 703 return rc; 704 } 705 706 707 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysReleasePageMappingLock} */ 708 static DECLCALLBACK(void) pdmR3DevHlp_PhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock) 709 { 710 PDMDEV_ASSERT_DEVINS(pDevIns); 711 PVM pVM = pDevIns->Internal.s.pVMR3; 712 LogFlow(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: pLock=%p\n", 713 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pLock)); 714 715 PGMPhysReleasePageMappingLock(pVM, pLock); 716 717 Log(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: returns void\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 718 } 719 720 721 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysReadGCVirt} */ 722 static DECLCALLBACK(int) pdmR3DevHlp_PhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb) 723 { 724 PDMDEV_ASSERT_DEVINS(pDevIns); 725 PVM pVM = pDevIns->Internal.s.pVMR3; 726 VM_ASSERT_EMT(pVM); 727 LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: pvDst=%p GCVirt=%RGv cb=%#x\n", 728 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pvDst, GCVirtSrc, cb)); 729 730 PVMCPU pVCpu = VMMGetCpu(pVM); 731 if (!pVCpu) 732 return VERR_ACCESS_DENIED; 733 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 734 /** @todo SMP. */ 735 #endif 736 737 int rc = PGMPhysSimpleReadGCPtr(pVCpu, pvDst, GCVirtSrc, cb); 738 739 LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 740 741 return rc; 742 } 743 744 745 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysWriteGCVirt} */ 746 static DECLCALLBACK(int) pdmR3DevHlp_PhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb) 747 { 748 PDMDEV_ASSERT_DEVINS(pDevIns); 749 PVM pVM = pDevIns->Internal.s.pVMR3; 750 VM_ASSERT_EMT(pVM); 751 LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: GCVirtDst=%RGv pvSrc=%p cb=%#x\n", 752 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCVirtDst, pvSrc, cb)); 753 754 PVMCPU pVCpu = VMMGetCpu(pVM); 755 if (!pVCpu) 756 return VERR_ACCESS_DENIED; 757 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 758 /** @todo SMP. */ 759 #endif 760 761 int rc = PGMPhysSimpleWriteGCPtr(pVCpu, GCVirtDst, pvSrc, cb); 762 763 LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 764 765 return rc; 766 } 767 768 769 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPtr2GCPhys} */ 770 static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys) 771 { 772 PDMDEV_ASSERT_DEVINS(pDevIns); 773 PVM pVM = pDevIns->Internal.s.pVMR3; 774 VM_ASSERT_EMT(pVM); 775 LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: GCPtr=%RGv pGCPhys=%p\n", 776 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPtr, pGCPhys)); 777 778 PVMCPU pVCpu = VMMGetCpu(pVM); 779 if (!pVCpu) 780 return VERR_ACCESS_DENIED; 781 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 782 /** @todo SMP. */ 783 #endif 784 785 int rc = PGMPhysGCPtr2GCPhys(pVCpu, GCPtr, pGCPhys); 786 787 LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: returns %Rrc *pGCPhys=%RGp\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, *pGCPhys)); 788 789 return rc; 790 } 791 792 793 /** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAlloc} */ 794 static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAlloc(PPDMDEVINS pDevIns, size_t cb) 795 { 796 PDMDEV_ASSERT_DEVINS(pDevIns); 797 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: cb=%#x\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cb)); 798 799 void *pv = MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb); 800 801 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns %p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pv)); 802 return pv; 803 } 804 805 806 /** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAllocZ} */ 807 static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb) 808 { 809 PDMDEV_ASSERT_DEVINS(pDevIns); 810 LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: cb=%#x\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cb)); 811 812 void *pv = MMR3HeapAllocZ(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb); 813 814 LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: returns %p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pv)); 815 return pv; 816 } 817 818 819 /** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapFree} */ 820 static DECLCALLBACK(void) pdmR3DevHlp_MMHeapFree(PPDMDEVINS pDevIns, void *pv) 821 { 822 PDMDEV_ASSERT_DEVINS(pDevIns); 823 LogFlow(("pdmR3DevHlp_MMHeapFree: caller='%s'/%d: pv=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pv)); 824 825 MMR3HeapFree(pv); 826 827 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns void\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 828 } 829 830 831 /** @interface_method_impl{PDMDEVHLPR3,pfnVMState} */ 832 static DECLCALLBACK(VMSTATE) pdmR3DevHlp_VMState(PPDMDEVINS pDevIns) 833 { 834 PDMDEV_ASSERT_DEVINS(pDevIns); 835 836 VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3); 837 838 LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %d (%s)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, 839 enmVMState, VMR3GetStateName(enmVMState))); 840 return enmVMState; 841 } 842 843 844 /** @interface_method_impl{PDMDEVHLPR3,pfnVMTeleportedAndNotFullyResumedYet} */ 845 static DECLCALLBACK(bool) pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns) 846 { 847 PDMDEV_ASSERT_DEVINS(pDevIns); 848 849 bool fRc = VMR3TeleportedAndNotFullyResumedYet(pDevIns->Internal.s.pVMR3); 850 851 LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %RTbool\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, 852 fRc)); 853 return fRc; 854 } 855 856 857 /** @interface_method_impl{PDMDEVHLPR3,pfnVMSetError} */ 858 static DECLCALLBACK(int) pdmR3DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) 859 { 860 PDMDEV_ASSERT_DEVINS(pDevIns); 861 va_list args; 862 va_start(args, pszFormat); 863 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2); 864 va_end(args); 865 return rc; 866 } 867 868 869 /** @interface_method_impl{PDMDEVHLPR3,pfnVMSetErrorV} */ 870 static DECLCALLBACK(int) pdmR3DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) 871 { 872 PDMDEV_ASSERT_DEVINS(pDevIns); 873 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2); 874 return rc; 875 } 876 877 878 /** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeError} */ 879 static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...) 880 { 881 PDMDEV_ASSERT_DEVINS(pDevIns); 882 va_list args; 883 va_start(args, pszFormat); 884 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, args); 885 va_end(args); 886 return rc; 887 } 888 889 890 /** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeErrorV} */ 891 static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va) 892 { 893 PDMDEV_ASSERT_DEVINS(pDevIns); 894 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, va); 895 return rc; 896 } 897 898 899 /** @interface_method_impl{PDMDEVHLPR3,pfnDBGFStopV} */ 900 static DECLCALLBACK(int) pdmR3DevHlp_DBGFStopV(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction, const char *pszFormat, va_list args) 901 { 902 PDMDEV_ASSERT_DEVINS(pDevIns); 903 #ifdef LOG_ENABLED 904 va_list va2; 905 va_copy(va2, args); 906 LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: pszFile=%p:{%s} iLine=%d pszFunction=%p:{%s} pszFormat=%p:{%s} (%N)\n", 907 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pszFile, pszFile, iLine, pszFunction, pszFunction, pszFormat, pszFormat, pszFormat, &va2)); 908 va_end(va2); 909 #endif 910 911 PVM pVM = pDevIns->Internal.s.pVMR3; 912 VM_ASSERT_EMT(pVM); 913 int rc = DBGFR3EventSrcV(pVM, DBGFEVENT_DEV_STOP, pszFile, iLine, pszFunction, pszFormat, args); 914 if (rc == VERR_DBGF_NOT_ATTACHED) 915 rc = VINF_SUCCESS; 916 917 LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 918 return rc; 919 } 920 921 922 /** @interface_method_impl{PDMDEVHLPR3,pfnDBGFInfoRegister} */ 923 static DECLCALLBACK(int) pdmR3DevHlp_DBGFInfoRegister(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler) 924 { 925 PDMDEV_ASSERT_DEVINS(pDevIns); 926 LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: pszName=%p:{%s} pszDesc=%p:{%s} pfnHandler=%p\n", 927 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pszName, pszName, pszDesc, pszDesc, pfnHandler)); 928 929 PVM pVM = pDevIns->Internal.s.pVMR3; 930 VM_ASSERT_EMT(pVM); 931 int rc = DBGFR3InfoRegisterDevice(pVM, pszName, pszDesc, pfnHandler, pDevIns); 932 933 LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 934 return rc; 935 } 936 937 938 /** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegister} */ 939 static DECLCALLBACK(void) pdmR3DevHlp_STAMRegister(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc) 940 { 941 PDMDEV_ASSERT_DEVINS(pDevIns); 942 PVM pVM = pDevIns->Internal.s.pVMR3; 943 VM_ASSERT_EMT(pVM); 944 945 STAM_REG(pVM, pvSample, enmType, pszName, enmUnit, pszDesc); 946 NOREF(pVM); 947 } 948 949 950 951 /** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterF} */ 952 static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility, 953 STAMUNIT enmUnit, const char *pszDesc, const char *pszName, ...) 954 { 955 PDMDEV_ASSERT_DEVINS(pDevIns); 956 PVM pVM = pDevIns->Internal.s.pVMR3; 957 VM_ASSERT_EMT(pVM); 958 959 va_list args; 960 va_start(args, pszName); 961 int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args); 962 va_end(args); 963 AssertRC(rc); 964 965 NOREF(pVM); 966 } 967 968 969 /** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterV} */ 970 static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterV(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility, 971 STAMUNIT enmUnit, const char *pszDesc, const char *pszName, va_list args) 972 { 973 PDMDEV_ASSERT_DEVINS(pDevIns); 974 PVM pVM = pDevIns->Internal.s.pVMR3; 975 VM_ASSERT_EMT(pVM); 976 977 int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args); 978 AssertRC(rc); 979 980 NOREF(pVM); 446 981 } 447 982 … … 860 1395 861 1396 862 /** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAlloc} */ 863 static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAlloc(PPDMDEVINS pDevIns, size_t cb) 864 { 865 PDMDEV_ASSERT_DEVINS(pDevIns); 866 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: cb=%#x\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cb)); 867 868 void *pv = MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb); 869 870 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns %p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pv)); 871 return pv; 872 } 873 874 875 /** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAllocZ} */ 876 static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb) 877 { 878 PDMDEV_ASSERT_DEVINS(pDevIns); 879 LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: cb=%#x\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cb)); 880 881 void *pv = MMR3HeapAllocZ(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb); 882 883 LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: returns %p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pv)); 884 return pv; 885 } 886 887 888 /** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapFree} */ 889 static DECLCALLBACK(void) pdmR3DevHlp_MMHeapFree(PPDMDEVINS pDevIns, void *pv) 890 { 891 PDMDEV_ASSERT_DEVINS(pDevIns); 892 LogFlow(("pdmR3DevHlp_MMHeapFree: caller='%s'/%d: pv=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pv)); 893 894 MMR3HeapFree(pv); 895 896 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns void\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 897 } 898 899 900 /** @interface_method_impl{PDMDEVHLPR3,pfnVMSetError} */ 901 static DECLCALLBACK(int) pdmR3DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) 902 { 903 PDMDEV_ASSERT_DEVINS(pDevIns); 904 va_list args; 905 va_start(args, pszFormat); 906 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2); 907 va_end(args); 908 return rc; 909 } 910 911 912 /** @interface_method_impl{PDMDEVHLPR3,pfnVMSetErrorV} */ 913 static DECLCALLBACK(int) pdmR3DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) 914 { 915 PDMDEV_ASSERT_DEVINS(pDevIns); 916 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2); 917 return rc; 918 } 919 920 921 /** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeError} */ 922 static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...) 923 { 924 PDMDEV_ASSERT_DEVINS(pDevIns); 925 va_list args; 926 va_start(args, pszFormat); 927 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, args); 928 va_end(args); 929 return rc; 930 } 931 932 933 /** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeErrorV} */ 934 static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va) 935 { 936 PDMDEV_ASSERT_DEVINS(pDevIns); 937 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, va); 938 return rc; 939 } 940 941 942 /** @interface_method_impl{PDMDEVHLPR3,pfnVMState} */ 943 static DECLCALLBACK(VMSTATE) pdmR3DevHlp_VMState(PPDMDEVINS pDevIns) 944 { 945 PDMDEV_ASSERT_DEVINS(pDevIns); 946 1397 /** @interface_method_impl{PDMDEVHLPR3,pfnQueueCreate} */ 1398 static DECLCALLBACK(int) pdmR3DevHlp_QueueCreate(PPDMDEVINS pDevIns, RTUINT cbItem, RTUINT cItems, uint32_t cMilliesInterval, 1399 PFNPDMQUEUEDEV pfnCallback, bool fGCEnabled, const char *pszName, PPDMQUEUE *ppQueue) 1400 { 1401 PDMDEV_ASSERT_DEVINS(pDevIns); 1402 LogFlow(("pdmR3DevHlp_QueueCreate: caller='%s'/%d: cbItem=%#x cItems=%#x cMilliesInterval=%u pfnCallback=%p fGCEnabled=%RTbool pszName=%p:{%s} ppQueue=%p\n", 1403 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cbItem, cItems, cMilliesInterval, pfnCallback, fGCEnabled, pszName, pszName, ppQueue)); 1404 1405 PVM pVM = pDevIns->Internal.s.pVMR3; 1406 VM_ASSERT_EMT(pVM); 1407 1408 if (pDevIns->iInstance > 0) 1409 { 1410 pszName = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s_%u", pszName, pDevIns->iInstance); 1411 AssertLogRelReturn(pszName, VERR_NO_MEMORY); 1412 } 1413 1414 int rc = PDMR3QueueCreateDevice(pVM, pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fGCEnabled, pszName, ppQueue); 1415 1416 LogFlow(("pdmR3DevHlp_QueueCreate: caller='%s'/%d: returns %Rrc *ppQueue=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, *ppQueue)); 1417 return rc; 1418 } 1419 1420 1421 /** @interface_method_impl{PDMDEVHLPR3,pfnCritSectInit} */ 1422 static DECLCALLBACK(int) pdmR3DevHlp_CritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL, 1423 const char *pszNameFmt, va_list va) 1424 { 1425 PDMDEV_ASSERT_DEVINS(pDevIns); 1426 LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: pCritSect=%p pszNameFmt=%p:{%s}\n", 1427 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pCritSect, pszNameFmt, pszNameFmt)); 1428 1429 PVM pVM = pDevIns->Internal.s.pVMR3; 1430 VM_ASSERT_EMT(pVM); 1431 int rc = pdmR3CritSectInitDevice(pVM, pDevIns, pCritSect, RT_SRC_POS, pszNameFmt, va); 1432 1433 LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 1434 return rc; 1435 } 1436 1437 1438 /** @interface_method_impl{PDMDEVHLPR3,pfnThreadCreate} */ 1439 static DECLCALLBACK(int) pdmR3DevHlp_ThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread, 1440 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName) 1441 { 1442 PDMDEV_ASSERT_DEVINS(pDevIns); 1443 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1444 LogFlow(("pdmR3DevHlp_ThreadCreate: caller='%s'/%d: ppThread=%p pvUser=%p pfnThread=%p pfnWakeup=%p cbStack=%#zx enmType=%d pszName=%p:{%s}\n", 1445 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName, pszName)); 1446 1447 int rc = pdmR3ThreadCreateDevice(pDevIns->Internal.s.pVMR3, pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName); 1448 1449 LogFlow(("pdmR3DevHlp_ThreadCreate: caller='%s'/%d: returns %Rrc *ppThread=%RTthrd\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, 1450 rc, *ppThread)); 1451 return rc; 1452 } 1453 1454 1455 /** @interface_method_impl{PDMDEVHLPR3,pfnSetAsyncNotification} */ 1456 static DECLCALLBACK(int) pdmR3DevHlp_SetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify) 1457 { 1458 PDMDEV_ASSERT_DEVINS(pDevIns); 1459 VM_ASSERT_EMT0(pDevIns->Internal.s.pVMR3); 1460 LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: pfnAsyncNotify=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pfnAsyncNotify)); 1461 1462 int rc = VINF_SUCCESS; 1463 AssertStmt(pfnAsyncNotify, rc = VERR_INVALID_PARAMETER); 1464 AssertStmt(!pDevIns->Internal.s.pfnAsyncNotify, rc = VERR_WRONG_ORDER); 1465 AssertStmt(pDevIns->Internal.s.fIntFlags & (PDMDEVINSINT_FLAGS_SUSPENDED | PDMDEVINSINT_FLAGS_RESET), rc = VERR_WRONG_ORDER); 947 1466 VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3); 948 949 LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %d (%s)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, 950 enmVMState, VMR3GetStateName(enmVMState))); 951 return enmVMState; 952 } 953 954 955 /** @interface_method_impl{PDMDEVHLPR3,pfnVMTeleportedAndNotFullyResumedYet} */ 956 static DECLCALLBACK(bool) pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns) 957 { 958 PDMDEV_ASSERT_DEVINS(pDevIns); 959 960 bool fRc = VMR3TeleportedAndNotFullyResumedYet(pDevIns->Internal.s.pVMR3); 961 962 LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %RTbool\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, 963 fRc)); 964 return fRc; 1467 AssertStmt( enmVMState == VMSTATE_SUSPENDING 1468 || enmVMState == VMSTATE_SUSPENDING_EXT_LS 1469 || enmVMState == VMSTATE_SUSPENDING_LS 1470 || enmVMState == VMSTATE_RESETTING 1471 || enmVMState == VMSTATE_RESETTING_LS 1472 || enmVMState == VMSTATE_POWERING_OFF 1473 || enmVMState == VMSTATE_POWERING_OFF_LS, 1474 rc = VERR_INVALID_STATE); 1475 1476 if (RT_SUCCESS(rc)) 1477 pDevIns->Internal.s.pfnAsyncNotify = pfnAsyncNotify; 1478 1479 LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 1480 return rc; 1481 } 1482 1483 1484 /** @interface_method_impl{PDMDEVHLPR3,pfnAsyncNotificationCompleted} */ 1485 static DECLCALLBACK(void) pdmR3DevHlp_AsyncNotificationCompleted(PPDMDEVINS pDevIns) 1486 { 1487 PDMDEV_ASSERT_DEVINS(pDevIns); 1488 PVM pVM = pDevIns->Internal.s.pVMR3; 1489 1490 VMSTATE enmVMState = VMR3GetState(pVM); 1491 if ( enmVMState == VMSTATE_SUSPENDING 1492 || enmVMState == VMSTATE_SUSPENDING_EXT_LS 1493 || enmVMState == VMSTATE_SUSPENDING_LS 1494 || enmVMState == VMSTATE_RESETTING 1495 || enmVMState == VMSTATE_RESETTING_LS 1496 || enmVMState == VMSTATE_POWERING_OFF 1497 || enmVMState == VMSTATE_POWERING_OFF_LS) 1498 { 1499 LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d:\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 1500 VMR3AsyncPdmNotificationWakeupU(pVM->pUVM); 1501 } 1502 else 1503 LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d: enmVMState=%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, enmVMState)); 1504 } 1505 1506 1507 /** @interface_method_impl{PDMDEVHLPR3,pfnRTCRegister} */ 1508 static DECLCALLBACK(int) pdmR3DevHlp_RTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp) 1509 { 1510 PDMDEV_ASSERT_DEVINS(pDevIns); 1511 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1512 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: pRtcReg=%p:{.u32Version=%#x, .pfnWrite=%p, .pfnRead=%p} ppRtcHlp=%p\n", 1513 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pRtcReg, pRtcReg->u32Version, pRtcReg->pfnWrite, 1514 pRtcReg->pfnWrite, ppRtcHlp)); 1515 1516 /* 1517 * Validate input. 1518 */ 1519 if (pRtcReg->u32Version != PDM_RTCREG_VERSION) 1520 { 1521 AssertMsgFailed(("u32Version=%#x expected %#x\n", pRtcReg->u32Version, 1522 PDM_RTCREG_VERSION)); 1523 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (version)\n", 1524 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER)); 1525 return VERR_INVALID_PARAMETER; 1526 } 1527 if ( !pRtcReg->pfnWrite 1528 || !pRtcReg->pfnRead) 1529 { 1530 Assert(pRtcReg->pfnWrite); 1531 Assert(pRtcReg->pfnRead); 1532 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (callbacks)\n", 1533 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER)); 1534 return VERR_INVALID_PARAMETER; 1535 } 1536 1537 if (!ppRtcHlp) 1538 { 1539 Assert(ppRtcHlp); 1540 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (ppRtcHlp)\n", 1541 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER)); 1542 return VERR_INVALID_PARAMETER; 1543 } 1544 1545 /* 1546 * Only one DMA device. 1547 */ 1548 PVM pVM = pDevIns->Internal.s.pVMR3; 1549 if (pVM->pdm.s.pRtc) 1550 { 1551 AssertMsgFailed(("Only one RTC device is supported!\n")); 1552 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n", 1553 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER)); 1554 return VERR_INVALID_PARAMETER; 1555 } 1556 1557 /* 1558 * Allocate and initialize pci bus structure. 1559 */ 1560 int rc = VINF_SUCCESS; 1561 PPDMRTC pRtc = (PPDMRTC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pRtc)); 1562 if (pRtc) 1563 { 1564 pRtc->pDevIns = pDevIns; 1565 pRtc->Reg = *pRtcReg; 1566 pVM->pdm.s.pRtc = pRtc; 1567 1568 /* set the helper pointer. */ 1569 *ppRtcHlp = &g_pdmR3DevRtcHlp; 1570 Log(("PDM: Registered RTC device '%s'/%d pDevIns=%p\n", 1571 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDevIns)); 1572 } 1573 else 1574 rc = VERR_NO_MEMORY; 1575 1576 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n", 1577 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 1578 return rc; 1579 } 1580 1581 1582 /** @interface_method_impl{PDMDEVHLPR3,pfnDMARegister} */ 1583 static DECLCALLBACK(int) pdmR3DevHlp_DMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser) 1584 { 1585 PDMDEV_ASSERT_DEVINS(pDevIns); 1586 PVM pVM = pDevIns->Internal.s.pVMR3; 1587 VM_ASSERT_EMT(pVM); 1588 LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: uChannel=%d pfnTransferHandler=%p pvUser=%p\n", 1589 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel, pfnTransferHandler, pvUser)); 1590 int rc = VINF_SUCCESS; 1591 if (pVM->pdm.s.pDmac) 1592 pVM->pdm.s.pDmac->Reg.pfnRegister(pVM->pdm.s.pDmac->pDevIns, uChannel, pfnTransferHandler, pvUser); 1593 else 1594 { 1595 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n")); 1596 rc = VERR_PDM_NO_DMAC_INSTANCE; 1597 } 1598 LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: returns %Rrc\n", 1599 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 1600 return rc; 1601 } 1602 1603 1604 /** @interface_method_impl{PDMDEVHLPR3,pfnDMAReadMemory} */ 1605 static DECLCALLBACK(int) pdmR3DevHlp_DMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead) 1606 { 1607 PDMDEV_ASSERT_DEVINS(pDevIns); 1608 PVM pVM = pDevIns->Internal.s.pVMR3; 1609 VM_ASSERT_EMT(pVM); 1610 LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbRead=%p\n", 1611 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbRead)); 1612 int rc = VINF_SUCCESS; 1613 if (pVM->pdm.s.pDmac) 1614 { 1615 uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnReadMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock); 1616 if (pcbRead) 1617 *pcbRead = cb; 1618 } 1619 else 1620 { 1621 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n")); 1622 rc = VERR_PDM_NO_DMAC_INSTANCE; 1623 } 1624 LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: returns %Rrc\n", 1625 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 1626 return rc; 1627 } 1628 1629 1630 /** @interface_method_impl{PDMDEVHLPR3,pfnDMAWriteMemory} */ 1631 static DECLCALLBACK(int) pdmR3DevHlp_DMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten) 1632 { 1633 PDMDEV_ASSERT_DEVINS(pDevIns); 1634 PVM pVM = pDevIns->Internal.s.pVMR3; 1635 VM_ASSERT_EMT(pVM); 1636 LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbWritten=%p\n", 1637 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbWritten)); 1638 int rc = VINF_SUCCESS; 1639 if (pVM->pdm.s.pDmac) 1640 { 1641 uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnWriteMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock); 1642 if (pcbWritten) 1643 *pcbWritten = cb; 1644 } 1645 else 1646 { 1647 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n")); 1648 rc = VERR_PDM_NO_DMAC_INSTANCE; 1649 } 1650 LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: returns %Rrc\n", 1651 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 1652 return rc; 1653 } 1654 1655 1656 /** @interface_method_impl{PDMDEVHLPR3,pfnDMASetDREQ} */ 1657 static DECLCALLBACK(int) pdmR3DevHlp_DMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel) 1658 { 1659 PDMDEV_ASSERT_DEVINS(pDevIns); 1660 PVM pVM = pDevIns->Internal.s.pVMR3; 1661 VM_ASSERT_EMT(pVM); 1662 LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: uChannel=%d uLevel=%d\n", 1663 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel, uLevel)); 1664 int rc = VINF_SUCCESS; 1665 if (pVM->pdm.s.pDmac) 1666 pVM->pdm.s.pDmac->Reg.pfnSetDREQ(pVM->pdm.s.pDmac->pDevIns, uChannel, uLevel); 1667 else 1668 { 1669 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n")); 1670 rc = VERR_PDM_NO_DMAC_INSTANCE; 1671 } 1672 LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: returns %Rrc\n", 1673 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 1674 return rc; 1675 } 1676 1677 /** @interface_method_impl{PDMDEVHLPR3,pfnDMAGetChannelMode} */ 1678 static DECLCALLBACK(uint8_t) pdmR3DevHlp_DMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel) 1679 { 1680 PDMDEV_ASSERT_DEVINS(pDevIns); 1681 PVM pVM = pDevIns->Internal.s.pVMR3; 1682 VM_ASSERT_EMT(pVM); 1683 LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: uChannel=%d\n", 1684 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel)); 1685 uint8_t u8Mode; 1686 if (pVM->pdm.s.pDmac) 1687 u8Mode = pVM->pdm.s.pDmac->Reg.pfnGetChannelMode(pVM->pdm.s.pDmac->pDevIns, uChannel); 1688 else 1689 { 1690 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n")); 1691 u8Mode = 3 << 2 /* illegal mode type */; 1692 } 1693 LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: returns %#04x\n", 1694 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, u8Mode)); 1695 return u8Mode; 1696 } 1697 1698 /** @interface_method_impl{PDMDEVHLPR3,pfnDMASchedule} */ 1699 static DECLCALLBACK(void) pdmR3DevHlp_DMASchedule(PPDMDEVINS pDevIns) 1700 { 1701 PDMDEV_ASSERT_DEVINS(pDevIns); 1702 PVM pVM = pDevIns->Internal.s.pVMR3; 1703 VM_ASSERT_EMT(pVM); 1704 LogFlow(("pdmR3DevHlp_DMASchedule: caller='%s'/%d: VM_FF_PDM_DMA %d -> 1\n", 1705 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VM_FF_ISSET(pVM, VM_FF_PDM_DMA))); 1706 1707 AssertMsg(pVM->pdm.s.pDmac, ("Configuration error: No DMAC controller available. This could be related to init order too!\n")); 1708 VM_FF_SET(pVM, VM_FF_PDM_DMA); 1709 REMR3NotifyDmaPending(pVM); 1710 VMR3NotifyGlobalFFU(pVM->pUVM, VMNOTIFYFF_FLAGS_DONE_REM); 1711 } 1712 1713 1714 /** @interface_method_impl{PDMDEVHLPR3,pfnCMOSWrite} */ 1715 static DECLCALLBACK(int) pdmR3DevHlp_CMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value) 1716 { 1717 PDMDEV_ASSERT_DEVINS(pDevIns); 1718 PVM pVM = pDevIns->Internal.s.pVMR3; 1719 VM_ASSERT_EMT(pVM); 1720 1721 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x u8Value=%#04x\n", 1722 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iReg, u8Value)); 1723 int rc; 1724 if (pVM->pdm.s.pRtc) 1725 rc = pVM->pdm.s.pRtc->Reg.pfnWrite(pVM->pdm.s.pRtc->pDevIns, iReg, u8Value); 1726 else 1727 rc = VERR_PDM_NO_RTC_INSTANCE; 1728 1729 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n", 1730 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 1731 return rc; 1732 } 1733 1734 1735 /** @interface_method_impl{PDMDEVHLPR3,pfnCMOSRead} */ 1736 static DECLCALLBACK(int) pdmR3DevHlp_CMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value) 1737 { 1738 PDMDEV_ASSERT_DEVINS(pDevIns); 1739 PVM pVM = pDevIns->Internal.s.pVMR3; 1740 VM_ASSERT_EMT(pVM); 1741 1742 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x pu8Value=%p\n", 1743 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iReg, pu8Value)); 1744 int rc; 1745 if (pVM->pdm.s.pRtc) 1746 rc = pVM->pdm.s.pRtc->Reg.pfnRead(pVM->pdm.s.pRtc->pDevIns, iReg, pu8Value); 1747 else 1748 rc = VERR_PDM_NO_RTC_INSTANCE; 1749 1750 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n", 1751 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 1752 return rc; 965 1753 } 966 1754 … … 993 1781 AssertBreakpoint(); 994 1782 return false; 995 }996 997 998 /** @interface_method_impl{PDMDEVHLPR3,pfnDBGFStopV} */999 static DECLCALLBACK(int) pdmR3DevHlp_DBGFStopV(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction, const char *pszFormat, va_list args)1000 {1001 PDMDEV_ASSERT_DEVINS(pDevIns);1002 #ifdef LOG_ENABLED1003 va_list va2;1004 va_copy(va2, args);1005 LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: pszFile=%p:{%s} iLine=%d pszFunction=%p:{%s} pszFormat=%p:{%s} (%N)\n",1006 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pszFile, pszFile, iLine, pszFunction, pszFunction, pszFormat, pszFormat, pszFormat, &va2));1007 va_end(va2);1008 #endif1009 1010 PVM pVM = pDevIns->Internal.s.pVMR3;1011 VM_ASSERT_EMT(pVM);1012 int rc = DBGFR3EventSrcV(pVM, DBGFEVENT_DEV_STOP, pszFile, iLine, pszFunction, pszFormat, args);1013 if (rc == VERR_DBGF_NOT_ATTACHED)1014 rc = VINF_SUCCESS;1015 1016 LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));1017 return rc;1018 }1019 1020 1021 /** @interface_method_impl{PDMDEVHLPR3,pfnDBGFInfoRegister} */1022 static DECLCALLBACK(int) pdmR3DevHlp_DBGFInfoRegister(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler)1023 {1024 PDMDEV_ASSERT_DEVINS(pDevIns);1025 LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: pszName=%p:{%s} pszDesc=%p:{%s} pfnHandler=%p\n",1026 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pszName, pszName, pszDesc, pszDesc, pfnHandler));1027 1028 PVM pVM = pDevIns->Internal.s.pVMR3;1029 VM_ASSERT_EMT(pVM);1030 int rc = DBGFR3InfoRegisterDevice(pVM, pszName, pszDesc, pfnHandler, pDevIns);1031 1032 LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));1033 return rc;1034 }1035 1036 1037 /** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegister} */1038 static DECLCALLBACK(void) pdmR3DevHlp_STAMRegister(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc)1039 {1040 PDMDEV_ASSERT_DEVINS(pDevIns);1041 PVM pVM = pDevIns->Internal.s.pVMR3;1042 VM_ASSERT_EMT(pVM);1043 1044 STAM_REG(pVM, pvSample, enmType, pszName, enmUnit, pszDesc);1045 NOREF(pVM);1046 }1047 1048 1049 1050 /** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterF} */1051 static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,1052 STAMUNIT enmUnit, const char *pszDesc, const char *pszName, ...)1053 {1054 PDMDEV_ASSERT_DEVINS(pDevIns);1055 PVM pVM = pDevIns->Internal.s.pVMR3;1056 VM_ASSERT_EMT(pVM);1057 1058 va_list args;1059 va_start(args, pszName);1060 int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);1061 va_end(args);1062 AssertRC(rc);1063 1064 NOREF(pVM);1065 }1066 1067 1068 /** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterV} */1069 static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterV(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,1070 STAMUNIT enmUnit, const char *pszDesc, const char *pszName, va_list args)1071 {1072 PDMDEV_ASSERT_DEVINS(pDevIns);1073 PVM pVM = pDevIns->Internal.s.pVMR3;1074 VM_ASSERT_EMT(pVM);1075 1076 int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);1077 AssertRC(rc);1078 1079 NOREF(pVM);1080 }1081 1082 1083 /** @interface_method_impl{PDMDEVHLPR3,pfnRTCRegister} */1084 static DECLCALLBACK(int) pdmR3DevHlp_RTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)1085 {1086 PDMDEV_ASSERT_DEVINS(pDevIns);1087 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);1088 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: pRtcReg=%p:{.u32Version=%#x, .pfnWrite=%p, .pfnRead=%p} ppRtcHlp=%p\n",1089 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pRtcReg, pRtcReg->u32Version, pRtcReg->pfnWrite,1090 pRtcReg->pfnWrite, ppRtcHlp));1091 1092 /*1093 * Validate input.1094 */1095 if (pRtcReg->u32Version != PDM_RTCREG_VERSION)1096 {1097 AssertMsgFailed(("u32Version=%#x expected %#x\n", pRtcReg->u32Version,1098 PDM_RTCREG_VERSION));1099 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (version)\n",1100 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));1101 return VERR_INVALID_PARAMETER;1102 }1103 if ( !pRtcReg->pfnWrite1104 || !pRtcReg->pfnRead)1105 {1106 Assert(pRtcReg->pfnWrite);1107 Assert(pRtcReg->pfnRead);1108 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",1109 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));1110 return VERR_INVALID_PARAMETER;1111 }1112 1113 if (!ppRtcHlp)1114 {1115 Assert(ppRtcHlp);1116 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (ppRtcHlp)\n",1117 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));1118 return VERR_INVALID_PARAMETER;1119 }1120 1121 /*1122 * Only one DMA device.1123 */1124 PVM pVM = pDevIns->Internal.s.pVMR3;1125 if (pVM->pdm.s.pRtc)1126 {1127 AssertMsgFailed(("Only one RTC device is supported!\n"));1128 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",1129 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));1130 return VERR_INVALID_PARAMETER;1131 }1132 1133 /*1134 * Allocate and initialize pci bus structure.1135 */1136 int rc = VINF_SUCCESS;1137 PPDMRTC pRtc = (PPDMRTC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pRtc));1138 if (pRtc)1139 {1140 pRtc->pDevIns = pDevIns;1141 pRtc->Reg = *pRtcReg;1142 pVM->pdm.s.pRtc = pRtc;1143 1144 /* set the helper pointer. */1145 *ppRtcHlp = &g_pdmR3DevRtcHlp;1146 Log(("PDM: Registered RTC device '%s'/%d pDevIns=%p\n",1147 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDevIns));1148 }1149 else1150 rc = VERR_NO_MEMORY;1151 1152 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",1153 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));1154 return rc;1155 }1156 1157 1158 /** @interface_method_impl{PDMDEVHLPR3,pfnPDMQueueCreate} */1159 static DECLCALLBACK(int) pdmR3DevHlp_PDMQueueCreate(PPDMDEVINS pDevIns, RTUINT cbItem, RTUINT cItems, uint32_t cMilliesInterval,1160 PFNPDMQUEUEDEV pfnCallback, bool fGCEnabled, const char *pszName, PPDMQUEUE *ppQueue)1161 {1162 PDMDEV_ASSERT_DEVINS(pDevIns);1163 LogFlow(("pdmR3DevHlp_PDMQueueCreate: caller='%s'/%d: cbItem=%#x cItems=%#x cMilliesInterval=%u pfnCallback=%p fGCEnabled=%RTbool pszName=%p:{%s} ppQueue=%p\n",1164 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cbItem, cItems, cMilliesInterval, pfnCallback, fGCEnabled, pszName, pszName, ppQueue));1165 1166 PVM pVM = pDevIns->Internal.s.pVMR3;1167 VM_ASSERT_EMT(pVM);1168 1169 if (pDevIns->iInstance > 0)1170 {1171 pszName = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s_%u", pszName, pDevIns->iInstance);1172 AssertLogRelReturn(pszName, VERR_NO_MEMORY);1173 }1174 1175 int rc = PDMR3QueueCreateDevice(pVM, pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fGCEnabled, pszName, ppQueue);1176 1177 LogFlow(("pdmR3DevHlp_PDMQueueCreate: caller='%s'/%d: returns %Rrc *ppQueue=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, *ppQueue));1178 return rc;1179 }1180 1181 1182 /** @interface_method_impl{PDMDEVHLPR3,pfnCritSectInit} */1183 static DECLCALLBACK(int) pdmR3DevHlp_CritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,1184 const char *pszNameFmt, va_list va)1185 {1186 PDMDEV_ASSERT_DEVINS(pDevIns);1187 LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: pCritSect=%p pszNameFmt=%p:{%s}\n",1188 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pCritSect, pszNameFmt, pszNameFmt));1189 1190 PVM pVM = pDevIns->Internal.s.pVMR3;1191 VM_ASSERT_EMT(pVM);1192 int rc = pdmR3CritSectInitDevice(pVM, pDevIns, pCritSect, RT_SRC_POS, pszNameFmt, va);1193 1194 LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));1195 return rc;1196 }1197 1198 1199 /** @interface_method_impl{PDMDEVHLPR3,pfnUTCNow} */1200 static DECLCALLBACK(PRTTIMESPEC) pdmR3DevHlp_UTCNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)1201 {1202 PDMDEV_ASSERT_DEVINS(pDevIns);1203 LogFlow(("pdmR3DevHlp_UTCNow: caller='%s'/%d: pTime=%p\n",1204 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pTime));1205 1206 pTime = TMR3UTCNow(pDevIns->Internal.s.pVMR3, pTime);1207 1208 LogFlow(("pdmR3DevHlp_UTCNow: caller='%s'/%d: returns %RU64\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, RTTimeSpecGetNano(pTime)));1209 return pTime;1210 }1211 1212 1213 /** @interface_method_impl{PDMDEVHLPR3,pfnPDMThreadCreate} */1214 static DECLCALLBACK(int) pdmR3DevHlp_PDMThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,1215 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)1216 {1217 PDMDEV_ASSERT_DEVINS(pDevIns);1218 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);1219 LogFlow(("pdmR3DevHlp_PDMThreadCreate: caller='%s'/%d: ppThread=%p pvUser=%p pfnThread=%p pfnWakeup=%p cbStack=%#zx enmType=%d pszName=%p:{%s}\n",1220 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName, pszName));1221 1222 int rc = pdmR3ThreadCreateDevice(pDevIns->Internal.s.pVMR3, pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);1223 1224 LogFlow(("pdmR3DevHlp_PDMThreadCreate: caller='%s'/%d: returns %Rrc *ppThread=%RTthrd\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance,1225 rc, *ppThread));1226 return rc;1227 1783 } 1228 1784 … … 2072 2628 2073 2629 2074 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysRead} */ 2075 static DECLCALLBACK(int) pdmR3DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead) 2076 { 2077 PDMDEV_ASSERT_DEVINS(pDevIns); 2078 PVM pVM = pDevIns->Internal.s.pVMR3; 2079 LogFlow(("pdmR3DevHlp_PhysRead: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n", 2080 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, pvBuf, cbRead)); 2081 2082 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 2083 if (!VM_IS_EMT(pVM)) 2084 { 2085 char szNames[128]; 2086 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames)); 2087 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames)); 2088 } 2089 #endif 2090 2091 int rc; 2092 if (VM_IS_EMT(pVM)) 2093 rc = PGMPhysRead(pVM, GCPhys, pvBuf, cbRead); 2094 else 2095 rc = PGMR3PhysReadExternal(pVM, GCPhys, pvBuf, cbRead); 2096 2097 Log(("pdmR3DevHlp_PhysRead: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2098 return rc; 2099 } 2100 2101 2102 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysWrite} */ 2103 static DECLCALLBACK(int) pdmR3DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite) 2104 { 2105 PDMDEV_ASSERT_DEVINS(pDevIns); 2106 PVM pVM = pDevIns->Internal.s.pVMR3; 2107 LogFlow(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n", 2108 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, pvBuf, cbWrite)); 2109 2110 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 2111 if (!VM_IS_EMT(pVM)) 2112 { 2113 char szNames[128]; 2114 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames)); 2115 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames)); 2116 } 2117 #endif 2118 2119 int rc; 2120 if (VM_IS_EMT(pVM)) 2121 rc = PGMPhysWrite(pVM, GCPhys, pvBuf, cbWrite); 2122 else 2123 rc = PGMR3PhysWriteExternal(pVM, GCPhys, pvBuf, cbWrite, pDevIns->pDevReg->szDeviceName); 2124 2125 Log(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2126 return rc; 2127 } 2128 2129 2130 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtr} */ 2131 static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock) 2132 { 2133 PDMDEV_ASSERT_DEVINS(pDevIns); 2134 PVM pVM = pDevIns->Internal.s.pVMR3; 2135 LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n", 2136 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock)); 2137 AssertReturn(!fFlags, VERR_INVALID_PARAMETER); 2138 2139 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 2140 if (!VM_IS_EMT(pVM)) 2141 { 2142 char szNames[128]; 2143 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames)); 2144 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames)); 2145 } 2146 #endif 2147 2148 int rc = PGMR3PhysGCPhys2CCPtrExternal(pVM, GCPhys, ppv, pLock); 2149 2150 Log(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2151 return rc; 2152 } 2153 2154 2155 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtrReadOnly} */ 2156 static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, const void **ppv, PPGMPAGEMAPLOCK pLock) 2157 { 2158 PDMDEV_ASSERT_DEVINS(pDevIns); 2159 PVM pVM = pDevIns->Internal.s.pVMR3; 2160 LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n", 2161 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock)); 2162 AssertReturn(!fFlags, VERR_INVALID_PARAMETER); 2163 2164 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 2165 if (!VM_IS_EMT(pVM)) 2166 { 2167 char szNames[128]; 2168 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames)); 2169 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames)); 2170 } 2171 #endif 2172 2173 int rc = PGMR3PhysGCPhys2CCPtrReadOnlyExternal(pVM, GCPhys, ppv, pLock); 2174 2175 Log(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2176 return rc; 2177 } 2178 2179 2180 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysReleasePageMappingLock} */ 2181 static DECLCALLBACK(void) pdmR3DevHlp_PhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock) 2182 { 2183 PDMDEV_ASSERT_DEVINS(pDevIns); 2184 PVM pVM = pDevIns->Internal.s.pVMR3; 2185 LogFlow(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: pLock=%p\n", 2186 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pLock)); 2187 2188 PGMPhysReleasePageMappingLock(pVM, pLock); 2189 2190 Log(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: returns void\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 2191 } 2192 2193 2194 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysReadGCVirt} */ 2195 static DECLCALLBACK(int) pdmR3DevHlp_PhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb) 2196 { 2197 PDMDEV_ASSERT_DEVINS(pDevIns); 2198 PVM pVM = pDevIns->Internal.s.pVMR3; 2199 VM_ASSERT_EMT(pVM); 2200 LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: pvDst=%p GCVirt=%RGv cb=%#x\n", 2201 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pvDst, GCVirtSrc, cb)); 2202 2203 PVMCPU pVCpu = VMMGetCpu(pVM); 2204 if (!pVCpu) 2205 return VERR_ACCESS_DENIED; 2206 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 2207 /** @todo SMP. */ 2208 #endif 2209 2210 int rc = PGMPhysSimpleReadGCPtr(pVCpu, pvDst, GCVirtSrc, cb); 2211 2212 LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2213 2214 return rc; 2215 } 2216 2217 2218 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysWriteGCVirt} */ 2219 static DECLCALLBACK(int) pdmR3DevHlp_PhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb) 2220 { 2221 PDMDEV_ASSERT_DEVINS(pDevIns); 2222 PVM pVM = pDevIns->Internal.s.pVMR3; 2223 VM_ASSERT_EMT(pVM); 2224 LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: GCVirtDst=%RGv pvSrc=%p cb=%#x\n", 2225 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCVirtDst, pvSrc, cb)); 2226 2227 PVMCPU pVCpu = VMMGetCpu(pVM); 2228 if (!pVCpu) 2229 return VERR_ACCESS_DENIED; 2230 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 2231 /** @todo SMP. */ 2232 #endif 2233 2234 int rc = PGMPhysSimpleWriteGCPtr(pVCpu, GCVirtDst, pvSrc, cb); 2235 2236 LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2237 2238 return rc; 2239 } 2240 2241 2242 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPtr2GCPhys} */ 2243 static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys) 2244 { 2245 PDMDEV_ASSERT_DEVINS(pDevIns); 2246 PVM pVM = pDevIns->Internal.s.pVMR3; 2247 VM_ASSERT_EMT(pVM); 2248 LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: GCPtr=%RGv pGCPhys=%p\n", 2249 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPtr, pGCPhys)); 2250 2251 PVMCPU pVCpu = VMMGetCpu(pVM); 2252 if (!pVCpu) 2253 return VERR_ACCESS_DENIED; 2254 #if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION) 2255 /** @todo SMP. */ 2256 #endif 2257 2258 int rc = PGMPhysGCPtr2GCPhys(pVCpu, GCPtr, pGCPhys); 2259 2260 LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: returns %Rrc *pGCPhys=%RGp\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, *pGCPhys)); 2261 2262 return rc; 2263 } 2264 2265 2266 /** @interface_method_impl{PDMDEVHLPR3,pfnSetAsyncNotification} */ 2267 static DECLCALLBACK(int) pdmR3DevHlp_SetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify) 2268 { 2269 PDMDEV_ASSERT_DEVINS(pDevIns); 2270 VM_ASSERT_EMT0(pDevIns->Internal.s.pVMR3); 2271 LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: pfnAsyncNotify=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pfnAsyncNotify)); 2272 2273 int rc = VINF_SUCCESS; 2274 AssertStmt(pfnAsyncNotify, rc = VERR_INVALID_PARAMETER); 2275 AssertStmt(!pDevIns->Internal.s.pfnAsyncNotify, rc = VERR_WRONG_ORDER); 2276 AssertStmt(pDevIns->Internal.s.fIntFlags & (PDMDEVINSINT_FLAGS_SUSPENDED | PDMDEVINSINT_FLAGS_RESET), rc = VERR_WRONG_ORDER); 2277 VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3); 2278 AssertStmt( enmVMState == VMSTATE_SUSPENDING 2279 || enmVMState == VMSTATE_SUSPENDING_EXT_LS 2280 || enmVMState == VMSTATE_SUSPENDING_LS 2281 || enmVMState == VMSTATE_RESETTING 2282 || enmVMState == VMSTATE_RESETTING_LS 2283 || enmVMState == VMSTATE_POWERING_OFF 2284 || enmVMState == VMSTATE_POWERING_OFF_LS, 2285 rc = VERR_INVALID_STATE); 2286 2287 if (RT_SUCCESS(rc)) 2288 pDevIns->Internal.s.pfnAsyncNotify = pfnAsyncNotify; 2289 2290 LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2291 return rc; 2292 } 2293 2294 2295 /** @interface_method_impl{PDMDEVHLPR3,pfnAsyncNotificationCompleted} */ 2296 static DECLCALLBACK(void) pdmR3DevHlp_AsyncNotificationCompleted(PPDMDEVINS pDevIns) 2297 { 2298 PDMDEV_ASSERT_DEVINS(pDevIns); 2299 PVM pVM = pDevIns->Internal.s.pVMR3; 2300 2301 VMSTATE enmVMState = VMR3GetState(pVM); 2302 if ( enmVMState == VMSTATE_SUSPENDING 2303 || enmVMState == VMSTATE_SUSPENDING_EXT_LS 2304 || enmVMState == VMSTATE_SUSPENDING_LS 2305 || enmVMState == VMSTATE_RESETTING 2306 || enmVMState == VMSTATE_RESETTING_LS 2307 || enmVMState == VMSTATE_POWERING_OFF 2308 || enmVMState == VMSTATE_POWERING_OFF_LS) 2309 { 2310 LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d:\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 2311 VMR3AsyncPdmNotificationWakeupU(pVM->pUVM); 2312 } 2313 else 2314 LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d: enmVMState=%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, enmVMState)); 2315 } 2316 2317 2318 /** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */ 2319 static DECLCALLBACK(bool) pdmR3DevHlp_A20IsEnabled(PPDMDEVINS pDevIns) 2630 /** 2631 * @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap 2632 */ 2633 static DECLCALLBACK(int) pdmR3DevHlp_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbSize) 2320 2634 { 2321 2635 PDMDEV_ASSERT_DEVINS(pDevIns); 2322 2636 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 2323 2637 2324 bool fRc = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR3));2325 2326 LogFlow(("pdmR3DevHlp_A20IsEnabled: caller='%s'/%d: returns %d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, fRc)); 2327 return fRc; 2328 } 2329 2330 2331 /** @interface_method_impl{PDMDEVHLPR3,pfnA20Set}*/2332 static DECLCALLBACK( void) pdmR3DevHlp_A20Set(PPDMDEVINS pDevIns, bool fEnable)2638 int rc = PDMR3RegisterVMMDevHeap(pDevIns->Internal.s.pVMR3, GCPhys, pvHeap, cbSize); 2639 return rc; 2640 } 2641 2642 2643 /** 2644 * @copydoc PDMDEVHLPR3::pfnUnregisterVMMDevHeap 2645 */ 2646 static DECLCALLBACK(int) pdmR3DevHlp_UnregisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys) 2333 2647 { 2334 2648 PDMDEV_ASSERT_DEVINS(pDevIns); 2335 2649 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 2336 LogFlow(("pdmR3DevHlp_A20Set: caller='%s'/%d: fEnable=%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, fEnable)); 2337 PGMR3PhysSetA20(VMMGetCpu(pDevIns->Internal.s.pVMR3), fEnable); 2650 2651 int rc = PDMR3UnregisterVMMDevHeap(pDevIns->Internal.s.pVMR3, GCPhys); 2652 return rc; 2338 2653 } 2339 2654 … … 2424 2739 } 2425 2740 2426 /** @interface_method_impl{PDMDEVHLPR3,pfnDMARegister} */ 2427 static DECLCALLBACK(int) pdmR3DevHlp_DMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser) 2428 { 2429 PDMDEV_ASSERT_DEVINS(pDevIns); 2430 PVM pVM = pDevIns->Internal.s.pVMR3; 2431 VM_ASSERT_EMT(pVM); 2432 LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: uChannel=%d pfnTransferHandler=%p pvUser=%p\n", 2433 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel, pfnTransferHandler, pvUser)); 2434 int rc = VINF_SUCCESS; 2435 if (pVM->pdm.s.pDmac) 2436 pVM->pdm.s.pDmac->Reg.pfnRegister(pVM->pdm.s.pDmac->pDevIns, uChannel, pfnTransferHandler, pvUser); 2437 else 2438 { 2439 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n")); 2440 rc = VERR_PDM_NO_DMAC_INSTANCE; 2441 } 2442 LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: returns %Rrc\n", 2443 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2444 return rc; 2445 } 2446 2447 /** @interface_method_impl{PDMDEVHLPR3,pfnDMAReadMemory} */ 2448 static DECLCALLBACK(int) pdmR3DevHlp_DMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead) 2449 { 2450 PDMDEV_ASSERT_DEVINS(pDevIns); 2451 PVM pVM = pDevIns->Internal.s.pVMR3; 2452 VM_ASSERT_EMT(pVM); 2453 LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbRead=%p\n", 2454 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbRead)); 2455 int rc = VINF_SUCCESS; 2456 if (pVM->pdm.s.pDmac) 2457 { 2458 uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnReadMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock); 2459 if (pcbRead) 2460 *pcbRead = cb; 2461 } 2462 else 2463 { 2464 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n")); 2465 rc = VERR_PDM_NO_DMAC_INSTANCE; 2466 } 2467 LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: returns %Rrc\n", 2468 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2469 return rc; 2470 } 2471 2472 /** @interface_method_impl{PDMDEVHLPR3,pfnDMAWriteMemory} */ 2473 static DECLCALLBACK(int) pdmR3DevHlp_DMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten) 2474 { 2475 PDMDEV_ASSERT_DEVINS(pDevIns); 2476 PVM pVM = pDevIns->Internal.s.pVMR3; 2477 VM_ASSERT_EMT(pVM); 2478 LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbWritten=%p\n", 2479 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbWritten)); 2480 int rc = VINF_SUCCESS; 2481 if (pVM->pdm.s.pDmac) 2482 { 2483 uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnWriteMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock); 2484 if (pcbWritten) 2485 *pcbWritten = cb; 2486 } 2487 else 2488 { 2489 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n")); 2490 rc = VERR_PDM_NO_DMAC_INSTANCE; 2491 } 2492 LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: returns %Rrc\n", 2493 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2494 return rc; 2495 } 2496 2497 /** @interface_method_impl{PDMDEVHLPR3,pfnDMASetDREQ} */ 2498 static DECLCALLBACK(int) pdmR3DevHlp_DMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel) 2499 { 2500 PDMDEV_ASSERT_DEVINS(pDevIns); 2501 PVM pVM = pDevIns->Internal.s.pVMR3; 2502 VM_ASSERT_EMT(pVM); 2503 LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: uChannel=%d uLevel=%d\n", 2504 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel, uLevel)); 2505 int rc = VINF_SUCCESS; 2506 if (pVM->pdm.s.pDmac) 2507 pVM->pdm.s.pDmac->Reg.pfnSetDREQ(pVM->pdm.s.pDmac->pDevIns, uChannel, uLevel); 2508 else 2509 { 2510 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n")); 2511 rc = VERR_PDM_NO_DMAC_INSTANCE; 2512 } 2513 LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: returns %Rrc\n", 2514 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2515 return rc; 2516 } 2517 2518 /** @interface_method_impl{PDMDEVHLPR3,pfnDMAGetChannelMode} */ 2519 static DECLCALLBACK(uint8_t) pdmR3DevHlp_DMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel) 2520 { 2521 PDMDEV_ASSERT_DEVINS(pDevIns); 2522 PVM pVM = pDevIns->Internal.s.pVMR3; 2523 VM_ASSERT_EMT(pVM); 2524 LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: uChannel=%d\n", 2525 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel)); 2526 uint8_t u8Mode; 2527 if (pVM->pdm.s.pDmac) 2528 u8Mode = pVM->pdm.s.pDmac->Reg.pfnGetChannelMode(pVM->pdm.s.pDmac->pDevIns, uChannel); 2529 else 2530 { 2531 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n")); 2532 u8Mode = 3 << 2 /* illegal mode type */; 2533 } 2534 LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: returns %#04x\n", 2535 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, u8Mode)); 2536 return u8Mode; 2537 } 2538 2539 /** @interface_method_impl{PDMDEVHLPR3,pfnDMASchedule} */ 2540 static DECLCALLBACK(void) pdmR3DevHlp_DMASchedule(PPDMDEVINS pDevIns) 2541 { 2542 PDMDEV_ASSERT_DEVINS(pDevIns); 2543 PVM pVM = pDevIns->Internal.s.pVMR3; 2544 VM_ASSERT_EMT(pVM); 2545 LogFlow(("pdmR3DevHlp_DMASchedule: caller='%s'/%d: VM_FF_PDM_DMA %d -> 1\n", 2546 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VM_FF_ISSET(pVM, VM_FF_PDM_DMA))); 2547 2548 AssertMsg(pVM->pdm.s.pDmac, ("Configuration error: No DMAC controller available. This could be related to init order too!\n")); 2549 VM_FF_SET(pVM, VM_FF_PDM_DMA); 2550 REMR3NotifyDmaPending(pVM); 2551 VMR3NotifyGlobalFFU(pVM->pUVM, VMNOTIFYFF_FLAGS_DONE_REM); 2552 } 2553 2554 2555 /** @interface_method_impl{PDMDEVHLPR3,pfnCMOSWrite} */ 2556 static DECLCALLBACK(int) pdmR3DevHlp_CMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value) 2557 { 2558 PDMDEV_ASSERT_DEVINS(pDevIns); 2559 PVM pVM = pDevIns->Internal.s.pVMR3; 2560 VM_ASSERT_EMT(pVM); 2561 2562 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x u8Value=%#04x\n", 2563 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iReg, u8Value)); 2564 int rc; 2565 if (pVM->pdm.s.pRtc) 2566 rc = pVM->pdm.s.pRtc->Reg.pfnWrite(pVM->pdm.s.pRtc->pDevIns, iReg, u8Value); 2567 else 2568 rc = VERR_PDM_NO_RTC_INSTANCE; 2569 2570 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n", 2571 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2572 return rc; 2573 } 2574 2575 2576 /** @interface_method_impl{PDMDEVHLPR3,pfnCMOSRead} */ 2577 static DECLCALLBACK(int) pdmR3DevHlp_CMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value) 2578 { 2579 PDMDEV_ASSERT_DEVINS(pDevIns); 2580 PVM pVM = pDevIns->Internal.s.pVMR3; 2581 VM_ASSERT_EMT(pVM); 2582 2583 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x pu8Value=%p\n", 2584 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iReg, pu8Value)); 2585 int rc; 2586 if (pVM->pdm.s.pRtc) 2587 rc = pVM->pdm.s.pRtc->Reg.pfnRead(pVM->pdm.s.pRtc->pDevIns, iReg, pu8Value); 2588 else 2589 rc = VERR_PDM_NO_RTC_INSTANCE; 2590 2591 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n", 2592 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); 2593 return rc; 2741 2742 /** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */ 2743 static DECLCALLBACK(bool) pdmR3DevHlp_A20IsEnabled(PPDMDEVINS pDevIns) 2744 { 2745 PDMDEV_ASSERT_DEVINS(pDevIns); 2746 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 2747 2748 bool fRc = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR3)); 2749 2750 LogFlow(("pdmR3DevHlp_A20IsEnabled: caller='%s'/%d: returns %d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, fRc)); 2751 return fRc; 2752 } 2753 2754 2755 /** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */ 2756 static DECLCALLBACK(void) pdmR3DevHlp_A20Set(PPDMDEVINS pDevIns, bool fEnable) 2757 { 2758 PDMDEV_ASSERT_DEVINS(pDevIns); 2759 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 2760 LogFlow(("pdmR3DevHlp_A20Set: caller='%s'/%d: fEnable=%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, fEnable)); 2761 PGMR3PhysSetA20(VMMGetCpu(pDevIns->Internal.s.pVMR3), fEnable); 2594 2762 } 2595 2763 … … 2610 2778 LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: returns void - *pEax=%#x *pEbx=%#x *pEcx=%#x *pEdx=%#x\n", 2611 2779 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, *pEax, *pEbx, *pEcx, *pEdx)); 2612 }2613 2614 2615 /** @interface_method_impl{PDMDEVHLPR3,pfnROMProtectShadow} */2616 static DECLCALLBACK(int) pdmR3DevHlp_ROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, PGMROMPROT enmProt)2617 {2618 PDMDEV_ASSERT_DEVINS(pDevIns);2619 LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x enmProt=%d\n",2620 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange, enmProt));2621 2622 int rc = PGMR3PhysRomProtect(pDevIns->Internal.s.pVMR3, GCPhysStart, cbRange, enmProt);2623 2624 LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));2625 return rc;2626 }2627 2628 2629 /**2630 * @copydoc PDMDEVHLPR3::pfnMMIO2Register2631 */2632 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Register(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)2633 {2634 PDMDEV_ASSERT_DEVINS(pDevIns);2635 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);2636 LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: iRegion=%#x cb=%#RGp fFlags=%RX32 ppv=%p pszDescp=%p:{%s}\n",2637 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, cb, fFlags, ppv, pszDesc, pszDesc));2638 2639 /** @todo PGMR3PhysMMIO2Register mangles the description, move it here and2640 * use a real string cache. */2641 int rc = PGMR3PhysMMIO2Register(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, cb, fFlags, ppv, pszDesc);2642 2643 LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));2644 return rc;2645 }2646 2647 2648 /**2649 * @copydoc PDMDEVHLPR3::pfnMMIO2Deregister2650 */2651 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Deregister(PPDMDEVINS pDevIns, uint32_t iRegion)2652 {2653 PDMDEV_ASSERT_DEVINS(pDevIns);2654 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);2655 LogFlow(("pdmR3DevHlp_MMIO2Deregister: caller='%s'/%d: iRegion=%#x\n",2656 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion));2657 2658 AssertReturn(iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);2659 2660 int rc = PGMR3PhysMMIO2Deregister(pDevIns->Internal.s.pVMR3, pDevIns, iRegion);2661 2662 LogFlow(("pdmR3DevHlp_MMIO2Deregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));2663 return rc;2664 }2665 2666 2667 /**2668 * @copydoc PDMDEVHLPR3::pfnMMIO2Map2669 */2670 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Map(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)2671 {2672 PDMDEV_ASSERT_DEVINS(pDevIns);2673 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);2674 LogFlow(("pdmR3DevHlp_MMIO2Map: caller='%s'/%d: iRegion=%#x GCPhys=%#RGp\n",2675 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, GCPhys));2676 2677 int rc = PGMR3PhysMMIO2Map(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, GCPhys);2678 2679 LogFlow(("pdmR3DevHlp_MMIO2Map: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));2680 return rc;2681 }2682 2683 2684 /**2685 * @copydoc PDMDEVHLPR3::pfnMMIO2Unmap2686 */2687 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Unmap(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)2688 {2689 PDMDEV_ASSERT_DEVINS(pDevIns);2690 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);2691 LogFlow(("pdmR3DevHlp_MMIO2Unmap: caller='%s'/%d: iRegion=%#x GCPhys=%#RGp\n",2692 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, GCPhys));2693 2694 int rc = PGMR3PhysMMIO2Unmap(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, GCPhys);2695 2696 LogFlow(("pdmR3DevHlp_MMIO2Unmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));2697 return rc;2698 }2699 2700 2701 /**2702 * @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO22703 */2704 static DECLCALLBACK(int) pdmR3DevHlp_MMHyperMapMMIO2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,2705 const char *pszDesc, PRTRCPTR pRCPtr)2706 {2707 PDMDEV_ASSERT_DEVINS(pDevIns);2708 PVM pVM = pDevIns->Internal.s.pVMR3;2709 VM_ASSERT_EMT(pVM);2710 LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: iRegion=%#x off=%RGp cb=%RGp pszDesc=%p:{%s} pRCPtr=%p\n",2711 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, off, cb, pszDesc, pszDesc, pRCPtr));2712 2713 if (pDevIns->iInstance > 0)2714 {2715 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);2716 if (pszDesc2)2717 pszDesc = pszDesc2;2718 }2719 2720 int rc = MMR3HyperMapMMIO2(pVM, pDevIns, iRegion, off, cb, pszDesc, pRCPtr);2721 2722 LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: returns %Rrc *pRCPtr=%RRv\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, *pRCPtr));2723 return rc;2724 }2725 2726 2727 /**2728 * @copydoc PDMDEVHLPR3::pfnMMIO2MapKernel2729 */2730 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2MapKernel(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,2731 const char *pszDesc, PRTR0PTR pR0Ptr)2732 {2733 PDMDEV_ASSERT_DEVINS(pDevIns);2734 PVM pVM = pDevIns->Internal.s.pVMR3;2735 VM_ASSERT_EMT(pVM);2736 LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: iRegion=%#x off=%RGp cb=%RGp pszDesc=%p:{%s} pR0Ptr=%p\n",2737 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, off, cb, pszDesc, pszDesc, pR0Ptr));2738 2739 if (pDevIns->iInstance > 0)2740 {2741 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);2742 if (pszDesc2)2743 pszDesc = pszDesc2;2744 }2745 2746 int rc = PGMR3PhysMMIO2MapKernel(pVM, pDevIns, iRegion, off, cb, pszDesc, pR0Ptr);2747 2748 LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: returns %Rrc *pR0Ptr=%RHv\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, *pR0Ptr));2749 return rc;2750 }2751 2752 2753 /**2754 * @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap2755 */2756 static DECLCALLBACK(int) pdmR3DevHlp_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbSize)2757 {2758 PDMDEV_ASSERT_DEVINS(pDevIns);2759 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);2760 2761 int rc = PDMR3RegisterVMMDevHeap(pDevIns->Internal.s.pVMR3, GCPhys, pvHeap, cbSize);2762 return rc;2763 }2764 2765 2766 /**2767 * @copydoc PDMDEVHLPR3::pfnUnregisterVMMDevHeap2768 */2769 static DECLCALLBACK(int) pdmR3DevHlp_UnregisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)2770 {2771 PDMDEV_ASSERT_DEVINS(pDevIns);2772 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);2773 2774 int rc = PDMR3UnregisterVMMDevHeap(pDevIns->Internal.s.pVMR3, GCPhys);2775 return rc;2776 2780 } 2777 2781 … … 2782 2786 const PDMDEVHLPR3 g_pdmR3DevHlpTrusted = 2783 2787 { 2784 PDM_DEVHLP _VERSION,2788 PDM_DEVHLPR3_VERSION, 2785 2789 pdmR3DevHlp_IOPortRegister, 2786 pdmR3DevHlp_IOPortRegister GC,2790 pdmR3DevHlp_IOPortRegisterRC, 2787 2791 pdmR3DevHlp_IOPortRegisterR0, 2788 2792 pdmR3DevHlp_IOPortDeregister, 2789 2793 pdmR3DevHlp_MMIORegister, 2790 pdmR3DevHlp_MMIORegister GC,2794 pdmR3DevHlp_MMIORegisterRC, 2791 2795 pdmR3DevHlp_MMIORegisterR0, 2792 2796 pdmR3DevHlp_MMIODeregister, 2797 pdmR3DevHlp_MMIO2Register, 2798 pdmR3DevHlp_MMIO2Deregister, 2799 pdmR3DevHlp_MMIO2Map, 2800 pdmR3DevHlp_MMIO2Unmap, 2801 pdmR3DevHlp_MMHyperMapMMIO2, 2802 pdmR3DevHlp_MMIO2MapKernel, 2793 2803 pdmR3DevHlp_ROMRegister, 2804 pdmR3DevHlp_ROMProtectShadow, 2794 2805 pdmR3DevHlp_SSMRegister, 2795 2806 pdmR3DevHlp_TMTimerCreate, 2807 pdmR3DevHlp_UTCNow, 2808 pdmR3DevHlp_PhysRead, 2809 pdmR3DevHlp_PhysWrite, 2810 pdmR3DevHlp_PhysGCPhys2CCPtr, 2811 pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly, 2812 pdmR3DevHlp_PhysReleasePageMappingLock, 2813 pdmR3DevHlp_PhysReadGCVirt, 2814 pdmR3DevHlp_PhysWriteGCVirt, 2815 pdmR3DevHlp_PhysGCPtr2GCPhys, 2816 pdmR3DevHlp_MMHeapAlloc, 2817 pdmR3DevHlp_MMHeapAllocZ, 2818 pdmR3DevHlp_MMHeapFree, 2819 pdmR3DevHlp_VMState, 2820 pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet, 2821 pdmR3DevHlp_VMSetError, 2822 pdmR3DevHlp_VMSetErrorV, 2823 pdmR3DevHlp_VMSetRuntimeError, 2824 pdmR3DevHlp_VMSetRuntimeErrorV, 2825 pdmR3DevHlp_DBGFStopV, 2826 pdmR3DevHlp_DBGFInfoRegister, 2827 pdmR3DevHlp_STAMRegister, 2828 pdmR3DevHlp_STAMRegisterF, 2829 pdmR3DevHlp_STAMRegisterV, 2796 2830 pdmR3DevHlp_PCIRegister, 2797 2831 pdmR3DevHlp_PCIIORegionRegister, … … 2802 2836 pdmR3DevHlp_ISASetIrqNoWait, 2803 2837 pdmR3DevHlp_DriverAttach, 2804 pdmR3DevHlp_MMHeapAlloc, 2805 pdmR3DevHlp_MMHeapAllocZ, 2806 pdmR3DevHlp_MMHeapFree, 2807 pdmR3DevHlp_VMSetError, 2808 pdmR3DevHlp_VMSetErrorV, 2809 pdmR3DevHlp_VMSetRuntimeError, 2810 pdmR3DevHlp_VMSetRuntimeErrorV, 2811 pdmR3DevHlp_VMState, 2812 pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet, 2838 pdmR3DevHlp_QueueCreate, 2839 pdmR3DevHlp_CritSectInit, 2840 pdmR3DevHlp_ThreadCreate, 2841 pdmR3DevHlp_SetAsyncNotification, 2842 pdmR3DevHlp_AsyncNotificationCompleted, 2843 pdmR3DevHlp_RTCRegister, 2844 pdmR3DevHlp_PCIBusRegister, 2845 pdmR3DevHlp_PICRegister, 2846 pdmR3DevHlp_APICRegister, 2847 pdmR3DevHlp_IOAPICRegister, 2848 pdmR3DevHlp_HPETRegister, 2849 pdmR3DevHlp_DMACRegister, 2850 pdmR3DevHlp_DMARegister, 2851 pdmR3DevHlp_DMAReadMemory, 2852 pdmR3DevHlp_DMAWriteMemory, 2853 pdmR3DevHlp_DMASetDREQ, 2854 pdmR3DevHlp_DMAGetChannelMode, 2855 pdmR3DevHlp_DMASchedule, 2856 pdmR3DevHlp_CMOSWrite, 2857 pdmR3DevHlp_CMOSRead, 2813 2858 pdmR3DevHlp_AssertEMT, 2814 2859 pdmR3DevHlp_AssertOther, 2815 pdmR3DevHlp_DBGFStopV,2816 pdmR3DevHlp_DBGFInfoRegister,2817 pdmR3DevHlp_STAMRegister,2818 pdmR3DevHlp_STAMRegisterF,2819 pdmR3DevHlp_STAMRegisterV,2820 pdmR3DevHlp_RTCRegister,2821 pdmR3DevHlp_PDMQueueCreate,2822 pdmR3DevHlp_CritSectInit,2823 pdmR3DevHlp_UTCNow,2824 pdmR3DevHlp_PDMThreadCreate,2825 pdmR3DevHlp_PhysGCPtr2GCPhys,2826 pdmR3DevHlp_SetAsyncNotification,2827 pdmR3DevHlp_AsyncNotificationCompleted,2828 2860 0, 2829 2861 0, … … 2837 2869 0, 2838 2870 pdmR3DevHlp_GetVM, 2839 pdmR3DevHlp_PCIBusRegister, 2840 pdmR3DevHlp_PICRegister, 2841 pdmR3DevHlp_APICRegister, 2842 pdmR3DevHlp_IOAPICRegister, 2843 pdmR3DevHlp_HPETRegister, 2844 pdmR3DevHlp_DMACRegister, 2871 pdmR3DevHlp_GetVMCPU, 2872 pdmR3DevHlp_RegisterVMMDevHeap, 2873 pdmR3DevHlp_UnregisterVMMDevHeap, 2874 pdmR3DevHlp_VMReset, 2875 pdmR3DevHlp_VMSuspend, 2876 pdmR3DevHlp_VMPowerOff, 2877 pdmR3DevHlp_A20IsEnabled, 2878 pdmR3DevHlp_A20Set, 2879 pdmR3DevHlp_GetCpuId, 2880 PDM_DEVHLPR3_VERSION /* the end */ 2881 }; 2882 2883 2884 2885 2886 /** @interface_method_impl{PDMDEVHLPR3,pfnGetVM} */ 2887 static DECLCALLBACK(PVM) pdmR3DevHlp_Untrusted_GetVM(PPDMDEVINS pDevIns) 2888 { 2889 PDMDEV_ASSERT_DEVINS(pDevIns); 2890 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 2891 return NULL; 2892 } 2893 2894 2895 /** @interface_method_impl{PDMDEVHLPR3,pfnGetVMCPU} */ 2896 static DECLCALLBACK(PVMCPU) pdmR3DevHlp_Untrusted_GetVMCPU(PPDMDEVINS pDevIns) 2897 { 2898 PDMDEV_ASSERT_DEVINS(pDevIns); 2899 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 2900 return NULL; 2901 } 2902 2903 2904 /** @interface_method_impl{PDMDEVHLPR3,pfnRegisterVMMDevHeap} */ 2905 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbSize) 2906 { 2907 PDMDEV_ASSERT_DEVINS(pDevIns); 2908 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 2909 return VERR_ACCESS_DENIED; 2910 } 2911 2912 2913 /** @interface_method_impl{PDMDEVHLPR3,pfnUnregisterVMMDevHeap} */ 2914 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_UnregisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys) 2915 { 2916 PDMDEV_ASSERT_DEVINS(pDevIns); 2917 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 2918 return VERR_ACCESS_DENIED; 2919 } 2920 2921 2922 /** @interface_method_impl{PDMDEVHLPR3,pfnVMReset} */ 2923 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMReset(PPDMDEVINS pDevIns) 2924 { 2925 PDMDEV_ASSERT_DEVINS(pDevIns); 2926 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 2927 return VERR_ACCESS_DENIED; 2928 } 2929 2930 2931 /** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspend} */ 2932 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspend(PPDMDEVINS pDevIns) 2933 { 2934 PDMDEV_ASSERT_DEVINS(pDevIns); 2935 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 2936 return VERR_ACCESS_DENIED; 2937 } 2938 2939 2940 /** @interface_method_impl{PDMDEVHLPR3,pfnVMPowerOff} */ 2941 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMPowerOff(PPDMDEVINS pDevIns) 2942 { 2943 PDMDEV_ASSERT_DEVINS(pDevIns); 2944 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 2945 return VERR_ACCESS_DENIED; 2946 } 2947 2948 2949 /** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */ 2950 static DECLCALLBACK(bool) pdmR3DevHlp_Untrusted_A20IsEnabled(PPDMDEVINS pDevIns) 2951 { 2952 PDMDEV_ASSERT_DEVINS(pDevIns); 2953 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 2954 return false; 2955 } 2956 2957 2958 /** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */ 2959 static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_A20Set(PPDMDEVINS pDevIns, bool fEnable) 2960 { 2961 PDMDEV_ASSERT_DEVINS(pDevIns); 2962 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 2963 NOREF(fEnable); 2964 } 2965 2966 2967 /** @interface_method_impl{PDMDEVHLPR3,pfnGetCpuId} */ 2968 static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, 2969 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx) 2970 { 2971 PDMDEV_ASSERT_DEVINS(pDevIns); 2972 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 2973 } 2974 2975 2976 /** 2977 * The device helper structure for non-trusted devices. 2978 */ 2979 const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted = 2980 { 2981 PDM_DEVHLPR3_VERSION, 2982 pdmR3DevHlp_IOPortRegister, 2983 pdmR3DevHlp_IOPortRegisterRC, 2984 pdmR3DevHlp_IOPortRegisterR0, 2985 pdmR3DevHlp_IOPortDeregister, 2986 pdmR3DevHlp_MMIORegister, 2987 pdmR3DevHlp_MMIORegisterRC, 2988 pdmR3DevHlp_MMIORegisterR0, 2989 pdmR3DevHlp_MMIODeregister, 2990 pdmR3DevHlp_MMIO2Register, 2991 pdmR3DevHlp_MMIO2Deregister, 2992 pdmR3DevHlp_MMIO2Map, 2993 pdmR3DevHlp_MMIO2Unmap, 2994 pdmR3DevHlp_MMHyperMapMMIO2, 2995 pdmR3DevHlp_MMIO2MapKernel, 2996 pdmR3DevHlp_ROMRegister, 2997 pdmR3DevHlp_ROMProtectShadow, 2998 pdmR3DevHlp_SSMRegister, 2999 pdmR3DevHlp_TMTimerCreate, 3000 pdmR3DevHlp_UTCNow, 2845 3001 pdmR3DevHlp_PhysRead, 2846 3002 pdmR3DevHlp_PhysWrite, … … 2850 3006 pdmR3DevHlp_PhysReadGCVirt, 2851 3007 pdmR3DevHlp_PhysWriteGCVirt, 2852 pdmR3DevHlp_A20IsEnabled, 2853 pdmR3DevHlp_A20Set, 2854 pdmR3DevHlp_VMReset, 2855 pdmR3DevHlp_VMSuspend, 2856 pdmR3DevHlp_VMPowerOff, 3008 pdmR3DevHlp_PhysGCPtr2GCPhys, 3009 pdmR3DevHlp_MMHeapAlloc, 3010 pdmR3DevHlp_MMHeapAllocZ, 3011 pdmR3DevHlp_MMHeapFree, 3012 pdmR3DevHlp_VMState, 3013 pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet, 3014 pdmR3DevHlp_VMSetError, 3015 pdmR3DevHlp_VMSetErrorV, 3016 pdmR3DevHlp_VMSetRuntimeError, 3017 pdmR3DevHlp_VMSetRuntimeErrorV, 3018 pdmR3DevHlp_DBGFStopV, 3019 pdmR3DevHlp_DBGFInfoRegister, 3020 pdmR3DevHlp_STAMRegister, 3021 pdmR3DevHlp_STAMRegisterF, 3022 pdmR3DevHlp_STAMRegisterV, 3023 pdmR3DevHlp_PCIRegister, 3024 pdmR3DevHlp_PCIIORegionRegister, 3025 pdmR3DevHlp_PCISetConfigCallbacks, 3026 pdmR3DevHlp_PCISetIrq, 3027 pdmR3DevHlp_PCISetIrqNoWait, 3028 pdmR3DevHlp_ISASetIrq, 3029 pdmR3DevHlp_ISASetIrqNoWait, 3030 pdmR3DevHlp_DriverAttach, 3031 pdmR3DevHlp_QueueCreate, 3032 pdmR3DevHlp_CritSectInit, 3033 pdmR3DevHlp_ThreadCreate, 3034 pdmR3DevHlp_SetAsyncNotification, 3035 pdmR3DevHlp_AsyncNotificationCompleted, 3036 pdmR3DevHlp_RTCRegister, 3037 pdmR3DevHlp_PCIBusRegister, 3038 pdmR3DevHlp_PICRegister, 3039 pdmR3DevHlp_APICRegister, 3040 pdmR3DevHlp_IOAPICRegister, 3041 pdmR3DevHlp_HPETRegister, 3042 pdmR3DevHlp_DMACRegister, 2857 3043 pdmR3DevHlp_DMARegister, 2858 3044 pdmR3DevHlp_DMAReadMemory, … … 2863 3049 pdmR3DevHlp_CMOSWrite, 2864 3050 pdmR3DevHlp_CMOSRead, 2865 pdmR3DevHlp_GetCpuId,2866 pdmR3DevHlp_ROMProtectShadow,2867 pdmR3DevHlp_MMIO2Register,2868 pdmR3DevHlp_MMIO2Deregister,2869 pdmR3DevHlp_MMIO2Map,2870 pdmR3DevHlp_MMIO2Unmap,2871 pdmR3DevHlp_MMHyperMapMMIO2,2872 pdmR3DevHlp_MMIO2MapKernel,2873 pdmR3DevHlp_RegisterVMMDevHeap,2874 pdmR3DevHlp_UnregisterVMMDevHeap,2875 pdmR3DevHlp_GetVMCPU,2876 PDM_DEVHLP_VERSION /* the end */2877 };2878 2879 2880 2881 2882 /** @interface_method_impl{PDMDEVHLPR3,pfnGetVM} */2883 static DECLCALLBACK(PVM) pdmR3DevHlp_Untrusted_GetVM(PPDMDEVINS pDevIns)2884 {2885 PDMDEV_ASSERT_DEVINS(pDevIns);2886 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));2887 return NULL;2888 }2889 2890 2891 /** @interface_method_impl{PDMDEVHLPR3,pfnPCIBusRegister} */2892 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg, PCPDMPCIHLPR3 *ppPciHlpR3)2893 {2894 PDMDEV_ASSERT_DEVINS(pDevIns);2895 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));2896 NOREF(pPciBusReg);2897 NOREF(ppPciHlpR3);2898 return VERR_ACCESS_DENIED;2899 }2900 2901 2902 /** @interface_method_impl{PDMDEVHLPR3,pfnPICRegister} */2903 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3)2904 {2905 PDMDEV_ASSERT_DEVINS(pDevIns);2906 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));2907 NOREF(pPicReg);2908 NOREF(ppPicHlpR3);2909 return VERR_ACCESS_DENIED;2910 }2911 2912 2913 /** @interface_method_impl{PDMDEVHLPR3,pfnAPICRegister} */2914 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_APICRegister(PPDMDEVINS pDevIns, PPDMAPICREG pApicReg, PCPDMAPICHLPR3 *ppApicHlpR3)2915 {2916 PDMDEV_ASSERT_DEVINS(pDevIns);2917 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));2918 NOREF(pApicReg);2919 NOREF(ppApicHlpR3);2920 return VERR_ACCESS_DENIED;2921 }2922 2923 2924 /** @interface_method_impl{PDMDEVHLPR3,pfnIOAPICRegister} */2925 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_IOAPICRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3)2926 {2927 PDMDEV_ASSERT_DEVINS(pDevIns);2928 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));2929 NOREF(pIoApicReg);2930 NOREF(ppIoApicHlpR3);2931 return VERR_ACCESS_DENIED;2932 }2933 2934 2935 /** @interface_method_impl{PDMDEVHLPR3,pfnHPETRegister} */2936 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_HPETRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)2937 {2938 PDMDEV_ASSERT_DEVINS(pDevIns);2939 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));2940 NOREF(pHpetReg);2941 NOREF(ppHpetHlpR3);2942 return VERR_ACCESS_DENIED;2943 }2944 2945 2946 /** @interface_method_impl{PDMDEVHLPR3,pfnDMACRegister} */2947 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)2948 {2949 PDMDEV_ASSERT_DEVINS(pDevIns);2950 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));2951 NOREF(pDmacReg);2952 NOREF(ppDmacHlp);2953 return VERR_ACCESS_DENIED;2954 }2955 2956 2957 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysRead} */2958 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)2959 {2960 PDMDEV_ASSERT_DEVINS(pDevIns);2961 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));2962 NOREF(GCPhys);2963 NOREF(pvBuf);2964 NOREF(cbRead);2965 return VERR_ACCESS_DENIED;2966 }2967 2968 2969 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysWrite} */2970 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)2971 {2972 PDMDEV_ASSERT_DEVINS(pDevIns);2973 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));2974 NOREF(GCPhys);2975 NOREF(pvBuf);2976 NOREF(cbWrite);2977 return VERR_ACCESS_DENIED;2978 }2979 2980 2981 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtr} */2982 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)2983 {2984 PDMDEV_ASSERT_DEVINS(pDevIns);2985 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));2986 NOREF(GCPhys);2987 NOREF(fFlags);2988 NOREF(ppv);2989 NOREF(pLock);2990 return VERR_ACCESS_DENIED;2991 }2992 2993 2994 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtrReadOnly} */2995 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, const void **ppv, PPGMPAGEMAPLOCK pLock)2996 {2997 PDMDEV_ASSERT_DEVINS(pDevIns);2998 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));2999 NOREF(GCPhys);3000 NOREF(fFlags);3001 NOREF(ppv);3002 NOREF(pLock);3003 return VERR_ACCESS_DENIED;3004 }3005 3006 3007 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysReleasePageMappingLock} */3008 static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_PhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)3009 {3010 PDMDEV_ASSERT_DEVINS(pDevIns);3011 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3012 NOREF(pLock);3013 }3014 3015 3016 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysReadGCVirt} */3017 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)3018 {3019 PDMDEV_ASSERT_DEVINS(pDevIns);3020 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3021 NOREF(pvDst);3022 NOREF(GCVirtSrc);3023 NOREF(cb);3024 return VERR_ACCESS_DENIED;3025 }3026 3027 3028 /** @interface_method_impl{PDMDEVHLPR3,pfnPhysWriteGCVirt} */3029 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)3030 {3031 PDMDEV_ASSERT_DEVINS(pDevIns);3032 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3033 NOREF(GCVirtDst);3034 NOREF(pvSrc);3035 NOREF(cb);3036 return VERR_ACCESS_DENIED;3037 }3038 3039 3040 /** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */3041 static DECLCALLBACK(bool) pdmR3DevHlp_Untrusted_A20IsEnabled(PPDMDEVINS pDevIns)3042 {3043 PDMDEV_ASSERT_DEVINS(pDevIns);3044 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3045 return false;3046 }3047 3048 3049 /** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */3050 static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_A20Set(PPDMDEVINS pDevIns, bool fEnable)3051 {3052 PDMDEV_ASSERT_DEVINS(pDevIns);3053 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3054 NOREF(fEnable);3055 }3056 3057 3058 /** @interface_method_impl{PDMDEVHLPR3,pfnVMReset} */3059 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMReset(PPDMDEVINS pDevIns)3060 {3061 PDMDEV_ASSERT_DEVINS(pDevIns);3062 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3063 return VERR_ACCESS_DENIED;3064 }3065 3066 3067 /** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspend} */3068 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspend(PPDMDEVINS pDevIns)3069 {3070 PDMDEV_ASSERT_DEVINS(pDevIns);3071 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3072 return VERR_ACCESS_DENIED;3073 }3074 3075 3076 /** @interface_method_impl{PDMDEVHLPR3,pfnVMPowerOff} */3077 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMPowerOff(PPDMDEVINS pDevIns)3078 {3079 PDMDEV_ASSERT_DEVINS(pDevIns);3080 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3081 return VERR_ACCESS_DENIED;3082 }3083 3084 /** @interface_method_impl{PDMDEVHLPR3,pfnDMARegister} */3085 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)3086 {3087 PDMDEV_ASSERT_DEVINS(pDevIns);3088 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3089 return VERR_ACCESS_DENIED;3090 }3091 3092 3093 /** @interface_method_impl{PDMDEVHLPR3,pfnDMAReadMemory} */3094 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead)3095 {3096 PDMDEV_ASSERT_DEVINS(pDevIns);3097 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3098 if (pcbRead)3099 *pcbRead = 0;3100 return VERR_ACCESS_DENIED;3101 }3102 3103 3104 /** @interface_method_impl{PDMDEVHLPR3,pfnDMAWriteMemory} */3105 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten)3106 {3107 PDMDEV_ASSERT_DEVINS(pDevIns);3108 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3109 if (pcbWritten)3110 *pcbWritten = 0;3111 return VERR_ACCESS_DENIED;3112 }3113 3114 3115 /** @interface_method_impl{PDMDEVHLPR3,pfnDMASetDREQ} */3116 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)3117 {3118 PDMDEV_ASSERT_DEVINS(pDevIns);3119 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3120 return VERR_ACCESS_DENIED;3121 }3122 3123 3124 /** @interface_method_impl{PDMDEVHLPR3,pfnDMAGetChannelMode} */3125 static DECLCALLBACK(uint8_t) pdmR3DevHlp_Untrusted_DMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)3126 {3127 PDMDEV_ASSERT_DEVINS(pDevIns);3128 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3129 return 3 << 2 /* illegal mode type */;3130 }3131 3132 3133 /** @interface_method_impl{PDMDEVHLPR3,pfnDMASchedule} */3134 static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_DMASchedule(PPDMDEVINS pDevIns)3135 {3136 PDMDEV_ASSERT_DEVINS(pDevIns);3137 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3138 }3139 3140 3141 /** @interface_method_impl{PDMDEVHLPR3,pfnCMOSWrite} */3142 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_CMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)3143 {3144 PDMDEV_ASSERT_DEVINS(pDevIns);3145 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3146 return VERR_ACCESS_DENIED;3147 }3148 3149 3150 /** @interface_method_impl{PDMDEVHLPR3,pfnCMOSRead} */3151 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_CMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)3152 {3153 PDMDEV_ASSERT_DEVINS(pDevIns);3154 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3155 return VERR_ACCESS_DENIED;3156 }3157 3158 3159 /** @interface_method_impl{PDMDEVHLPR3,pfnGetCpuId} */3160 static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,3161 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)3162 {3163 PDMDEV_ASSERT_DEVINS(pDevIns);3164 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3165 }3166 3167 3168 /** @interface_method_impl{PDMDEVHLPR3,pfnROMProtectShadow} */3169 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_ROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, PGMROMPROT enmProt)3170 {3171 PDMDEV_ASSERT_DEVINS(pDevIns);3172 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3173 return VERR_ACCESS_DENIED;3174 }3175 3176 3177 /** @interface_method_impl{PDMDEVHLPR3,pfnMMIO2Register} */3178 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2Register(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)3179 {3180 PDMDEV_ASSERT_DEVINS(pDevIns);3181 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3182 return VERR_ACCESS_DENIED;3183 }3184 3185 3186 /** @interface_method_impl{PDMDEVHLPR3,pfnMMIO2Deregister} */3187 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2Deregister(PPDMDEVINS pDevIns, uint32_t iRegion)3188 {3189 PDMDEV_ASSERT_DEVINS(pDevIns);3190 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3191 return VERR_ACCESS_DENIED;3192 }3193 3194 3195 /** @interface_method_impl{PDMDEVHLPR3,pfnMMIO2Map} */3196 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2Map(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)3197 {3198 PDMDEV_ASSERT_DEVINS(pDevIns);3199 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3200 return VERR_ACCESS_DENIED;3201 }3202 3203 3204 /** @interface_method_impl{PDMDEVHLPR3,pfnMMIO2Unmap} */3205 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2Unmap(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)3206 {3207 PDMDEV_ASSERT_DEVINS(pDevIns);3208 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3209 return VERR_ACCESS_DENIED;3210 }3211 3212 3213 /** @interface_method_impl{PDMDEVHLPR3,pfnMMHyperMapMMIO2} */3214 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMHyperMapMMIO2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTRCPTR pRCPtr)3215 {3216 PDMDEV_ASSERT_DEVINS(pDevIns);3217 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3218 return VERR_ACCESS_DENIED;3219 }3220 3221 3222 /** @interface_method_impl{PDMDEVHLPR3,pfnMMIO2MapKernel} */3223 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2MapKernel(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr)3224 {3225 PDMDEV_ASSERT_DEVINS(pDevIns);3226 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3227 return VERR_ACCESS_DENIED;3228 }3229 3230 3231 /** @interface_method_impl{PDMDEVHLPR3,pfnRegisterVMMDevHeap} */3232 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbSize)3233 {3234 PDMDEV_ASSERT_DEVINS(pDevIns);3235 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3236 return VERR_ACCESS_DENIED;3237 }3238 3239 3240 /** @interface_method_impl{PDMDEVHLPR3,pfnUnregisterVMMDevHeap} */3241 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_UnregisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)3242 {3243 PDMDEV_ASSERT_DEVINS(pDevIns);3244 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3245 return VERR_ACCESS_DENIED;3246 }3247 3248 3249 /** @interface_method_impl{PDMDEVHLPR3,pfnGetVMCPU} */3250 static DECLCALLBACK(PVMCPU) pdmR3DevHlp_Untrusted_GetVMCPU(PPDMDEVINS pDevIns)3251 {3252 PDMDEV_ASSERT_DEVINS(pDevIns);3253 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));3254 return NULL;3255 }3256 3257 3258 /**3259 * The device helper structure for non-trusted devices.3260 */3261 const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted =3262 {3263 PDM_DEVHLP_VERSION,3264 pdmR3DevHlp_IOPortRegister,3265 pdmR3DevHlp_IOPortRegisterGC,3266 pdmR3DevHlp_IOPortRegisterR0,3267 pdmR3DevHlp_IOPortDeregister,3268 pdmR3DevHlp_MMIORegister,3269 pdmR3DevHlp_MMIORegisterGC,3270 pdmR3DevHlp_MMIORegisterR0,3271 pdmR3DevHlp_MMIODeregister,3272 pdmR3DevHlp_ROMRegister,3273 pdmR3DevHlp_SSMRegister,3274 pdmR3DevHlp_TMTimerCreate,3275 pdmR3DevHlp_PCIRegister,3276 pdmR3DevHlp_PCIIORegionRegister,3277 pdmR3DevHlp_PCISetConfigCallbacks,3278 pdmR3DevHlp_PCISetIrq,3279 pdmR3DevHlp_PCISetIrqNoWait,3280 pdmR3DevHlp_ISASetIrq,3281 pdmR3DevHlp_ISASetIrqNoWait,3282 pdmR3DevHlp_DriverAttach,3283 pdmR3DevHlp_MMHeapAlloc,3284 pdmR3DevHlp_MMHeapAllocZ,3285 pdmR3DevHlp_MMHeapFree,3286 pdmR3DevHlp_VMSetError,3287 pdmR3DevHlp_VMSetErrorV,3288 pdmR3DevHlp_VMSetRuntimeError,3289 pdmR3DevHlp_VMSetRuntimeErrorV,3290 pdmR3DevHlp_VMState,3291 pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet,3292 3051 pdmR3DevHlp_AssertEMT, 3293 3052 pdmR3DevHlp_AssertOther, 3294 pdmR3DevHlp_DBGFStopV,3295 pdmR3DevHlp_DBGFInfoRegister,3296 pdmR3DevHlp_STAMRegister,3297 pdmR3DevHlp_STAMRegisterF,3298 pdmR3DevHlp_STAMRegisterV,3299 pdmR3DevHlp_RTCRegister,3300 pdmR3DevHlp_PDMQueueCreate,3301 pdmR3DevHlp_CritSectInit,3302 pdmR3DevHlp_UTCNow,3303 pdmR3DevHlp_PDMThreadCreate,3304 pdmR3DevHlp_PhysGCPtr2GCPhys,3305 pdmR3DevHlp_SetAsyncNotification,3306 pdmR3DevHlp_AsyncNotificationCompleted,3307 3053 0, 3308 3054 0, … … 3316 3062 0, 3317 3063 pdmR3DevHlp_Untrusted_GetVM, 3318 pdmR3DevHlp_Untrusted_PCIBusRegister, 3319 pdmR3DevHlp_Untrusted_PICRegister, 3320 pdmR3DevHlp_Untrusted_APICRegister, 3321 pdmR3DevHlp_Untrusted_IOAPICRegister, 3322 pdmR3DevHlp_Untrusted_HPETRegister, 3323 pdmR3DevHlp_Untrusted_DMACRegister, 3324 pdmR3DevHlp_Untrusted_PhysRead, 3325 pdmR3DevHlp_Untrusted_PhysWrite, 3326 pdmR3DevHlp_Untrusted_PhysGCPhys2CCPtr, 3327 pdmR3DevHlp_Untrusted_PhysGCPhys2CCPtrReadOnly, 3328 pdmR3DevHlp_Untrusted_PhysReleasePageMappingLock, 3329 pdmR3DevHlp_Untrusted_PhysReadGCVirt, 3330 pdmR3DevHlp_Untrusted_PhysWriteGCVirt, 3331 pdmR3DevHlp_Untrusted_A20IsEnabled, 3332 pdmR3DevHlp_Untrusted_A20Set, 3064 pdmR3DevHlp_Untrusted_GetVMCPU, 3065 pdmR3DevHlp_Untrusted_RegisterVMMDevHeap, 3066 pdmR3DevHlp_Untrusted_UnregisterVMMDevHeap, 3333 3067 pdmR3DevHlp_Untrusted_VMReset, 3334 3068 pdmR3DevHlp_Untrusted_VMSuspend, 3335 3069 pdmR3DevHlp_Untrusted_VMPowerOff, 3336 pdmR3DevHlp_Untrusted_DMARegister, 3337 pdmR3DevHlp_Untrusted_DMAReadMemory, 3338 pdmR3DevHlp_Untrusted_DMAWriteMemory, 3339 pdmR3DevHlp_Untrusted_DMASetDREQ, 3340 pdmR3DevHlp_Untrusted_DMAGetChannelMode, 3341 pdmR3DevHlp_Untrusted_DMASchedule, 3342 pdmR3DevHlp_Untrusted_CMOSWrite, 3343 pdmR3DevHlp_Untrusted_CMOSRead, 3070 pdmR3DevHlp_Untrusted_A20IsEnabled, 3071 pdmR3DevHlp_Untrusted_A20Set, 3344 3072 pdmR3DevHlp_Untrusted_GetCpuId, 3345 pdmR3DevHlp_Untrusted_ROMProtectShadow, 3346 pdmR3DevHlp_Untrusted_MMIO2Register, 3347 pdmR3DevHlp_Untrusted_MMIO2Deregister, 3348 pdmR3DevHlp_Untrusted_MMIO2Map, 3349 pdmR3DevHlp_Untrusted_MMIO2Unmap, 3350 pdmR3DevHlp_Untrusted_MMHyperMapMMIO2, 3351 pdmR3DevHlp_Untrusted_MMIO2MapKernel, 3352 pdmR3DevHlp_Untrusted_RegisterVMMDevHeap, 3353 pdmR3DevHlp_Untrusted_UnregisterVMMDevHeap, 3354 pdmR3DevHlp_Untrusted_GetVMCPU, 3355 PDM_DEVHLP_VERSION /* the end */ 3073 PDM_DEVHLPR3_VERSION /* the end */ 3356 3074 }; 3357 3075
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