Changeset 31636 in vbox for trunk/src/VBox
- Timestamp:
- Aug 13, 2010 12:03:15 PM (14 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/EMRaw.cpp
r30263 r31636 690 690 691 691 uint32_t opsize; 692 rc = EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);692 rc = VBOXSTRICTRC_TODO(EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &opsize)); 693 693 if (RT_SUCCESS(rc)) 694 694 { … … 1184 1184 #endif 1185 1185 1186 rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);1186 rc = VBOXSTRICTRC_TODO(EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &size)); 1187 1187 if (RT_SUCCESS(rc)) 1188 1188 { -
trunk/src/VBox/VMM/PATM/VMMGC/PATMGC.cpp
r31402 r31636 522 522 } 523 523 524 rc = EMInterpretInstructionCPU(pVM, VMMGetCpu0(pVM), &cpu, pRegFrame, 0 /* not relevant here */, &size); 524 rc = EMInterpretInstructionCPU(pVM, VMMGetCpu0(pVM), &cpu, pRegFrame, 0 /* not relevant here */, 525 EMCODETYPE_SUPERVISOR, &size); 525 526 if (rc != VINF_SUCCESS) 526 527 { -
trunk/src/VBox/VMM/VMMAll/EMAll.cpp
r31569 r31636 75 75 * Internal Functions * 76 76 *******************************************************************************/ 77 DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize, EMCODETYPE enmCodeType = EMCODETYPE_SUPERVISOR); 77 DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, 78 RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize); 78 79 79 80 … … 311 312 * to worry about e.g. invalid modrm combinations (!) 312 313 */ 313 VMMDECL( int) EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)314 VMMDECL(VBOXSTRICTRC) EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 314 315 { 315 316 RTGCPTR pbCode; 316 317 317 318 LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault)); 318 intrc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);319 VBOXSTRICTRC rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode); 319 320 if (RT_SUCCESS(rc)) 320 321 { … … 326 327 { 327 328 Assert(cbOp == pDis->opsize); 328 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize);329 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbSize); 329 330 if (RT_SUCCESS(rc)) 330 331 pRegFrame->rip += cbOp; /* Move on to the next instruction. */ … … 342 343 * EIP is *NOT* updated! 343 344 * 344 * @returns VBox st atus code.345 * @returns VBox strict status code. 345 346 * @retval VINF_* Scheduling instructions. When these are returned, it 346 347 * starts to get a bit tricky to know whether code was … … 365 366 * Make sure this can't happen!! (will add some assertions/checks later) 366 367 */ 367 VMMDECL(int) EMInterpretInstructionCPUEx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize, EMCODETYPE enmCodeType) 368 VMMDECL(VBOXSTRICTRC) EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, 369 RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize) 368 370 { 369 371 STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a); 370 int rc = emInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, enmCodeType);372 VBOXSTRICTRC rc = emInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize); 371 373 STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a); 372 374 if (RT_SUCCESS(rc)) … … 1765 1767 * 1766 1768 */ 1767 VMMDECL(int) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC) 1768 { 1769 int rc; 1770 1769 VMMDECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC) 1770 { 1771 1771 /** @todo is addr always a flat linear address or ds based 1772 1772 * (in absence of segment override prefixes)???? … … 1775 1775 LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC)); 1776 1776 #endif 1777 rc = PGMInvalidatePage(pVCpu, pAddrGC);1777 VBOXSTRICTRC rc = PGMInvalidatePage(pVCpu, pAddrGC); 1778 1778 if ( rc == VINF_SUCCESS 1779 1779 || rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */) 1780 1780 return VINF_SUCCESS; 1781 1781 AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR, 1782 ("%Rrc addr=%RGv\n", rc, pAddrGC),1782 ("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), pAddrGC), 1783 1783 VERR_EM_INTERPRETER); 1784 1784 return rc; … … 1789 1789 * INVLPG Emulation. 1790 1790 */ 1791 static intemInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1791 static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1792 1792 { 1793 1793 OP_PARAMVAL param1; 1794 1794 RTGCPTR addr; 1795 1795 1796 intrc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE);1796 VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE); 1797 1797 if(RT_FAILURE(rc)) 1798 1798 return VERR_EM_INTERPRETER; … … 1822 1822 return VINF_SUCCESS; 1823 1823 AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR, 1824 ("%Rrc addr=%RGv\n", rc, addr),1824 ("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), addr), 1825 1825 VERR_EM_INTERPRETER); 1826 1826 return rc; … … 2426 2426 * HLT Emulation. 2427 2427 */ 2428 static int emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2428 static VBOXSTRICTRC 2429 emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2429 2430 { 2430 2431 return VINF_EM_HALT; … … 2573 2574 * MWAIT Emulation. 2574 2575 */ 2575 VMMDECL( int) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)2576 VMMDECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame) 2576 2577 { 2577 2578 uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures; … … 2617 2618 } 2618 2619 2619 static intemInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2620 static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2620 2621 { 2621 2622 return EMInterpretMWait(pVM, pVCpu, pRegFrame); … … 2802 2803 * @copydoc EMInterpretInstructionCPU 2803 2804 */ 2804 DECLINLINE( int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,2805 uint32_t *pcbSize, EMCODETYPE enmCodeType)2805 DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, 2806 RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize) 2806 2807 { 2807 2808 Assert(enmCodeType == EMCODETYPE_SUPERVISOR || enmCodeType == EMCODETYPE_ALL); … … 2942 2943 #endif 2943 2944 2944 intrc;2945 VBOXSTRICTRC rc; 2945 2946 #if (defined(VBOX_STRICT) || defined(LOG_ENABLED)) 2946 2947 LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis))); -
trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
r31565 r31636 694 694 * Emulation of the invlpg instruction (HC only actually). 695 695 * 696 * @returns VBox status code, special care required.696 * @returns Strict VBox status code, special care required. 697 697 * @retval VINF_PGM_SYNC_CR3 - handled. 698 698 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only). … … 706 706 * 707 707 * @todo Flush page or page directory only if necessary! 708 * @todo VBOXSTRICTRC 708 709 */ 709 710 VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage) … … 797 798 * @param pvFault Fault address. 798 799 */ 799 VMMDECL( int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)800 VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault) 800 801 { 801 802 uint32_t cb; 802 intrc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);803 VBOXSTRICTRC rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb); 803 804 if (rc == VERR_EM_INTERPRETER) 804 805 rc = VINF_EM_RAW_EMULATE_INSTR; 805 806 if (rc != VINF_SUCCESS) 806 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));807 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault)); 807 808 return rc; 808 809 } -
trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
r31612 r31636 385 385 * It's writing to an unhandled part of the LDT page several million times. 386 386 */ 387 rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);387 rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault)); 388 388 LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage)); 389 389 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; }); … … 799 799 our shadow page tables. (Required for e.g. Solaris guests; soft 800 800 ecc, random nr generator.) */ 801 rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);801 rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault)); 802 802 LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage)); 803 803 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon)); … … 946 946 { 947 947 Assert((uErr & (X86_TRAP_PF_RW | X86_TRAP_PF_P)) == (X86_TRAP_PF_RW | X86_TRAP_PF_P)); 948 rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);948 rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault)); 949 949 if (RT_SUCCESS(rc)) 950 950 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ); -
trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
r31593 r31636 120 120 * @param pPool The pool. 121 121 * @param pPage A page in the chain. 122 * @todo VBOXSTRICTRC 122 123 */ 123 124 int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage) … … 852 853 * @param GCPhysFault The fault address as guest physical address. 853 854 * @param pvFault The fault address. 855 * @todo VBOXSTRICTRC 854 856 */ 855 857 static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis, … … 862 864 863 865 /* 864 * Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection). Must do this in raw mode (!); XP boot will fail otherwise 866 * Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection). 867 * Must do this in raw mode (!); XP boot will fail otherwise. 865 868 */ 866 869 uint32_t cbWritten; 867 int rc2 = EMInterpretInstructionCPUEx(pVM, pVCpu, pDis, pRegFrame, pvFault, &cbWritten, EMCODETYPE_ALL);870 VBOXSTRICTRC rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL, &cbWritten); 868 871 if (RT_SUCCESS(rc2)) 872 { 869 873 pRegFrame->rip += pDis->opsize; 874 AssertMsg(rc2 == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rc2))); /* ASSUMES no complicated stuff here. */ 875 } 870 876 else if (rc2 == VERR_EM_INTERPRETER) 871 877 { … … 886 892 } 887 893 else 888 rc = rc2;894 rc = VBOXSTRICTRC_VAL(rc2); 889 895 890 896 LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc)); … … 1002 1008 */ 1003 1009 uint32_t cb; 1004 int rc = EMInterpretInstructionCPUEx(pVM, pVCpu, pDis, pRegFrame, pvFault, &cb, EMCODETYPE_ALL);1010 VBOXSTRICTRC rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL, &cb); 1005 1011 if (RT_SUCCESS(rc)) 1012 { 1006 1013 pRegFrame->rip += pDis->opsize; 1014 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rc))); /* ASSUMES no complicated stuff here. */ 1015 } 1007 1016 else if (rc == VERR_EM_INTERPRETER) 1008 1017 { … … 1043 1052 #endif 1044 1053 1045 LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));1046 return rc;1054 LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", VBOXSTRICTRC_VAL(rc), cb)); 1055 return VBOXSTRICTRC_VAL(rc); 1047 1056 } 1048 1057 -
trunk/src/VBox/VMM/VMMGC/TRPMGCHandlers.cpp
r31402 r31636 549 549 LogFlow(("TRPMGCTrap06Handler: -> EMInterpretInstructionCPU\n")); 550 550 uint32_t cbIgnored; 551 rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, pRegFrame, PC, &cbIgnored);551 rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR, &cbIgnored); 552 552 if (RT_SUCCESS(rc)) 553 553 pRegFrame->eip += Cpu.opsize; … … 794 794 { 795 795 uint32_t cbIgnored; 796 rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, &cbIgnored);796 rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR, &cbIgnored); 797 797 if (RT_SUCCESS(rc)) 798 798 pRegFrame->eip += pCpu->opsize; … … 873 873 { 874 874 uint32_t cbIgnored; 875 rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, &cbIgnored);875 rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR, &cbIgnored); 876 876 if (RT_SUCCESS(rc)) 877 877 pRegFrame->eip += pCpu->opsize; -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r31569 r31636 3290 3290 3291 3291 default: 3292 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, &cbSize);3292 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &cbSize); 3293 3293 break; 3294 3294 }
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