Changeset 41675 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Jun 12, 2012 8:27:37 PM (13 years ago)
- svn:sync-xref-src-repo-rev:
- 78482
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 20 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/EMAll.cpp
r41674 r41675 789 789 case OP_LMSW: return "Lmsw"; 790 790 case OP_SMSW: return "Smsw"; 791 case OP_CMPXCHG: return pDis->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";792 case OP_CMPXCHG8B: return pDis->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";791 case OP_CMPXCHG: return pDis->prefix & DISPREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg"; 792 case OP_CMPXCHG8B: return pDis->prefix & DISPREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b"; 793 793 794 794 default: … … 1009 1009 static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1010 1010 { 1011 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */1011 Assert(pDis->mode != DISCPUMODE_64BIT); /** @todo check */ 1012 1012 OP_PARAMVAL param1; 1013 1013 NOREF(pvFault); … … 1028 1028 1029 1029 /* Read stack value first */ 1030 if (SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)1030 if (SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == DISCPUMODE_16BIT) 1031 1031 return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */ 1032 1032 … … 1561 1561 } 1562 1562 #ifdef LOG_ENABLED 1563 if (pDis->mode == CPUMODE_64BIT)1563 if (pDis->mode == DISCPUMODE_64BIT) 1564 1564 LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64)); 1565 1565 else … … 1624 1624 } 1625 1625 #ifdef LOG_ENABLED 1626 if (pDis->mode == CPUMODE_64BIT)1626 if (pDis->mode == DISCPUMODE_64BIT) 1627 1627 LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size)); 1628 1628 else … … 1652 1652 1653 1653 /* Don't support any but these three prefix bytes. */ 1654 if ((pDis->prefix & ~( PREFIX_ADDRSIZE|PREFIX_OPSIZE|PREFIX_REP|PREFIX_REX)))1654 if ((pDis->prefix & ~(DISPREFIX_ADDRSIZE|DISPREFIX_OPSIZE|DISPREFIX_REP|DISPREFIX_REX))) 1655 1655 return VERR_EM_INTERPRETER; 1656 1656 1657 1657 switch (pDis->addrmode) 1658 1658 { 1659 case CPUMODE_16BIT:1659 case DISCPUMODE_16BIT: 1660 1660 GCOffset = pRegFrame->di; 1661 1661 cTransfers = pRegFrame->cx; 1662 1662 break; 1663 case CPUMODE_32BIT:1663 case DISCPUMODE_32BIT: 1664 1664 GCOffset = pRegFrame->edi; 1665 1665 cTransfers = pRegFrame->ecx; 1666 1666 break; 1667 case CPUMODE_64BIT:1667 case DISCPUMODE_64BIT: 1668 1668 GCOffset = pRegFrame->rdi; 1669 1669 cTransfers = pRegFrame->rcx; … … 1677 1677 switch (pDis->opmode) 1678 1678 { 1679 case CPUMODE_16BIT:1679 case DISCPUMODE_16BIT: 1680 1680 cbSize = 2; 1681 1681 break; 1682 case CPUMODE_32BIT:1682 case DISCPUMODE_32BIT: 1683 1683 cbSize = 4; 1684 1684 break; 1685 case CPUMODE_64BIT:1685 case DISCPUMODE_64BIT: 1686 1686 cbSize = 8; 1687 1687 break; … … 1693 1693 offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize; 1694 1694 1695 if (!(pDis->prefix & PREFIX_REP))1695 if (!(pDis->prefix & DISPREFIX_REP)) 1696 1696 { 1697 1697 LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize)); … … 1705 1705 switch (pDis->addrmode) 1706 1706 { 1707 case CPUMODE_16BIT:1707 case DISCPUMODE_16BIT: 1708 1708 pRegFrame->di += offIncrement; 1709 1709 break; 1710 case CPUMODE_32BIT:1710 case DISCPUMODE_32BIT: 1711 1711 pRegFrame->edi += offIncrement; 1712 1712 break; 1713 case CPUMODE_64BIT:1713 case DISCPUMODE_64BIT: 1714 1714 pRegFrame->rdi += offIncrement; 1715 1715 break; … … 1770 1770 switch (pDis->addrmode) 1771 1771 { 1772 case CPUMODE_16BIT:1772 case DISCPUMODE_16BIT: 1773 1773 pRegFrame->di = GCOffset; 1774 1774 pRegFrame->cx = cTransfers; 1775 1775 break; 1776 case CPUMODE_32BIT:1776 case DISCPUMODE_32BIT: 1777 1777 pRegFrame->edi = GCOffset; 1778 1778 pRegFrame->ecx = cTransfers; 1779 1779 break; 1780 case CPUMODE_64BIT:1780 case DISCPUMODE_64BIT: 1781 1781 pRegFrame->rdi = GCOffset; 1782 1782 pRegFrame->rcx = cTransfers; … … 1848 1848 LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar)); 1849 1849 1850 if (pDis->prefix & PREFIX_LOCK)1850 if (pDis->prefix & DISPREFIX_LOCK) 1851 1851 eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->param2.cb); 1852 1852 else … … 1870 1870 static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1871 1871 { 1872 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */1872 Assert(pDis->mode != DISCPUMODE_64BIT); /** @todo check */ 1873 1873 OP_PARAMVAL param1; 1874 1874 NOREF(pvFault); … … 1901 1901 LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax)); 1902 1902 1903 if (pDis->prefix & PREFIX_LOCK)1903 if (pDis->prefix & DISPREFIX_LOCK) 1904 1904 eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx); 1905 1905 else … … 1924 1924 static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1925 1925 { 1926 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */1926 Assert(pDis->mode != DISCPUMODE_64BIT); /** @todo check */ 1927 1927 OP_PARAMVAL param1; 1928 1928 void *pvParamReg2; … … 1970 1970 LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, *(uint64_t *)pvParamReg2)); 1971 1971 1972 if (pDis->prefix & PREFIX_LOCK)1972 if (pDis->prefix & DISPREFIX_LOCK) 1973 1973 eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2); 1974 1974 else … … 2654 2654 AssertRCReturn(rc, VERR_EM_INTERPRETER); 2655 2655 2656 if (!(pDis->prefix & PREFIX_OPSIZE))2656 if (!(pDis->prefix & DISPREFIX_OPSIZE)) 2657 2657 dtr32.uAddr &= 0xffffff; /* 16 bits operand size */ 2658 2658 … … 3030 3030 /* Note: The Intel manual claims there's a REX version of RDMSR that's slightly 3031 3031 different, so we play safe by completely disassembling the instruction. */ 3032 Assert(!(pDis->prefix & PREFIX_REX));3032 Assert(!(pDis->prefix & DISPREFIX_REX)); 3033 3033 NOREF(pDis); NOREF(pvFault); NOREF(pcbSize); 3034 3034 return EMInterpretRdmsr(pVM, pVCpu, pRegFrame); … … 3104 3104 3105 3105 #ifdef IN_RC 3106 if ( (pDis->prefix & ( PREFIX_REPNE |PREFIX_REP))3107 || ( (pDis->prefix & PREFIX_LOCK)3106 if ( (pDis->prefix & (DISPREFIX_REPNE | DISPREFIX_REP)) 3107 || ( (pDis->prefix & DISPREFIX_LOCK) 3108 3108 && pDis->pCurInstr->opcode != OP_CMPXCHG 3109 3109 && pDis->pCurInstr->opcode != OP_CMPXCHG8B … … 3116 3116 ) 3117 3117 #else 3118 if ( (pDis->prefix & PREFIX_REPNE)3119 || ( (pDis->prefix & PREFIX_REP)3118 if ( (pDis->prefix & DISPREFIX_REPNE) 3119 || ( (pDis->prefix & DISPREFIX_REP) 3120 3120 && pDis->pCurInstr->opcode != OP_STOSWD 3121 3121 ) 3122 || ( (pDis->prefix & PREFIX_LOCK)3122 || ( (pDis->prefix & DISPREFIX_LOCK) 3123 3123 && pDis->pCurInstr->opcode != OP_OR 3124 3124 && pDis->pCurInstr->opcode != OP_AND … … 3228 3228 # define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \ 3229 3229 case opcode:\ 3230 if (pDis->prefix & PREFIX_LOCK) \3230 if (pDis->prefix & DISPREFIX_LOCK) \ 3231 3231 rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \ 3232 3232 else \ -
trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp
r41072 r41675 670 670 * We do not support segment prefixes or REPNE. 671 671 */ 672 if (pCpu->prefix & ( PREFIX_SEG |PREFIX_REPNE))672 if (pCpu->prefix & (DISPREFIX_SEG | DISPREFIX_REPNE)) 673 673 return VINF_IOM_R3_MMIO_READ_WRITE; /** @todo -> interpret whatever. */ 674 674 … … 679 679 */ 680 680 uint32_t cTransfers = 1; 681 if (pCpu->prefix & PREFIX_REP)681 if (pCpu->prefix & DISPREFIX_REP) 682 682 { 683 683 #ifndef IN_RC … … 688 688 689 689 cTransfers = pRegFrame->ecx; 690 if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid) == CPUMODE_16BIT)690 if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid) == DISCPUMODE_16BIT) 691 691 cTransfers &= 0xffff; 692 692 … … 767 767 #endif 768 768 /* Update ecx. */ 769 if (pCpu->prefix & PREFIX_REP)769 if (pCpu->prefix & DISPREFIX_REP) 770 770 pRegFrame->ecx = cTransfers; 771 771 } … … 875 875 876 876 /* Update ecx on exit. */ 877 if (pCpu->prefix & PREFIX_REP)877 if (pCpu->prefix & DISPREFIX_REP) 878 878 pRegFrame->ecx = cTransfers; 879 879 } … … 898 898 switch (enmCpuMode) 899 899 { 900 case CPUMODE_16BIT: return UINT16_MAX;901 case CPUMODE_32BIT: return UINT32_MAX;902 case CPUMODE_64BIT: return UINT64_MAX;900 case DISCPUMODE_16BIT: return UINT16_MAX; 901 case DISCPUMODE_32BIT: return UINT32_MAX; 902 case DISCPUMODE_64BIT: return UINT64_MAX; 903 903 default: 904 904 AssertFailedReturn(UINT32_MAX); … … 928 928 * We do not support segment prefixes or REPNE.. 929 929 */ 930 if (pCpu->prefix & ( PREFIX_SEG |PREFIX_REPNE))930 if (pCpu->prefix & (DISPREFIX_SEG | DISPREFIX_REPNE)) 931 931 return VINF_IOM_R3_MMIO_READ_WRITE; /** @todo -> REM instead of HC */ 932 932 … … 936 936 uint64_t const fAddrMask = iomDisModeToMask(pCpu->addrmode); 937 937 RTGCUINTREG cTransfers = 1; 938 if (pCpu->prefix & PREFIX_REP)938 if (pCpu->prefix & DISPREFIX_REP) 939 939 { 940 940 #ifndef IN_RC … … 983 983 pRegFrame->rdi = ((pRegFrame->rdi + (cTransfers << SIZE_2_SHIFT(cb))) & fAddrMask) 984 984 | (pRegFrame->rdi & ~fAddrMask); 985 if (pCpu->prefix & PREFIX_REP)985 if (pCpu->prefix & DISPREFIX_REP) 986 986 pRegFrame->rcx &= ~fAddrMask; 987 987 } … … 998 998 pRegFrame->rdi = ((pRegFrame->rdi - (cTransfers << SIZE_2_SHIFT(cb))) & fAddrMask) 999 999 | (pRegFrame->rdi & ~fAddrMask); 1000 if (pCpu->prefix & PREFIX_REP)1000 if (pCpu->prefix & DISPREFIX_REP) 1001 1001 pRegFrame->rcx &= ~fAddrMask; 1002 1002 } … … 1025 1025 1026 1026 /* Update rcx on exit. */ 1027 if (pCpu->prefix & PREFIX_REP)1027 if (pCpu->prefix & DISPREFIX_REP) 1028 1028 pRegFrame->rcx = (cTransfers & fAddrMask) 1029 1029 | (pRegFrame->rcx & ~fAddrMask); … … 1062 1062 * We do not support segment prefixes or REP*. 1063 1063 */ 1064 if (pCpu->prefix & ( PREFIX_SEG | PREFIX_REP |PREFIX_REPNE))1064 if (pCpu->prefix & (DISPREFIX_SEG | DISPREFIX_REP | DISPREFIX_REPNE)) 1065 1065 return VINF_IOM_R3_MMIO_READ_WRITE; /** @todo -> REM instead of HC */ 1066 1066 … … 2030 2030 * pointer. Segment prefixes are deliberately ignored, as per the instruction specification. 2031 2031 */ 2032 if ( (uPrefix & PREFIX_REPNE)2032 if ( (uPrefix & DISPREFIX_REPNE) 2033 2033 || pRegFrame->eflags.Bits.u1DF) 2034 2034 return VINF_EM_RAW_EMULATE_INSTR; … … 2041 2041 uint64_t const fAddrMask = iomDisModeToMask(enmAddrMode); 2042 2042 RTGCUINTREG cTransfers = 1; 2043 if (uPrefix & PREFIX_REP)2043 if (uPrefix & DISPREFIX_REP) 2044 2044 { 2045 2045 #ifndef IN_RC … … 2108 2108 2109 2109 /* Update rcx on exit. */ 2110 if (uPrefix & PREFIX_REP)2110 if (uPrefix & DISPREFIX_REP) 2111 2111 pRegFrame->rcx = (cTransfers & fAddrMask) 2112 2112 | (pRegFrame->rcx & ~fAddrMask); … … 2147 2147 cb = 1; 2148 2148 else 2149 cb = (pCpu->opmode == CPUMODE_16BIT) ? 2 : 4; /* dword in both 32 & 64 bits mode */2149 cb = (pCpu->opmode == DISCPUMODE_16BIT) ? 2 : 4; /* dword in both 32 & 64 bits mode */ 2150 2150 2151 2151 VBOXSTRICTRC rcStrict = IOMInterpretCheckPortIOAccess(pVM, pRegFrame, Port, cb); … … 2192 2192 * decrementing source pointer. 2193 2193 */ 2194 if ( (uPrefix & ( PREFIX_SEG |PREFIX_REPNE))2194 if ( (uPrefix & (DISPREFIX_SEG | DISPREFIX_REPNE)) 2195 2195 || pRegFrame->eflags.Bits.u1DF) 2196 2196 return VINF_EM_RAW_EMULATE_INSTR; … … 2203 2203 uint64_t const fAddrMask = iomDisModeToMask(enmAddrMode); 2204 2204 RTGCUINTREG cTransfers = 1; 2205 if (uPrefix & PREFIX_REP)2205 if (uPrefix & DISPREFIX_REP) 2206 2206 { 2207 2207 #ifndef IN_RC … … 2275 2275 2276 2276 /* Update rcx on exit. */ 2277 if (uPrefix & PREFIX_REP)2277 if (uPrefix & DISPREFIX_REP) 2278 2278 pRegFrame->rcx = (cTransfers & fAddrMask) 2279 2279 | (pRegFrame->rcx & ~fAddrMask); … … 2316 2316 cb = 1; 2317 2317 else 2318 cb = (pCpu->opmode == CPUMODE_16BIT) ? 2 : 4; /* dword in both 32 & 64 bits mode */2318 cb = (pCpu->opmode == DISCPUMODE_16BIT) ? 2 : 4; /* dword in both 32 & 64 bits mode */ 2319 2319 2320 2320 VBOXSTRICTRC rcStrict = IOMInterpretCheckPortIOAccess(pVM, pRegFrame, Port, cb); -
trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
r41458 r41675 918 918 if ( rc == VINF_SUCCESS 919 919 && pDis->pCurInstr->opcode == OP_MOVSWD 920 && (pDis->prefix & PREFIX_REP))920 && (pDis->prefix & DISPREFIX_REP)) 921 921 { 922 922 CSAMMarkPossibleCodePage(pVM, pvFault); -
trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp
r41446 r41675 107 107 rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, &cbOp); 108 108 if ( RT_SUCCESS(rc) 109 && pDis->mode == CPUMODE_32BIT /** @todo why does this matter? */110 && !(pDis->prefix & ( PREFIX_REPNE | PREFIX_REP |PREFIX_SEG)))109 && pDis->mode == DISCPUMODE_32BIT /** @todo why does this matter? */ 110 && !(pDis->prefix & (DISPREFIX_REPNE | DISPREFIX_REP | DISPREFIX_SEG))) 111 111 { 112 112 switch (pDis->opcode) -
trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
r41663 r41675 793 793 case OP_MOVSWD: 794 794 case OP_STOSWD: 795 if ( pDis->prefix == ( PREFIX_REP|PREFIX_REX)795 if ( pDis->prefix == (DISPREFIX_REP|DISPREFIX_REX) 796 796 && pRegFrame->rcx >= 0x40 797 797 ) 798 798 { 799 Assert(pDis->mode == CPUMODE_64BIT);799 Assert(pDis->mode == DISCPUMODE_64BIT); 800 800 801 801 Log(("pgmPoolMonitorIsReused: OP_STOSQ\n")); … … 890 890 NOREF(pVM); 891 891 892 Assert(pDis->mode == CPUMODE_32BIT || pDis->mode ==CPUMODE_64BIT);892 Assert(pDis->mode == DISCPUMODE_32BIT || pDis->mode == DISCPUMODE_64BIT); 893 893 Assert(pRegFrame->rcx <= 0x20); 894 894 895 895 #ifdef VBOX_STRICT 896 if (pDis->opmode == CPUMODE_32BIT)896 if (pDis->opmode == DISCPUMODE_32BIT) 897 897 Assert(uIncrement == 4); 898 898 else … … 1155 1155 * Simple instructions, no REP prefix. 1156 1156 */ 1157 if (!(pDis->prefix & ( PREFIX_REP |PREFIX_REPNE)))1157 if (!(pDis->prefix & (DISPREFIX_REP | DISPREFIX_REPNE))) 1158 1158 { 1159 1159 rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused); … … 1203 1203 bool fValidStosd = false; 1204 1204 1205 if ( pDis->mode == CPUMODE_32BIT1206 && pDis->prefix == PREFIX_REP1205 if ( pDis->mode == DISCPUMODE_32BIT 1206 && pDis->prefix == DISPREFIX_REP 1207 1207 && pRegFrame->ecx <= 0x20 1208 1208 && pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK) … … 1215 1215 } 1216 1216 else 1217 if ( pDis->mode == CPUMODE_64BIT1218 && pDis->prefix == ( PREFIX_REP |PREFIX_REX)1217 if ( pDis->mode == DISCPUMODE_64BIT 1218 && pDis->prefix == (DISPREFIX_REP | DISPREFIX_REX) 1219 1219 && pRegFrame->rcx <= 0x20 1220 1220 && pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK) -
trunk/src/VBox/VMM/VMMAll/SELMAll.cpp
r40449 r41675 911 911 Desc = paLDT[Sel >> X86_SEL_SHIFT]; 912 912 } 913 return (Desc.Gen.u1DefBig) ? CPUMODE_32BIT :CPUMODE_16BIT;913 return (Desc.Gen.u1DefBig) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; 914 914 } 915 915 #endif /* !IN_RING0 */ … … 938 938 if ( eflags.Bits.u1VM 939 939 || CPUMIsGuestInRealMode(pVCpu)) 940 return CPUMODE_16BIT;940 return DISCPUMODE_16BIT; 941 941 942 942 return selmGetCpuModeFromSelector(pVCpu->CTX_SUFF(pVM), pVCpu, Sel); … … 945 945 if ( pHiddenSel->Attr.n.u1Long 946 946 && CPUMIsGuestInLongMode(pVCpu)) 947 return CPUMODE_64BIT;947 return DISCPUMODE_64BIT; 948 948 949 949 /* Else compatibility or 32 bits mode. */ 950 return pHiddenSel->Attr.n.u1DefBig ? CPUMODE_32BIT :CPUMODE_16BIT;950 return pHiddenSel->Attr.n.u1DefBig ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; 951 951 } 952 952 -
trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
r41645 r41675 2972 2972 */ 2973 2973 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid); 2974 if (enmMode != CPUMODE_16BIT)2974 if (enmMode != DISCPUMODE_16BIT) 2975 2975 { 2976 2976 RTGCPTR pbCode; -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r41645 r41675 3585 3585 X86EFLAGS eflags; 3586 3586 3587 if (pDis->prefix & PREFIX_OPSIZE)3587 if (pDis->prefix & DISPREFIX_OPSIZE) 3588 3588 { 3589 3589 cbParm = 4; … … 3627 3627 X86EFLAGS eflags; 3628 3628 3629 if (pDis->prefix & PREFIX_OPSIZE)3629 if (pDis->prefix & DISPREFIX_OPSIZE) 3630 3630 { 3631 3631 cbParm = 4; … … 3669 3669 uint16_t aIretFrame[3]; 3670 3670 3671 if (pDis->prefix & ( PREFIX_OPSIZE |PREFIX_ADDRSIZE))3671 if (pDis->prefix & (DISPREFIX_OPSIZE | DISPREFIX_ADDRSIZE)) 3672 3672 { 3673 3673 rc = VERR_EM_INTERPRETER; -
trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r41674 r41675 3631 3631 State.cbSegLimit = pCtx->csHid.u32Limit; 3632 3632 enmDisCpuMode = (State.f64Bits) 3633 ? CPUMODE_64BIT3633 ? DISCPUMODE_64BIT 3634 3634 : pCtx->csHid.Attr.n.u1DefBig 3635 ? CPUMODE_32BIT3636 : CPUMODE_16BIT;3635 ? DISCPUMODE_32BIT 3636 : DISCPUMODE_16BIT; 3637 3637 } 3638 3638 else … … 3659 3659 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase; 3660 3660 State.cbSegLimit = SelInfo.cbLimit; 3661 enmDisCpuMode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT :CPUMODE_16BIT;3661 enmDisCpuMode = SelInfo.u.Raw.Gen.u1DefBig ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; 3662 3662 } 3663 3663 } … … 3665 3665 { 3666 3666 /* real or V86 mode */ 3667 enmDisCpuMode = CPUMODE_16BIT;3667 enmDisCpuMode = DISCPUMODE_16BIT; 3668 3668 State.GCPtrSegBase = pCtx->cs * 16; 3669 3669 State.GCPtrSegEnd = 0xFFFFFFFF; -
trunk/src/VBox/VMM/VMMR3/CSAM.cpp
r41674 r41675 870 870 Assert(VALID_PTR(pCurInstrHC)); 871 871 872 rc = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? CPUMODE_32BIT :CPUMODE_16BIT,872 rc = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, 873 873 &cpu, &opsize, NULL, 0); 874 874 } … … 1053 1053 STAM_PROFILE_START(&pVM->csam.s.StatTimeDisasm, a); 1054 1054 #ifdef DEBUG 1055 rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? CPUMODE_32BIT :CPUMODE_16BIT,1055 rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, 1056 1056 &cpu, &opsize, szOutput, sizeof(szOutput)); 1057 1057 if (RT_SUCCESS(rc2)) Log(("CSAM Call Analysis: %s", szOutput)); 1058 1058 #else 1059 rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? CPUMODE_32BIT :CPUMODE_16BIT,1059 rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, 1060 1060 &cpu, &opsize, NULL, 0); 1061 1061 #endif … … 1266 1266 STAM_PROFILE_START(&pVM->csam.s.StatTimeDisasm, a); 1267 1267 #ifdef DEBUG 1268 rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, fCode32 ? CPUMODE_32BIT :CPUMODE_16BIT,1268 rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, fCode32 ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, 1269 1269 &cpu, &opsize, szOutput, sizeof(szOutput)); 1270 1270 if (RT_SUCCESS(rc2)) Log(("CSAM Analysis: %s", szOutput)); 1271 1271 #else 1272 rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, fCode32 ? CPUMODE_32BIT :CPUMODE_16BIT,1272 rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, fCode32 ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, 1273 1273 &cpu, &opsize, NULL, 0); 1274 1274 #endif … … 2261 2261 { 2262 2262 /* Assuming 32 bits code for now. */ 2263 Assert(SELMGetCpuModeFromSelector(VMMGetCpu0(pVM), pCtxCore->eflags, pCtxCore->cs, &pCtxCore->csHid) == CPUMODE_32BIT);2263 Assert(SELMGetCpuModeFromSelector(VMMGetCpu0(pVM), pCtxCore->eflags, pCtxCore->cs, &pCtxCore->csHid) == DISCPUMODE_32BIT); 2264 2264 2265 2265 pInstrGC = SELMToFlat(pVM, DIS_SELREG_CS, pCtxCore, pInstrGC); -
trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp
r41674 r41675 122 122 case DBGF_DISAS_FLAGS_DEFAULT_MODE: 123 123 enmCpuMode = pState->f64Bits 124 ? CPUMODE_64BIT124 ? DISCPUMODE_64BIT 125 125 : pSelInfo->u.Raw.Gen.u1DefBig 126 ? CPUMODE_32BIT127 : CPUMODE_16BIT;126 ? DISCPUMODE_32BIT 127 : DISCPUMODE_16BIT; 128 128 break; 129 129 case DBGF_DISAS_FLAGS_16BIT_MODE: 130 130 case DBGF_DISAS_FLAGS_16BIT_REAL_MODE: 131 enmCpuMode = CPUMODE_16BIT;131 enmCpuMode = DISCPUMODE_16BIT; 132 132 break; 133 133 case DBGF_DISAS_FLAGS_32BIT_MODE: 134 enmCpuMode = CPUMODE_32BIT;134 enmCpuMode = DISCPUMODE_32BIT; 135 135 break; 136 136 case DBGF_DISAS_FLAGS_64BIT_MODE: 137 enmCpuMode = CPUMODE_64BIT;137 enmCpuMode = DISCPUMODE_64BIT; 138 138 break; 139 139 } -
trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp
r40446 r41675 307 307 rcStrict = VINF_EM_RAW_EMULATE_INSTR; 308 308 309 if (!(Cpu.prefix & ( PREFIX_REP |PREFIX_REPNE)))309 if (!(Cpu.prefix & (DISPREFIX_REP | DISPREFIX_REPNE))) 310 310 { 311 311 switch (Cpu.pCurInstr->opcode) … … 326 326 } 327 327 } 328 else if (Cpu.prefix & PREFIX_REP)328 else if (Cpu.prefix & DISPREFIX_REP) 329 329 { 330 330 switch (Cpu.pCurInstr->opcode) -
trunk/src/VBox/VMM/VMMR3/EMRaw.cpp
r40451 r41675 428 428 VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR; 429 429 430 if (!(Cpu.prefix & ( PREFIX_REP |PREFIX_REPNE)))430 if (!(Cpu.prefix & (DISPREFIX_REP | DISPREFIX_REPNE))) 431 431 { 432 432 switch (Cpu.pCurInstr->opcode) … … 447 447 } 448 448 } 449 else if (Cpu.prefix & PREFIX_REP)449 else if (Cpu.prefix & DISPREFIX_REP) 450 450 { 451 451 switch (Cpu.pCurInstr->opcode) … … 684 684 { 685 685 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), 686 (SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);686 (SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0); 687 687 if (RT_SUCCESS(rc)) 688 688 { … … 934 934 { 935 935 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), 936 (SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);936 (SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0); 937 937 if (RT_SUCCESS(rc)) 938 938 { … … 1041 1041 if ( (pCtx->ss & X86_SEL_RPL) == 0 1042 1042 && !pCtx->eflags.Bits.u1VM 1043 && SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)1043 && SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) 1044 1044 { 1045 1045 STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a); -
trunk/src/VBox/VMM/VMMR3/PATM.cpp
r41674 r41675 604 604 disinfo.fReadFlags = fReadFlags; 605 605 return RT_SUCCESS(DISInstrToStrWithReader(InstrGCPtr32, 606 (pPatch->flags & PATMFL_CODE32) ? CPUMODE_32BIT :CPUMODE_16BIT,606 (pPatch->flags & PATMFL_CODE32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, 607 607 patmReadBytes, &disinfo, 608 608 pCpu, pcbInstr, pszOutput, cbOutput)); … … 620 620 disinfo.fReadFlags = fReadFlags; 621 621 return RT_SUCCESS(DISInstrWithReader(InstrGCPtr32, 622 (pPatch->flags & PATMFL_CODE32) ? CPUMODE_32BIT :CPUMODE_16BIT,622 (pPatch->flags & PATMFL_CODE32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, 623 623 patmReadBytes, &disinfo, 624 624 pCpu, pcbInstr)); … … 1654 1654 */ 1655 1655 Log(("patmRecompileCallback: jump to code we've recompiled before %RRv!\n", pCurInstrGC)); 1656 return patmPatchGenRelJump(pVM, pPatch, pCurInstrGC, OP_JMP, !!(pCpu->prefix & PREFIX_OPSIZE));1656 return patmPatchGenRelJump(pVM, pPatch, pCurInstrGC, OP_JMP, !!(pCpu->prefix & DISPREFIX_OPSIZE)); 1657 1657 } 1658 1658 … … 1713 1713 } 1714 1714 else 1715 rc = patmPatchGenRelJump(pVM, pPatch, pTargetGC, pCpu->pCurInstr->opcode, !!(pCpu->prefix & PREFIX_OPSIZE));1715 rc = patmPatchGenRelJump(pVM, pPatch, pTargetGC, pCpu->pCurInstr->opcode, !!(pCpu->prefix & DISPREFIX_OPSIZE)); 1716 1716 1717 1717 if (RT_SUCCESS(rc)) … … 1855 1855 fGenerateJmpBack = false; 1856 1856 1857 rc = patmPatchGenPopf(pVM, pPatch, pCurInstrGC + pCpu->opsize, !!(pCpu->prefix & PREFIX_OPSIZE), fGenerateJmpBack);1857 rc = patmPatchGenPopf(pVM, pPatch, pCurInstrGC + pCpu->opsize, !!(pCpu->prefix & DISPREFIX_OPSIZE), fGenerateJmpBack); 1858 1858 if (RT_SUCCESS(rc)) 1859 1859 { … … 1873 1873 1874 1874 case OP_PUSHF: 1875 rc = patmPatchGenPushf(pVM, pPatch, !!(pCpu->prefix & PREFIX_OPSIZE));1875 rc = patmPatchGenPushf(pVM, pPatch, !!(pCpu->prefix & DISPREFIX_OPSIZE)); 1876 1876 if (RT_SUCCESS(rc)) 1877 1877 rc = VWRN_CONTINUE_RECOMPILE; … … 1890 1890 case OP_IRET: 1891 1891 Log(("IRET at %RRv\n", pCurInstrGC)); 1892 rc = patmPatchGenIret(pVM, pPatch, pCurInstrGC, !!(pCpu->prefix & PREFIX_OPSIZE));1892 rc = patmPatchGenIret(pVM, pPatch, pCurInstrGC, !!(pCpu->prefix & DISPREFIX_OPSIZE)); 1893 1893 if (RT_SUCCESS(rc)) 1894 1894 { … … 3217 3217 pPatch->uCurPatchOffset = 0; 3218 3218 3219 cpu.mode = (pPatch->flags & PATMFL_CODE32) ? CPUMODE_32BIT :CPUMODE_16BIT;3219 cpu.mode = (pPatch->flags & PATMFL_CODE32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; 3220 3220 3221 3221 /* Note: Set the PATM interrupt flag here; it was cleared before the patched call. (!!!) */ … … 4212 4212 pPatchRec->patch.pPrivInstrGC = pInstrGC; 4213 4213 pPatchRec->patch.flags = flags; 4214 pPatchRec->patch.uOpMode = (flags & PATMFL_CODE32) ? CPUMODE_32BIT :CPUMODE_16BIT;4214 pPatchRec->patch.uOpMode = (flags & PATMFL_CODE32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; 4215 4215 pPatchRec->patch.pTrampolinePatchesHead = NULL; 4216 4216 … … 6457 6457 if (disret && (cpu.pCurInstr->opcode == OP_SYSEXIT || cpu.pCurInstr->opcode == OP_HLT || cpu.pCurInstr->opcode == OP_INT3)) 6458 6458 { 6459 cpu.mode = (pPatch->patch.flags & PATMFL_CODE32) ? CPUMODE_32BIT :CPUMODE_16BIT;6459 cpu.mode = (pPatch->patch.flags & PATMFL_CODE32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; 6460 6460 disret = patmR3DisInstr(pVM, &pPatch->patch, pNewEip, PATMGCVirtToHCVirt(pVM, &cacheRec, pNewEip), PATMREAD_RAWCODE, 6461 6461 &cpu, &opsize); -
trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp
r41663 r41675 701 701 offset = 0; 702 702 /* include prefix byte to make sure we don't use the incorrect selector register. */ 703 if (pCpu->prefix & PREFIX_SEG)703 if (pCpu->prefix & DISPREFIX_SEG) 704 704 pPB[offset++] = DISQuerySegPrefixByte(pCpu); 705 705 pPB[offset++] = 0xFF; // push r/m32 706 706 pPB[offset++] = MAKE_MODRM(pCpu->ModRM.Bits.Mod, 6 /* group 5 */, pCpu->ModRM.Bits.Rm); 707 707 i = 2; /* standard offset of modrm bytes */ 708 if (pCpu->prefix & PREFIX_OPSIZE)708 if (pCpu->prefix & DISPREFIX_OPSIZE) 709 709 i++; //skip operand prefix 710 if (pCpu->prefix & PREFIX_SEG)710 if (pCpu->prefix & DISPREFIX_SEG) 711 711 i++; //skip segment prefix 712 712 … … 797 797 offset = 0; 798 798 /* include prefix byte to make sure we don't use the incorrect selector register. */ 799 if (pCpu->prefix & PREFIX_SEG)799 if (pCpu->prefix & DISPREFIX_SEG) 800 800 pPB[offset++] = DISQuerySegPrefixByte(pCpu); 801 801 … … 803 803 pPB[offset++] = MAKE_MODRM(pCpu->ModRM.Bits.Mod, 6 /* group 5 */, pCpu->ModRM.Bits.Rm); 804 804 i = 2; /* standard offset of modrm bytes */ 805 if (pCpu->prefix & PREFIX_OPSIZE)805 if (pCpu->prefix & DISPREFIX_OPSIZE) 806 806 i++; //skip operand prefix 807 if (pCpu->prefix & PREFIX_SEG)807 if (pCpu->prefix & DISPREFIX_SEG) 808 808 i++; //skip segment prefix 809 809 … … 1276 1276 PATCHGEN_PROLOG_NODEF(pVM, pPatch); 1277 1277 offset = 0; 1278 if (pCpu->prefix & PREFIX_OPSIZE)1278 if (pCpu->prefix & DISPREFIX_OPSIZE) 1279 1279 pPB[offset++] = 0x66; /* size override -> 16 bits push */ 1280 1280 pPB[offset++] = 0x16; … … 1289 1289 PATCHGEN_PROLOG_NODEF(pVM, pPatch); 1290 1290 offset = 0; 1291 if (pCpu->prefix & PREFIX_OPSIZE)1291 if (pCpu->prefix & DISPREFIX_OPSIZE) 1292 1292 pPB[offset++] = 0x66; /* size override -> 16 bits pop */ 1293 1293 pPB[offset++] = 0x58 + pCpu->param1.base.reg_gen; … … 1320 1320 1321 1321 /** @todo segment prefix (untested) */ 1322 Assert(pCpu->prefix == PREFIX_NONE || pCpu->prefix ==PREFIX_OPSIZE);1322 Assert(pCpu->prefix == DISPREFIX_NONE || pCpu->prefix == DISPREFIX_OPSIZE); 1323 1323 1324 1324 PATCHGEN_PROLOG(pVM, pPatch); … … 1329 1329 // 8B 15 [32 bits addr] mov edx, CPUMCTX.tr/ldtr 1330 1330 1331 if (pCpu->prefix == PREFIX_OPSIZE)1331 if (pCpu->prefix == DISPREFIX_OPSIZE) 1332 1332 pPB[offset++] = 0x66; 1333 1333 … … 1360 1360 pPB[offset++] = 0x52; // push edx 1361 1361 1362 if (pCpu->prefix == PREFIX_SEG)1362 if (pCpu->prefix == DISPREFIX_SEG) 1363 1363 { 1364 1364 pPB[offset++] = DISQuerySegPrefixByte(pCpu); … … 1369 1369 1370 1370 i = 3; /* standard offset of modrm bytes */ 1371 if (pCpu->prefix == PREFIX_OPSIZE)1371 if (pCpu->prefix == DISPREFIX_OPSIZE) 1372 1372 i++; //skip operand prefix 1373 if (pCpu->prefix == PREFIX_SEG)1373 if (pCpu->prefix == DISPREFIX_SEG) 1374 1374 i++; //skip segment prefix 1375 1375 … … 1420 1420 1421 1421 /* @todo segment prefix (untested) */ 1422 Assert(pCpu->prefix == PREFIX_NONE);1422 Assert(pCpu->prefix == DISPREFIX_NONE); 1423 1423 1424 1424 // sgdt %Ms … … 1455 1455 pPB[offset++] = 0x52; // push edx 1456 1456 1457 if (pCpu->prefix == PREFIX_SEG)1457 if (pCpu->prefix == DISPREFIX_SEG) 1458 1458 { 1459 1459 pPB[offset++] = DISQuerySegPrefixByte(pCpu); … … 1464 1464 1465 1465 i = 3; /* standard offset of modrm bytes */ 1466 if (pCpu->prefix == PREFIX_OPSIZE)1466 if (pCpu->prefix == DISPREFIX_OPSIZE) 1467 1467 i++; //skip operand prefix 1468 if (pCpu->prefix == PREFIX_SEG)1468 if (pCpu->prefix == DISPREFIX_SEG) 1469 1469 i++; //skip segment prefix 1470 1470 rc = patmPatchReadBytes(pVM, &pPB[offset], (RTRCPTR)((RTGCUINTPTR32)pCurInstrGC + i), pCpu->opsize - i); -
trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp
r41674 r41675 835 835 DISCPUSTATE Cpu; 836 836 char szDisas[256]; 837 int rc = DISInstr(pu8CodeR3 + offCode, CPUMODE_32BIT, &Cpu, &cbInstr);837 int rc = DISInstr(pu8CodeR3 + offCode, DISCPUMODE_32BIT, &Cpu, &cbInstr); 838 838 if (RT_SUCCESS(rc)) 839 839 { -
trunk/src/VBox/VMM/VMMRC/PATMRC.cpp
r41674 r41675 511 511 512 512 cpu.mode = SELMGetCpuModeFromSelector(VMMGetCpu0(pVM), pRegFrame->eflags, pRegFrame->cs, 0); 513 if (cpu.mode != CPUMODE_32BIT)513 if (cpu.mode != DISCPUMODE_32BIT) 514 514 { 515 515 AssertFailed(); -
trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp
r41658 r41675 542 542 * Speed up dtrace and don't entrust invalid lock sequences to the recompiler. 543 543 */ 544 else if (Cpu.prefix & PREFIX_LOCK)544 else if (Cpu.prefix & DISPREFIX_LOCK) 545 545 { 546 546 Log(("TRPMGCTrap06Handler: pc=%08x op=%d\n", pRegFrame->eip, Cpu.pCurInstr->opcode)); -
trunk/src/VBox/VMM/include/EMHandleRCTmpl.h
r41168 r41675 112 112 case VINF_PATM_HC_MMIO_PATCH_READ: 113 113 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), 114 PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));114 PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0)); 115 115 if (RT_FAILURE(rc)) 116 116 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO"); -
trunk/src/VBox/VMM/testcase/tstCompiler.cpp
r41669 r41675 207 207 char sz[256]; 208 208 uint32_t cbInstr = 0; 209 if (RT_SUCCESS(DISInstrToStr(pbCur, CPUMODE_32BIT, &Cpu, &cbInstr, sz, sizeof(sz))))209 if (RT_SUCCESS(DISInstrToStr(pbCur, DISCPUMODE_32BIT, &Cpu, &cbInstr, sz, sizeof(sz)))) 210 210 { 211 211 RTPrintf("tstBitFields: %s", sz);
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