Changeset 48213 in vbox for trunk/src/VBox
- Timestamp:
- Aug 30, 2013 11:17:51 PM (11 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 3 edited
-
VMMR0/HMR0.cpp (modified) (3 diffs)
-
VMMR3/HM.cpp (modified) (13 diffs)
-
include/HMInternal.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HMR0.cpp
r48212 r48213 147 147 { 148 148 /* HWCR MSR (for diagnostics) */ 149 uint64_t msrHwcr;149 uint64_t u64MsrHwcr; 150 150 151 151 /** SVM revision. */ … … 618 618 { 619 619 /* Read the HWCR MSR for diagnostics. */ 620 g_HvmR0.svm. msrHwcr= ASMRdMsr(MSR_K8_HWCR);620 g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR); 621 621 g_HvmR0.svm.fSupported = true; 622 622 } … … 1266 1266 pVM->hm.s.vmx.msr.u64Vmfunc = g_HvmR0.vmx.msr.u64Vmfunc; 1267 1267 pVM->hm.s.vmx.msr.u64EptVpidCaps = g_HvmR0.vmx.msr.u64EptVpidCaps; 1268 pVM->hm.s.svm. msrHwcr = g_HvmR0.svm.msrHwcr;1268 pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr; 1269 1269 pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev; 1270 1270 pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features; -
trunk/src/VBox/VMM/VMMR3/HM.cpp
r48212 r48213 277 277 do { \ 278 278 if ((allowed1) & (featflag)) \ 279 LogRel(("HM: 279 LogRel(("HM: " #featflag "\n")); \ 280 280 else \ 281 LogRel(("HM: 281 LogRel(("HM: " #featflag " *must* be cleared\n")); \ 282 282 if ((disallowed0) & (featflag)) \ 283 LogRel(("HM: 283 LogRel(("HM: " #featflag " *must* be set\n")); \ 284 284 } while (0) 285 285 … … 287 287 do { \ 288 288 if ((allowed1) & (featflag)) \ 289 LogRel(("HM: 289 LogRel(("HM: " #featflag "\n")); \ 290 290 else \ 291 LogRel(("HM: 291 LogRel(("HM: " #featflag " not supported\n")); \ 292 292 } while (0) 293 293 … … 295 295 do { \ 296 296 if ((msrcaps) & (cap)) \ 297 LogRel(("HM: 297 LogRel(("HM: " #cap "\n")); \ 298 298 } while (0) 299 299 … … 979 979 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.msr.u64FeatureCtrl)); 980 980 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.msr.u64BasicInfo)); 981 LogRel(("HM: VMCS id= %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.u64BasicInfo)));982 LogRel(("HM: VMCS size= %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.u64BasicInfo)));983 LogRel(("HM: VMCS physical address limit= %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.u64BasicInfo) ? "< 4 GB" : "None"));984 LogRel(("HM: VMCS memory type= %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.u64BasicInfo)));985 LogRel(("HM: Dual-monitor treatment support= %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.u64BasicInfo)));986 LogRel(("HM: OUTS & INS instruction-info= %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.u64BasicInfo)));981 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.u64BasicInfo))); 982 LogRel(("HM: VMCS size = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.u64BasicInfo))); 983 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.u64BasicInfo) ? "< 4 GB" : "None")); 984 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.u64BasicInfo))); 985 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.u64BasicInfo))); 986 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.u64BasicInfo))); 987 987 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops)); 988 988 … … 1093 1093 } 1094 1094 1095 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", pVM->hm.s.vmx.msr.u64Misc)); 1096 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.u64Misc) == pVM->hm.s.vmx.cPreemptTimerShift) 1097 { 1098 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x\n", 1099 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.u64Misc))); 1100 } 1095 val = pVM->hm.s.vmx.msr.u64Misc; 1096 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val)); 1097 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift) 1098 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val))); 1101 1099 else 1102 1100 { 1103 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n", 1104 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.u64Misc), pVM->hm.s.vmx.cPreemptTimerShift)); 1105 } 1106 1107 val = pVM->hm.s.vmx.msr.u64Misc; 1108 LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %RTbool\n", !!MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))); 1109 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val))); 1110 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val))); 1111 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val))); 1112 LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %RTbool\n", !!MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))); 1113 LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %RTbool\n", !!MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))); 1114 LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %RTbool\n", !!MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))); 1115 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val))); 1101 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n", 1102 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift)); 1103 } 1104 1105 LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %RTbool\n", !!MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))); 1106 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val))); 1107 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val))); 1108 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val))); 1109 LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %RTbool\n", !!MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))); 1110 LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %RTbool\n", !!MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))); 1111 LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %RTbool\n", !!MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))); 1112 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val))); 1116 1113 1117 1114 /* Paranoia */ … … 1125 1122 val = pVM->hm.s.vmx.msr.u64VmcsEnum; 1126 1123 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val)); 1127 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX= %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));1124 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val))); 1128 1125 1129 1126 val = pVM->hm.s.vmx.msr.u64Vmfunc; … … 1284 1281 { 1285 1282 LogRel(("HM: Nested paging enabled!\n")); 1286 LogRel(("HM: EPT root page physaddr = %#RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));1287 1283 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT) 1288 LogRel(("HM: EPT flush type= VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));1284 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n")); 1289 1285 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS) 1290 LogRel(("HM: EPT flush type= VMX_FLUSH_EPT_ALL_CONTEXTS\n"));1286 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n")); 1291 1287 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED) 1292 LogRel(("HM: EPT flush type= VMX_FLUSH_EPT_NOT_SUPPORTED\n"));1288 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n")); 1293 1289 else 1294 LogRel(("HM: EPT flush type= %d\n", pVM->hm.s.vmx.enmFlushEpt));1290 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt)); 1295 1291 1296 1292 if (pVM->hm.s.vmx.fUnrestrictedGuest) … … 1313 1309 LogRel(("HM: VPID enabled!\n")); 1314 1310 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR) 1315 LogRel(("HM: VPID flush type= VMX_FLUSH_VPID_INDIV_ADDR\n"));1311 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n")); 1316 1312 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT) 1317 LogRel(("HM: VPID flush type= VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));1313 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n")); 1318 1314 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS) 1319 LogRel(("HM: VPID flush type= VMX_FLUSH_VPID_ALL_CONTEXTS\n"));1315 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n")); 1320 1316 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS) 1321 LogRel(("HM: VPID flush type= VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));1317 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n")); 1322 1318 else 1323 LogRel(("HM: VPID flush type= %d\n", pVM->hm.s.vmx.enmFlushVpid));1319 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid)); 1324 1320 } 1325 1321 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED) … … 1363 1359 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX)); 1364 1360 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX)); 1365 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm. msrHwcr));1361 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr)); 1366 1362 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev)); 1367 1363 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid)); … … 1392 1388 if (fSvmFeatures & s_aSvmFeatures[i].fFlag) 1393 1389 { 1394 LogRel(("HM: 1390 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName)); 1395 1391 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag; 1396 1392 } … … 1398 1394 for (unsigned iBit = 0; iBit < 32; iBit++) 1399 1395 if (RT_BIT_32(iBit) & fSvmFeatures) 1400 LogRel(("HM: 1396 LogRel(("HM: Reserved bit %u\n", iBit)); 1401 1397 1402 1398 /* … … 1422 1418 if (pVM->hm.s.fNestedPaging) 1423 1419 { 1424 LogRel(("HM: 1420 LogRel(("HM: Nested paging enabled!\n")); 1425 1421 1426 1422 /* … … 1431 1427 { 1432 1428 PGMSetLargePageUsage(pVM, true); 1433 LogRel(("HM: 1429 LogRel(("HM: Large page support enabled!\n")); 1434 1430 } 1435 1431 #endif -
trunk/src/VBox/VMM/include/HMInternal.h
r48212 r48213 404 404 405 405 /* HWCR MSR (for diagnostics) */ 406 uint64_t msrHwcr;406 uint64_t u64MsrHwcr; 407 407 408 408 /** SVM revision. */
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