Changeset 49893 in vbox for trunk/src

Timestamp:

Dec 13, 2013 12:40:20 AM (11 years ago)

Author:

vboxsync

Message:

MSR rewrite: initial hacking - half disabled.

Location:

trunk/src/VBox/VMM

Files:

• Makefile.kmk (modified) (8 diffs)
• VMMAll/CPUMAllMsrs.cpp (added)
• VMMAll/CPUMAllRegs.cpp (modified) (27 diffs)
• VMMAll/MMAll.cpp (modified) (1 diff)
• VMMAll/MMAllHyper.cpp (modified) (3 diffs)
• VMMR0/CPUMR0.cpp (modified) (4 diffs)
• VMMR0/HMVMXR0.cpp (modified) (2 diffs)
• VMMR3/CPUM.cpp (modified) (55 diffs)
• VMMR3/CPUMR3CpuId.cpp (added)
• VMMR3/CPUMR3Db.cpp (added)
• VMMR3/EM.cpp (modified) (1 diff)
• VMMR3/PGM.cpp (modified) (1 diff)
• VMMR3/VM.cpp (modified) (1 diff)
• VMMR3/VMM.cpp (modified) (1 diff)
• VMMR3/VMMTests.cpp (modified) (2 diffs)
• VMMRC/VMMRC.cpp (modified) (3 diffs)
• VMMRC/VMMRCA.asm (modified) (4 diffs)
• include/CPUMInternal.h (modified) (7 diffs)
• include/CPUMInternal.mac (modified) (2 diffs)
• testcase/tstVMStruct.h (modified) (1 diff)
• tools/Makefile.kmk (modified) (1 diff)
• tools/VBoxCpuReport.cpp (added)

trunk/src/VBox/VMM/Makefile.kmk

@@ -77 +77 @@
 endif
 
+ifdef VBOX_WITH_NEW_MSR_CODE
+ VMM_COMMON_DEFS += VBOX_WITH_NEW_MSR_CODE
+endif
+
 
 #
@@ -118 +122 @@
         VMMR3/CFGM.cpp \
         VMMR3/CPUM.cpp \
+        VMMR3/CPUMR3CpuId.cpp \
+        VMMR3/CPUMR3Db.cpp \
         VMMR3/CPUMDbg.cpp \
         VMMR3/DBGF.cpp \
@@ -187 +193 @@
        ,) \
         VMMAll/CPUMAllRegs.cpp \
+        VMMAll/CPUMAllMsrs.cpp \
         VMMAll/CPUMStack.cpp \
         VMMAll/DBGFAll.cpp \
@@ -438 +445 @@
         VMMRZ/VMMRZ.cpp \
         VMMAll/CPUMAllRegs.cpp \
+        VMMAll/CPUMAllMsrs.cpp \
         VMMAll/DBGFAll.cpp \
         VMMAll/IEMAll.cpp \
@@ -540 +548 @@
         VMMRZ/VMMRZ.cpp \
         VMMAll/CPUMAllRegs.cpp \
+        VMMAll/CPUMAllMsrs.cpp \
         VMMAll/CPUMStack.cpp \
         VMMAll/DBGFAll.cpp \
@@ -610 +619 @@
  LIBRARIES += SSMStandalone
  SSMStandalone_TEMPLATE = VBOXR3EXE
- SSMStandalone_DEFS     = IN_VMM_R3 IN_VMM_STATIC SSM_STANDALONE
+ SSMStandalone_DEFS     = IN_VMM_R3 IN_VMM_STATIC SSM_STANDALONE CPUM_DB_STANDALONE
  SSMStandalone_INCS     = include
- SSMStandalone_SOURCES  = VMMR3/SSM.cpp
+ SSMStandalone_SOURCES  = \
+        VMMR3/SSM.cpp \
+        VMMR3/CPUMR3Db.cpp
 endif # !VBOX_ONLY_EXTPACKS
 
@@ -704 +715 @@
 endif # bird wants good stacks
 
+
+# Alias the CPU database entries.
+$(foreach base,$(notdir $(basename $(wildcard $(PATH_SUB_CURRENT)/VMMR3/cpus/*.h))), $(eval $(base).o $(base).obj: CPUMR3Db.o))
+
+
 include $(FILE_KBUILD_SUB_FOOTER)
 
@@ -732 +748 @@
 LegacyandAMD64.o LegacyandAMD64.obj:           32BitToAMD64.o PAEToAMD64.o
 AMD64andLegacy.o AMD64andLegacy.obj:           AMD64To32Bit.o AMD64ToPAE.o
+

trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

@@ -870 +870 @@
 }
 
+#ifndef VBOX_WITH_NEW_MSR_CODE
 
 /**
@@ -1585 +1586 @@
 }
 
+#endif /* !VBOX_WITH_NEW_MSR_CODE */
+
 
 VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
@@ -1849 +1852 @@
 {
     return pVCpu->cpum.s.Guest.msrEFER;
+}
+
+
+/**
+ * Looks up a CPUID leaf in the CPUID leaf array.
+ *
+ * @returns Pointer to the leaf if found, NULL if not.
+ *
+ * @param   pVM                 Pointer to the cross context VM structure.
+ * @param   uLeaf               The leaf to get.
+ * @param   uSubLeaf            The subleaf, if applicable.  Just pass 0 if it
+ *                              isn't.
+ */
+PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf)
+{
+    unsigned            iEnd     = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
+    if (iEnd)
+    {
+        unsigned        iStart   = 0;
+        PCPUMCPUIDLEAF  paLeaves = pVM->cpum.s.GuestInfo.CTX_SUFF(paCpuIdLeaves);
+        for (;;)
+        {
+            unsigned i = iStart + (iEnd - iStart) / 2U;
+            if (uLeaf < paLeaves[i].uLeaf)
+            {
+                if (i <= iStart)
+                    return NULL;
+                iEnd = i;
+            }
+            else if (uLeaf > paLeaves[i].uLeaf)
+            {
+                i += 1;
+                if (i >= iEnd)
+                    return NULL;
+                iStart = i;
+            }
+            else
+            {
+                uSubLeaf &= paLeaves[i].fSubLeafMask;
+                if (uSubLeaf != paLeaves[i].uSubLeaf)
+                {
+                    /* Find the right subleaf.  We return the last one before
+                       uSubLeaf if we don't find an exact match. */
+                    if (uSubLeaf < paLeaves[i].uSubLeaf)
+                        while (   i > 0
+                               && uLeaf    == paLeaves[i].uLeaf
+                               && uSubLeaf  < paLeaves[i].uSubLeaf)
+                            i--;
+                    else
+                        while (   i + 1 < pVM->cpum.s.GuestInfo.cCpuIdLeaves
+                               && uLeaf    == paLeaves[i + 1].uLeaf
+                               && uSubLeaf >= paLeaves[i + 1].uSubLeaf)
+                            i++;
+                }
+                return &paLeaves[i];
+            }
+        }
+    }
+
+    return NULL;
 }
 
@@ -1895 +1958 @@
     if (    iLeaf == 4
         &&  cCurrentCacheIndex < 3
-        &&  pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
+        &&  pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
     {
         uint32_t type, level, sharing, linesize,
@@ -1997 +2060 @@
 VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
 {
+    PCPUMCPUIDLEAF pLeaf;
+
     switch (enmFeature)
     {
@@ -2003 +2068 @@
          */
         case CPUMCPUIDFEATURE_APIC:
-            if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
-                pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
-            if (    pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
-                &&  pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
-                pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_APIC;
+
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (   pLeaf
+                && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
+                pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
+
+            pVM->cpum.s.GuestFeatures.fApic = 1;
             LogRel(("CPUM: SetGuestCpuIdFeature: Enabled APIC\n"));
             break;
@@ -2015 +2085 @@
         */
         case CPUMCPUIDFEATURE_X2APIC:
-            if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
-                pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdStd[1].ecx = pLeaf->uEcx |= X86_CPUID_FEATURE_ECX_X2APIC;
+            pVM->cpum.s.GuestFeatures.fX2Apic = 1;
             LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
             break;
@@ -2025 +2097 @@
          */
         case CPUMCPUIDFEATURE_SEP:
-        {
-            if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
+            if (!pVM->cpum.s.HostFeatures.fSysEnter)
             {
                 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
@@ -2032 +2103 @@
             }
 
-            if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
-                pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_SEP;
+            pVM->cpum.s.GuestFeatures.fSysEnter = 1;
             LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
             break;
-        }
 
         /*
@@ -2043 +2115 @@
          */
         case CPUMCPUIDFEATURE_SYSCALL:
-        {
-            if (    pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
-                ||  !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (   !pLeaf
+                || !pVM->cpum.s.HostFeatures.fSysCall)
             {
 #if HC_ARCH_BITS == 32
-                /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode.
-                 * Even when the cpu is capable of doing so in 64 bits mode.
-                 */
-                if (    pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
-                    ||  !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
-                    ||  !(ASMCpuId_EDX(1) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
+                /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
+                   mode by Intel, even when the cpu is capable of doing so in
+                   64-bit mode.  Long mode requires syscall support. */
+                if (!pVM->cpum.s.HostFeatures.fLongMode)
 #endif
                 {
@@ -2060 +2130 @@
                 }
             }
+
             /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
-            pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
+            pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
+            pVM->cpum.s.GuestFeatures.fSysCall = 1;
             LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
             break;
-        }
 
         /*
@@ -2071 +2142 @@
          */
         case CPUMCPUIDFEATURE_PAE:
-        {
-            if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
+            if (!pVM->cpum.s.HostFeatures.fPae)
             {
                 LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
@@ -2078 +2148 @@
             }
 
-            if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
-                pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
-            if (    pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
-                &&  pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
-                pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_PAE;
+
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (    pLeaf
+                &&  pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
+                pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
+
+            pVM->cpum.s.GuestFeatures.fPae = 1;
             LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
             break;
-        }
 
         /*
@@ -2092 +2166 @@
          */
         case CPUMCPUIDFEATURE_LONG_MODE:
-        {
-            if (    pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
-                ||  !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (   !pLeaf
+                || !pVM->cpum.s.HostFeatures.fLongMode)
             {
                 LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
@@ -2101 +2175 @@
 
             /* Valid for both Intel and AMD. */
-            pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
+            pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
+            pVM->cpum.s.GuestFeatures.fLongMode = 1;
             LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
             break;
-        }
 
         /*
@@ -2111 +2185 @@
          */
         case CPUMCPUIDFEATURE_NX:
-        {
-            if (    pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
-                ||  !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (   !pLeaf
+                || !pVM->cpum.s.HostFeatures.fNoExecute)
             {
                 LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
@@ -2120 +2194 @@
 
             /* Valid for both Intel and AMD. */
-            pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_NX;
+            pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_NX;
+            pVM->cpum.s.GuestFeatures.fNoExecute = 1;
             LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
             break;
-        }
+
 
         /*
@@ -2130 +2205 @@
          */
         case CPUMCPUIDFEATURE_LAHF:
-        {
-            if (    pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
-                ||  !(ASMCpuId_ECX(0x80000001) & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF))
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (   !pLeaf
+                || !pVM->cpum.s.HostFeatures.fLahfSahf)
             {
                 LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
@@ -2139 +2214 @@
 
             /* Valid for both Intel and AMD. */
-            pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
+            pVM->cpum.s.aGuestCpuIdExt[1].ecx = pLeaf->uEcx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
+            pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
             LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
             break;
-        }
-
+
+        /*
+         * Set the page attribute table bit.  This is alternative page level
+         * cache control that doesn't much matter when everything is
+         * virtualized, though it may when passing thru device memory.
+         */
         case CPUMCPUIDFEATURE_PAT:
-        {
-            if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
-                pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
-            if (    pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
-                &&  pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
-                pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_PAT;
+
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (   pLeaf
+                && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
+                pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
+
+            pVM->cpum.s.GuestFeatures.fPat = 1;
             LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
             break;
-        }
 
         /*
@@ -2160 +2243 @@
          */
         case CPUMCPUIDFEATURE_RDTSCP:
-        {
-            if (    pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
-                ||  !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
-                ||  pVM->cpum.s.u8PortableCpuIdLevel > 0)
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (   !pLeaf
+                || !pVM->cpum.s.HostFeatures.fRdTscP
+                || pVM->cpum.s.u8PortableCpuIdLevel > 0)
             {
                 if (!pVM->cpum.s.u8PortableCpuIdLevel)
@@ -2171 +2254 @@
 
             /* Valid for both Intel and AMD. */
-            pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
+            pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
+            pVM->cpum.s.HostFeatures.fRdTscP = 1;
             LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
             break;
-        }
 
        /*
@@ -2180 +2263 @@
         */
         case CPUMCPUIDFEATURE_HVP:
-            if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0);
+            if (pLeaf)
                 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
+            pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
             LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
             break;
@@ -2189 +2274 @@
             break;
     }
+
     for (VMCPUID i = 0; i < pVM->cCpus; i++)
     {
@@ -2208 +2294 @@
     switch (enmFeature)
     {
+        case CPUMCPUIDFEATURE_APIC:         return pVM->cpum.s.GuestFeatures.fApic;
+        case CPUMCPUIDFEATURE_X2APIC:       return pVM->cpum.s.GuestFeatures.fX2Apic;
+        case CPUMCPUIDFEATURE_SYSCALL:      return pVM->cpum.s.GuestFeatures.fSysCall;
+        case CPUMCPUIDFEATURE_SEP:          return pVM->cpum.s.GuestFeatures.fSysEnter;
+        case CPUMCPUIDFEATURE_PAE:          return pVM->cpum.s.GuestFeatures.fPae;
+        case CPUMCPUIDFEATURE_NX:           return pVM->cpum.s.GuestFeatures.fNoExecute;
+        case CPUMCPUIDFEATURE_LAHF:         return pVM->cpum.s.GuestFeatures.fLahfSahf;
+        case CPUMCPUIDFEATURE_LONG_MODE:    return pVM->cpum.s.GuestFeatures.fLongMode;
+        case CPUMCPUIDFEATURE_PAT:          return pVM->cpum.s.GuestFeatures.fPat;
+        case CPUMCPUIDFEATURE_RDTSCP:       return pVM->cpum.s.GuestFeatures.fRdTscP;
+        case CPUMCPUIDFEATURE_HVP:          return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
+
+        case CPUMCPUIDFEATURE_INVALID:
+        case CPUMCPUIDFEATURE_32BIT_HACK:
+            break;
+    }
+    AssertFailed();
+    return false;
+}
+
+
+/**
+ * Clears a CPUID feature bit.
+ *
+ * @param   pVM             Pointer to the VM.
+ * @param   enmFeature      The feature to clear.
+ */
+VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
+{
+    PCPUMCPUIDLEAF pLeaf;
+    switch (enmFeature)
+    {
+        case CPUMCPUIDFEATURE_APIC:
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
+
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (   pLeaf
+                && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
+                pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
+
+            pVM->cpum.s.GuestFeatures.fApic = 0;
+            Log(("CPUM: ClearGuestCpuIdFeature: Disabled APIC\n"));
+            break;
+
+        case CPUMCPUIDFEATURE_X2APIC:
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdStd[1].ecx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
+            pVM->cpum.s.GuestFeatures.fX2Apic = 0;
+            Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
+            break;
+
         case CPUMCPUIDFEATURE_PAE:
-        {
-            if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
-                return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
-            break;
-        }
-
-        case CPUMCPUIDFEATURE_NX:
-        {
-            if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
-                return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_NX);
-        }
-
-        case CPUMCPUIDFEATURE_SYSCALL:
-        {
-            if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
-                return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
-        }
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
+
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (   pLeaf
+                && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
+                pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
+
+            pVM->cpum.s.GuestFeatures.fPae = 0;
+            Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
+            break;
+
+        case CPUMCPUIDFEATURE_PAT:
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
+
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (   pLeaf
+                && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
+                pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
+
+            pVM->cpum.s.GuestFeatures.fPat = 0;
+            Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
+            break;
+
+        case CPUMCPUIDFEATURE_LONG_MODE:
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
+            pVM->cpum.s.GuestFeatures.fLongMode = 0;
+            break;
+
+        case CPUMCPUIDFEATURE_LAHF:
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdExt[1].ecx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
+            pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
+            break;
 
         case CPUMCPUIDFEATURE_RDTSCP:
-        {
-            if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
-                return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
-            break;
-        }
-
-        case CPUMCPUIDFEATURE_LONG_MODE:
-        {
-            if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
-                return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
-            break;
-        }
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
+            pVM->cpum.s.GuestFeatures.fRdTscP = 0;
+            Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
+            break;
+
+        case CPUMCPUIDFEATURE_HVP:
+            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0);
+            if (pLeaf)
+                pVM->cpum.s.aGuestCpuIdStd[1].ecx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
+            pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
+            break;
 
         default:
@@ -2245 +2409 @@
             break;
     }
-    return false;
-}
-
-
-/**
- * Clears a CPUID feature bit.
- *
- * @param   pVM             Pointer to the VM.
- * @param   enmFeature      The feature to clear.
- */
-VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
-{
-    switch (enmFeature)
-    {
-        /*
-         * Set the APIC bit in both feature masks.
-         */
-        case CPUMCPUIDFEATURE_APIC:
-            if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
-                pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
-            if (    pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
-                &&  pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
-                pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
-            Log(("CPUM: ClearGuestCpuIdFeature: Disabled APIC\n"));
-            break;
-
-        /*
-         * Clear the x2APIC bit in the standard feature mask.
-         */
-        case CPUMCPUIDFEATURE_X2APIC:
-            if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
-                pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
-            Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
-            break;
-
-        case CPUMCPUIDFEATURE_PAE:
-        {
-            if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
-                pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
-            if (    pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
-                &&  pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
-                pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
-            Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
-            break;
-        }
-
-        case CPUMCPUIDFEATURE_PAT:
-        {
-            if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
-                pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
-            if (    pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
-                &&  pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
-                pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
-            Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
-            break;
-        }
-
-        case CPUMCPUIDFEATURE_LONG_MODE:
-        {
-            if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
-                pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
-            break;
-        }
-
-        case CPUMCPUIDFEATURE_LAHF:
-        {
-            if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
-                pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
-            break;
-        }
-
-        case CPUMCPUIDFEATURE_RDTSCP:
-        {
-            if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
-                pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
-            Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
-            break;
-        }
-
-        case CPUMCPUIDFEATURE_HVP:
-            if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
-                pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
-            break;
-
-        default:
-            AssertMsgFailed(("enmFeature=%d\n", enmFeature));
-            break;
-    }
+
     for (VMCPUID i = 0; i < pVM->cCpus; i++)
     {
@@ -2349 +2426 @@
 VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
 {
-    return pVM->cpum.s.enmHostCpuVendor;
+    return (CPUMCPUVENDOR)pVM->cpum.s.HostFeatures.enmCpuVendor;
 }
 
@@ -2361 +2438 @@
 VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
 {
-    return pVM->cpum.s.enmGuestCpuVendor;
+    return (CPUMCPUVENDOR)pVM->cpum.s.GuestFeatures.enmCpuVendor;
 }
 

trunk/src/VBox/VMM/VMMAll/MMAll.cpp

@@ -568 +568 @@
         TAG2STR(CFGM_USER);
 
+        TAG2STR(CPUM_CTX);
+        TAG2STR(CPUM_CPUID);
+        TAG2STR(CPUM_MSRS);
+
         TAG2STR(CSAM);
         TAG2STR(CSAM_PATCH);

trunk/src/VBox/VMM/VMMAll/MMAllHyper.cpp

@@ -322 +322 @@
 }
 
+
 /**
  * Wrapper for mmHyperAllocInternal
@@ -327 +328 @@
 VMMDECL(int) MMHyperAlloc(PVM pVM, size_t cb, unsigned uAlignment, MMTAG enmTag, void **ppv)
 {
-    int rc;
-
-    rc = mmHyperLock(pVM);
+    int rc = mmHyperLock(pVM);
     AssertRCReturn(rc, rc);
 
@@ -339 +338 @@
     return rc;
 }
+
+
+/**
+ * Duplicates a block of memory.
+ */
+VMMDECL(int) MMHyperDupMem(PVM pVM, const void *pvSrc, size_t cb, unsigned uAlignment, MMTAG enmTag, void **ppv)
+{
+    int rc = MMHyperAlloc(pVM, cb, uAlignment, enmTag, ppv);
+    if (RT_SUCCESS(rc))
+        memcpy(*ppv, pvSrc, cb);
+    return rc;
+}
+
 
 /**

trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp

@@ -76 +76 @@
 #endif
 
+/**
+ * CPUID bits to unify among all cores.
+ */
+static struct
+{
+    uint32_t uLeaf;  /**< Leaf to check. */
+    uint32_t ecx;    /**< which bits in ecx to unify between CPUs. */
+    uint32_t edx;    /**< which bits in edx to unify between CPUs. */
+}
+const g_aCpuidUnifyBits[] =
+{
+    {
+        0x00000001,
+        X86_CPUID_FEATURE_ECX_CX16 | X86_CPUID_FEATURE_ECX_MONITOR,
+        X86_CPUID_FEATURE_EDX_CX8
+    }
+};
+
+
 
 /*******************************************************************************
@@ -114 +133 @@
 
 /**
+ *
+ *
  * Check the CPUID features of this particular CPU and disable relevant features
  * for the guest which do not exist on this CPU. We have seen systems where the
@@ -127 +148 @@
 static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void *pvUser1, void *pvUser2)
 {
+    PVM     pVM   = (PVM)pvUser1;
+    PCPUM   pCPUM = &pVM->cpum.s;
+
     NOREF(idCpu); NOREF(pvUser2);
-
-    struct
-    {
-        uint32_t uLeave; /* leave to check */
-        uint32_t ecx;    /* which bits in ecx to unify between CPUs */
-        uint32_t edx;    /* which bits in edx to unify between CPUs */
-    } aCpuidUnify[]
-    =
-    {
-        { 0x00000001, X86_CPUID_FEATURE_ECX_CX16
-                    | X86_CPUID_FEATURE_ECX_MONITOR,
-                      X86_CPUID_FEATURE_EDX_CX8 }
-    };
-    PVM pVM = (PVM)pvUser1;
-    PCPUM pCPUM = &pVM->cpum.s;
-    for (uint32_t i = 0; i < RT_ELEMENTS(aCpuidUnify); i++)
-    {
-        uint32_t uLeave = aCpuidUnify[i].uLeave;
+    for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
+    {
+        /* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
+                 necessarily in the VM process context.  So, we using the
+                 legacy arrays as temporary storage. */
+
+        uint32_t   uLeaf = g_aCpuidUnifyBits[i].uLeaf;
+        PCPUMCPUID pLegacyLeaf;
+        if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
+            pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdStd[uLeaf];
+        else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
+            pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdExt[uLeaf - UINT32_C(0x80000000)];
+        else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
+            pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdCentaur[uLeaf - UINT32_C(0xc0000000)];
+        else
+            continue;
+
         uint32_t eax, ebx, ecx, edx;
-
-        ASMCpuId_Idx_ECX(uLeave, 0, &eax, &ebx, &ecx, &edx);
-        PCPUMCPUID paLeaves;
-        if (uLeave < 0x80000000)
-            paLeaves = &pCPUM->aGuestCpuIdStd[uLeave - 0x00000000];
-        else if (uLeave < 0xc0000000)
-            paLeaves = &pCPUM->aGuestCpuIdExt[uLeave - 0x80000000];
-        else
-            paLeaves = &pCPUM->aGuestCpuIdCentaur[uLeave - 0xc0000000];
-        /* unify important bits */
-        ASMAtomicAndU32(&paLeaves->ecx, ecx | ~aCpuidUnify[i].ecx);
-        ASMAtomicAndU32(&paLeaves->edx, edx | ~aCpuidUnify[i].edx);
+        ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
+
+        ASMAtomicAndU32(&pLegacyLeaf->ecx, ecx | ~g_aCpuidUnifyBits[i].ecx);
+        ASMAtomicAndU32(&pLegacyLeaf->edx, edx | ~g_aCpuidUnifyBits[i].edx);
     }
 }
@@ -260 +275 @@
         }
 
+        /*
+         * Unify/cross check some CPUID feature bits on all available CPU cores
+         * and threads.  We've seen CPUs where the monitor support differed.
+         *
+         * Because the hyper heap isn't always mapped into ring-0, we cannot
+         * access it from a RTMpOnAll callback.  We use the legacy CPUID arrays
+         * as temp ring-0 accessible memory instead, ASSUMING that they're all
+         * up to date when we get here.
+         */
         RTMpOnAll(cpumR0CheckCpuid, pVM, NULL);
+
+        for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
+        {
+            uint32_t        uLeaf = g_aCpuidUnifyBits[i].uLeaf;
+            PCPUMCPUIDLEAF  pLeaf = cpumCpuIdGetLeaf(pVM, uLeaf, 0);
+            if (pLeaf)
+            {
+                PCPUMCPUID pLegacyLeaf;
+                if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
+                    pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdStd[uLeaf];
+                else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
+                    pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdExt[uLeaf - UINT32_C(0x80000000)];
+                else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
+                    pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdCentaur[uLeaf - UINT32_C(0xc0000000)];
+                else
+                    continue;
+
+                pLeaf->uEcx = pLegacyLeaf->ecx;
+                pLeaf->uEdx = pLegacyLeaf->edx;
+            }
+        }
+
     }
 

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -5899 +5899 @@
         switch (pMsr->u32Msr)
         {
-            case MSR_K8_TSC_AUX:        CPUMSetGuestMsr(pVCpu, MSR_K8_TSC_AUX, pMsr->u64Value);  break;
+            case MSR_K8_TSC_AUX:        CPUMR0SetGuestTscAux(pVCpu, pMsr->u64Value);             break;
             case MSR_K8_LSTAR:          pMixedCtx->msrLSTAR        = pMsr->u64Value;             break;
             case MSR_K6_STAR:           pMixedCtx->msrSTAR         = pMsr->u64Value;             break;
@@ -8147 +8147 @@
             AssertRC(rc2);
             Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS));
-            uint64_t u64GuestTscAuxMsr;
-            rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAuxMsr);
-            AssertRC(rc2);
-            hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX, u64GuestTscAuxMsr, true /* fUpdateHostMsr */);
+            hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX, CPUMR0GetGuestTscAux(pVCpu), true /* fUpdateHostMsr */);
         }
         else

trunk/src/VBox/VMM/VMMR3/CPUM.cpp

@@ -55 +55 @@
 #include <VBox/err.h>
 #include <VBox/log.h>
+#include <iprt/asm-amd64-x86.h>
 #include <iprt/assert.h>
-#include <iprt/asm-amd64-x86.h>
+#include <iprt/cpuset.h>
+#include <iprt/mem.h>
+#include <iprt/mp.h>
 #include <iprt/string.h>
-#include <iprt/mp.h>
-#include <iprt/cpuset.h>
 #include "internal/pgm.h"
 
@@ -115 +116 @@
 *   Internal Functions                                                         *
 *******************************************************************************/
-static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
 static int cpumR3CpuIdInit(PVM pVM);
 static DECLCALLBACK(int)  cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
@@ -581 +581 @@
 
     /*
-     * Assert alignment and sizes.
+     * Assert alignment, sizes and tables.
      */
     AssertCompileMemberAlignment(VM, cpum.s, 32);
@@ -592 +592 @@
     AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
     AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
+#ifdef VBOX_STRICT
+    int rc2 = cpumR3MsrStrictInitChecks();
+    AssertRCReturn(rc2, rc2);
+#endif
 
     /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
     pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
     Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
+
 
     /* Calculate the offset from CPUMCPU to CPUM. */
@@ -647 +652 @@
 
     /*
-     * Detect the host CPU vendor.
-     * (The guest CPU vendor is re-detected later on.)
-     */
-    uint32_t uEAX, uEBX, uECX, uEDX;
-    ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
-    pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
-    pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
+     * Gather info about the host CPU.
+     */
+    PCPUMCPUIDLEAF  paLeaves;
+    uint32_t        cLeaves;
+    int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
+    AssertLogRelRCReturn(rc, rc);
+
+    rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
+    RTMemFree(paLeaves);
+    AssertLogRelRCReturn(rc, rc);
+    pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
 
     /*
@@ -662 +671 @@
      * Register saved state data item.
      */
-    int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
-                                   NULL, cpumR3LiveExec, NULL,
-                                   NULL, cpumR3SaveExec, NULL,
-                                   cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
+    rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
+                               NULL, cpumR3LiveExec, NULL,
+                               NULL, cpumR3SaveExec, NULL,
+                               cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
     if (RT_FAILURE(rc))
         return rc;
@@ -700 +709 @@
 
 /**
- * Detect the CPU vendor give n the
- *
- * @returns The vendor.
- * @param   uEAX                EAX from CPUID(0).
- * @param   uEBX                EBX from CPUID(0).
- * @param   uECX                ECX from CPUID(0).
- * @param   uEDX                EDX from CPUID(0).
- */
-static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
-{
-    if (ASMIsValidStdRange(uEAX))
-    {
-        if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
-            return CPUMCPUVENDOR_AMD;
-
-        if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
-            return CPUMCPUVENDOR_INTEL;
-
-        if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
-            return CPUMCPUVENDOR_VIA;
-
-        /** @todo detect the other buggers... */
-    }
-
-    return CPUMCPUVENDOR_UNKNOWN;
+ * Loads MSR range overrides.
+ *
+ * This must be called before the MSR ranges are moved from the normal heap to
+ * the hyper heap!
+ *
+ * @returns VBox status code (VMSetError called).
+ * @param   pVM                 Pointer to the cross context VM structure
+ * @param   pMsrNode            The CFGM node with the MSR overrides.
+ */
+static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
+{
+    for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
+    {
+        /*
+         * Assemble a valid MSR range.
+         */
+        CPUMMSRRANGE MsrRange;
+        MsrRange.offCpumCpu = 0;
+        MsrRange.fReserved  = 0;
+
+        int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
+
+        rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
+                              MsrRange.szName, rc);
+
+        rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
+                              MsrRange.szName, rc);
+
+        char szType[32];
+        rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
+                              MsrRange.szName, rc);
+        if (!RTStrICmp(szType, "FixedValue"))
+        {
+            MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
+            MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
+
+            rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uInitOrReadValue, 0);
+            if (RT_FAILURE(rc))
+                return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
+                                  MsrRange.szName, rc);
+
+            rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
+            if (RT_FAILURE(rc))
+                return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
+                                  MsrRange.szName, rc);
+
+            rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
+            if (RT_FAILURE(rc))
+                return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
+                                  MsrRange.szName, rc);
+        }
+        else
+            return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
+                              "Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
+
+        /*
+         * Insert the range into the table (replaces/splits/shrinks existing
+         * MSR ranges).
+         */
+        rc = cpumR3MsrRangesInsert(&pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges, &MsrRange);
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
+    }
+
+    return VINF_SUCCESS;
 }
+
+
+/**
+ * Loads CPUID leaf overrides.
+ *
+ * This must be called before the CPUID leaves are moved from the normal
+ * heap to the hyper heap!
+ *
+ * @returns VBox status code (VMSetError called).
+ * @param   pVM             Pointer to the cross context VM structure
+ * @param   pParentNode     The CFGM node with the CPUID leaves.
+ * @param   pszLabel        How to label the overrides we're loading.
+ */
+static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
+{
+    for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
+    {
+        /*
+         * Get the leaf and subleaf numbers.
+         */
+        char szName[128];
+        int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
+
+        /* The leaf number is either specified directly or thru the node name. */
+        uint32_t uLeaf;
+        rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
+        if (rc == VERR_CFGM_VALUE_NOT_FOUND)
+        {
+            rc = RTStrToUInt32Full(szName, 16, &uLeaf);
+            if (rc != VINF_SUCCESS)
+                return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
+                                  "Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
+        }
+        else if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
+                              pszLabel, szName, rc);
+
+        uint32_t uSubLeaf;
+        rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
+                              pszLabel, szName, rc);
+
+        uint32_t fSubLeafMask;
+        rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
+                              pszLabel, szName, rc);
+
+        /*
+         * Look up the specified leaf, since the output register values
+         * defaults to any existing values.  This allows overriding a single
+         * register, without needing to know the other values.
+         */
+        PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
+                                                   uLeaf, uSubLeaf);
+        CPUMCPUIDLEAF   Leaf;
+        if (pLeaf)
+            Leaf = *pLeaf;
+        else
+            RT_ZERO(Leaf);
+        Leaf.uLeaf          = uLeaf;
+        Leaf.uSubLeaf       = uSubLeaf;
+        Leaf.fSubLeafMask   = fSubLeafMask;
+
+        rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
+                              pszLabel, szName, rc);
+        rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
+                              pszLabel, szName, rc);
+        rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
+                              pszLabel, szName, rc);
+        rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
+                              pszLabel, szName, rc);
+
+        /*
+         * Insert the leaf into the table (replaces existing ones).
+         */
+        rc = cpumR3CpuIdInsert(&pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves, &Leaf);
+        if (RT_FAILURE(rc))
+            return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
+    }
+
+    return VINF_SUCCESS;
+}
+
 
 
@@ -815 +967 @@
 
 
+static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCPUM, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
+{
+    /*
+     * Install the CPUID information.
+     */
+    int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
+                           MM_TAG_CPUM_CPUID, (void **)&pCPUM->GuestInfo.paCpuIdLeavesR3);
+
+    AssertLogRelRCReturn(rc, rc);
+
+    pCPUM->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCPUM->GuestInfo.paCpuIdLeavesR3);
+    pCPUM->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCPUM->GuestInfo.paCpuIdLeavesR3);
+    Assert(MMHyperR0ToR3(pVM, pCPUM->GuestInfo.paCpuIdLeavesR0) == (void *)pCPUM->GuestInfo.paCpuIdLeavesR3);
+    Assert(MMHyperRCToR3(pVM, pCPUM->GuestInfo.paCpuIdLeavesRC) == (void *)pCPUM->GuestInfo.paCpuIdLeavesR3);
+
+    /*
+     * Explode the guest CPU features.
+     */
+    rc = cpumR3CpuIdExplodeFeatures(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, &pCPUM->GuestFeatures);
+    AssertLogRelRCReturn(rc, rc);
+
+
+    /*
+     * Populate the legacy arrays.  Currently used for everything, later only
+     * for patch manager.
+     */
+    struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
+    {
+        { pCPUM->aGuestCpuIdStd,        RT_ELEMENTS(pCPUM->aGuestCpuIdStd),     0x00000000 },
+        { pCPUM->aGuestCpuIdExt,        RT_ELEMENTS(pCPUM->aGuestCpuIdExt),     0x80000000 },
+        { pCPUM->aGuestCpuIdCentaur,    RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), 0xc0000000 },
+        { pCPUM->aGuestCpuIdHyper,      RT_ELEMENTS(pCPUM->aGuestCpuIdHyper),   0x40000000 },
+    };
+    for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
+    {
+        uint32_t    cLeft       = aOldRanges[i].cCpuIds;
+        uint32_t    uLeaf       = aOldRanges[i].uBase + cLeft;
+        PCPUMCPUID  pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
+        while (cLeft-- > 0)
+        {
+            uLeaf--;
+            pLegacyLeaf--;
+
+            PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, uLeaf, 0);
+            if (pLeaf)
+            {
+                pLegacyLeaf->eax = pLeaf->uEax;
+                pLegacyLeaf->ebx = pLeaf->uEbx;
+                pLegacyLeaf->ecx = pLeaf->uEcx;
+                pLegacyLeaf->edx = pLeaf->uEdx;
+            }
+            else
+                *pLegacyLeaf = pCPUM->GuestInfo.DefCpuId;
+        }
+    }
+
+    pCPUM->GuestCpuIdDef = pCPUM->GuestInfo.DefCpuId;
+
+    return VINF_SUCCESS;
+}
+
+
 /**
  * Initializes the emulated CPU's cpuid information.
@@ -825 +1039 @@
     PCPUM       pCPUM    = &pVM->cpum.s;
     PCFGMNODE   pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
-    uint32_t    i;
     int         rc;
 
-#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
-    if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
+#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
+    if ( pCPUM->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
     { \
-        LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
-        pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
-    }
-#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
-    if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
+        LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
+        (a_pLeafReg) &= ~(uint32_t)(fMask); \
+    }
+#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
+    if ( pCPUM->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
     { \
-        LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
-        pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
+        LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
+        (a_pLeafReg) &= ~(uint32_t)(fBitMask); \
     }
 
@@ -847 +1060 @@
      * Enables the Synthetic CPU.  The Vendor ID and Processor Name are
      * completely overridden by VirtualBox custom strings.  Some
-     * CPUID information is withheld, like the cache info. */
-    rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu",  &pCPUM->fSyntheticCpu, false);
+     * CPUID information is withheld, like the cache info.
+     *
+     * This is obsoleted by PortableCpuIdLevel. */
+    bool fSyntheticCpu;
+    rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu",  &fSyntheticCpu, false);
     AssertRCReturn(rc, rc);
 
@@ -856 +1072 @@
      * values should only be used when older CPUs are involved since it may
      * harm performance and maybe also cause problems with specific guests. */
-    rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
-    AssertRCReturn(rc, rc);
-
-    AssertLogRelReturn(!pCPUM->fSyntheticCpu || !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
-
-    /*
-     * Get the host CPUID leaves and redetect the guest CPU vendor (could've
-     * been overridden).
-     */
-    /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
-     * Overrides the host CPUID leaf values used for calculating the guest CPUID
-     * leaves.  This can be used to preserve the CPUID values when moving a VM to a
-     * different machine.  Another use is restricting (or extending) the feature set
-     * exposed to the guest. */
-    PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
-    rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0],     RT_ELEMENTS(pCPUM->aGuestCpuIdStd),     pHostOverrideCfg);
-    AssertRCReturn(rc, rc);
-    rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0],     RT_ELEMENTS(pCPUM->aGuestCpuIdExt),     pHostOverrideCfg);
-    AssertRCReturn(rc, rc);
-    rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
-    AssertRCReturn(rc, rc);
-
-    pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
-                                                  pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
-
-    /*
-     * Determine the default leaf.
-     *
-     * Intel returns values of the highest standard function, while AMD
-     * returns zeros. VIA on the other hand seems to returning nothing or
-     * perhaps some random garbage, we don't try to duplicate this behavior.
-     */
-    ASMCpuIdExSlow(pCPUM->aGuestCpuIdStd[0].eax + 10, 0, 0, 0, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
-                   &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
-                   &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
+    rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, fSyntheticCpu ? 1 : 0);
+    AssertLogRelRCReturn(rc, rc);
+
+    /** @cfgm{CPUM/GuestCpuName, string}
+     * The name of of the CPU we're to emulate.  The default is the host CPU.
+     * Note! CPUs other than "host" one is currently unsupported. */
+    char szCpuName[128];
+    rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", szCpuName, sizeof(szCpuName), "host");
+    AssertLogRelRCReturn(rc, rc);
 
     /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
@@ -896 +1086 @@
      */
     bool fCmpXchg16b;
-    rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false); AssertRCReturn(rc, rc);
+    rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false);
+    AssertLogRelRCReturn(rc, rc);
 
     /** @cfgm{/CPUM/MONITOR, boolean, true}
@@ -902 +1093 @@
      */
     bool fMonitor;
-    rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &fMonitor, true); AssertRCReturn(rc, rc);
-
-    /* Cpuid 1 & 0x80000001:
+    rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &fMonitor, true);
+    AssertLogRelRCReturn(rc, rc);
+
+    /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
+     * Expose MWAIT extended features to the guest.  For now we expose just MWAIT
+     * break on interrupt feature (bit 1).
+     */
+    bool fMWaitExtensions;
+    rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false);
+    AssertLogRelRCReturn(rc, rc);
+
+    /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
+     * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
+     * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
+     * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
+     */
+    bool fNt4LeafLimit;
+    rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false);
+    AssertLogRelRCReturn(rc, rc);
+
+    /** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
+     * Restrict the reported CPU family+model+stepping of intel CPUs.  This is
+     * probably going to be a temporary hack, so don't depend on this.
+     * The 1st byte of the value is the stepping, the 2nd byte value is the model
+     * number and the 3rd byte value is the family, and the 4th value must be zero.
+     */
+    uint32_t uMaxIntelFamilyModelStep;
+    rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &uMaxIntelFamilyModelStep, UINT32_MAX);
+    AssertLogRelRCReturn(rc, rc);
+
+    /*
+     * Get the guest CPU data from the database and/or the host.
+     */
+    rc = cpumR3DbGetCpuInfo(szCpuName, &pCPUM->GuestInfo);
+    if (RT_FAILURE(rc))
+        return rc == VERR_CPUM_DB_CPU_NOT_FOUND
+             ? VMSetError(pVM, rc, RT_SRC_POS,
+                          "Info on guest CPU '%s' could not be found. Please, select a different CPU.", szCpuName)
+             : rc;
+
+    /** @cfgm{CPUM/MSRs/[Name]/[First|Last|Type|Value|...],}
+     * Overrides the guest MSRs.
+     */
+    rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
+
+    /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
+     * Overrides the CPUID leaf values (from the host CPU usually) used for
+     * calculating the guest CPUID leaves.  This can be used to preserve the CPUID
+     * values when moving a VM to a different machine.  Another use is restricting
+     * (or extending) the feature set exposed to the guest. */
+    if (RT_SUCCESS(rc))
+        rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
+
+    if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
+        rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
+                        "Found unsupported configuration node '/CPUM/CPUID/'. "
+                        "Please use IMachine::setCPUIDLeaf() instead.");
+
+    /*
+     * Pre-exploded the CPUID info.
+     */
+    if (RT_SUCCESS(rc))
+        rc = cpumR3CpuIdExplodeFeatures(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, &pCPUM->GuestFeatures);
+    if (RT_FAILURE(rc))
+    {
+        RTMemFree(pCPUM->GuestInfo.paCpuIdLeavesR3);
+        pCPUM->GuestInfo.paCpuIdLeavesR3 = NULL;
+        RTMemFree(pCPUM->GuestInfo.paMsrRangesR3);
+        pCPUM->GuestInfo.paMsrRangesR3 = NULL;
+        return rc;
+    }
+
+
+    /* ... split this function about here ... */
+
+
+    PCPUMCPUIDLEAF pStdLeaf0 = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 0, 0);
+    AssertLogRelReturn(pStdLeaf0, VERR_CPUM_IPE_2);
+
+
+    /* Cpuid 1:
      * Only report features we can support.
      *
@@ -910 +1179 @@
      *       options may require adjusting (i.e. stripping what was enabled).
      */
-    pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
+    PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 1, 0);
+    AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
+    pStdFeatureLeaf->uEdx        &= X86_CPUID_FEATURE_EDX_FPU
                                   | X86_CPUID_FEATURE_EDX_VME
                                   | X86_CPUID_FEATURE_EDX_DE
@@ -941 +1212 @@
                                   //| X86_CPUID_FEATURE_EDX_PBE   - no pending break enabled.
                                   | 0;
-    pCPUM->aGuestCpuIdStd[1].ecx &= 0
+    pStdFeatureLeaf->uEcx        &= 0
                                   | X86_CPUID_FEATURE_ECX_SSE3
                                   /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
@@ -961 +1232 @@
     if (pCPUM->u8PortableCpuIdLevel > 0)
     {
-        PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
-        PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
-        PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3,  X86_CPUID_FEATURE_ECX_SSE3);
-        PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, CX16,  X86_CPUID_FEATURE_ECX_CX16);
-        PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2,  X86_CPUID_FEATURE_EDX_SSE2);
-        PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE,   X86_CPUID_FEATURE_EDX_SSE);
-        PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
-        PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV,  X86_CPUID_FEATURE_EDX_CMOV);
-
-        Assert(!(pCPUM->aGuestCpuIdStd[1].edx & (  X86_CPUID_FEATURE_EDX_SEP
+        PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
+        PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
+        PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE3,  X86_CPUID_FEATURE_ECX_SSE3);
+        PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, CX16,  X86_CPUID_FEATURE_ECX_CX16);
+        PORTABLE_DISABLE_FEATURE_BIT(2, pStdFeatureLeaf->uEdx, SSE2,  X86_CPUID_FEATURE_EDX_SSE2);
+        PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, SSE,   X86_CPUID_FEATURE_EDX_SSE);
+        PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
+        PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, CMOV,  X86_CPUID_FEATURE_EDX_CMOV);
+
+        Assert(!(pStdFeatureLeaf->uEdx        & (  X86_CPUID_FEATURE_EDX_SEP
                                                  | X86_CPUID_FEATURE_EDX_PSN
                                                  | X86_CPUID_FEATURE_EDX_DS
@@ -978 +1249 @@
                                                  | X86_CPUID_FEATURE_EDX_PBE
                                                  )));
-        Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & (  X86_CPUID_FEATURE_ECX_PCLMUL
+        Assert(!(pStdFeatureLeaf->uEcx        & (  X86_CPUID_FEATURE_ECX_PCLMUL
                                                  | X86_CPUID_FEATURE_ECX_DTES64
                                                  | X86_CPUID_FEATURE_ECX_CPLDS
@@ -1008 +1279 @@
      * ASSUMES that this is ALWAYS the AMD defined feature set if present.
      */
-    pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
+    PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
+                                                        UINT32_C(0x80000001), 0);
+    if (pExtFeatureLeaf)
+    {
+        pExtFeatureLeaf->uEdx    &= X86_CPUID_AMD_FEATURE_EDX_FPU
                                   | X86_CPUID_AMD_FEATURE_EDX_VME
                                   | X86_CPUID_AMD_FEATURE_EDX_DE
@@ -1037 +1312 @@
                                   | X86_CPUID_AMD_FEATURE_EDX_3DNOW
                                   | 0;
-    pCPUM->aGuestCpuIdExt[1].ecx &= 0
+        pExtFeatureLeaf->uEcx    &= 0
                                   //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
                                   //| X86_CPUID_AMD_FEATURE_ECX_CMPL
@@ -1054 +1329 @@
                                   //| X86_CPUID_AMD_FEATURE_ECX_WDT
                                   | 0;
-    if (pCPUM->u8PortableCpuIdLevel > 0)
-    {
-        PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L,       X86_CPUID_AMD_FEATURE_ECX_CR8L);
-        PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW,      X86_CPUID_AMD_FEATURE_EDX_3DNOW);
-        PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX,   X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
-        PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR,      X86_CPUID_AMD_FEATURE_EDX_FFXSR);
-        PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP,     X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
-        PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF,  X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
-        PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV,       X86_CPUID_AMD_FEATURE_EDX_CMOV);
-
-        Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & (  X86_CPUID_AMD_FEATURE_ECX_CMPL
-                                                 | X86_CPUID_AMD_FEATURE_ECX_SVM
-                                                 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
-                                                 | X86_CPUID_AMD_FEATURE_ECX_CR8L
-                                                 | X86_CPUID_AMD_FEATURE_ECX_ABM
-                                                 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
-                                                 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
-                                                 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
-                                                 | X86_CPUID_AMD_FEATURE_ECX_OSVW
-                                                 | X86_CPUID_AMD_FEATURE_ECX_IBS
-                                                 | X86_CPUID_AMD_FEATURE_ECX_SSE5
-                                                 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
-                                                 | X86_CPUID_AMD_FEATURE_ECX_WDT
-                                                 | UINT32_C(0xffffc000)
-                                                 )));
-        Assert(!(pCPUM->aGuestCpuIdExt[1].edx & (  RT_BIT(10)
-                                                 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
-                                                 | RT_BIT(18)
-                                                 | RT_BIT(19)
-                                                 | RT_BIT(21)
-                                                 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
-                                                 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
-                                                 | RT_BIT(28)
-                                                 )));
-    }
-
-    /*
-     * Apply the Synthetic CPU modifications. (TODO: move this up)
-     */
-    if (pCPUM->fSyntheticCpu)
-    {
-        static const char s_szVendor[13]    = "VirtualBox  ";
-        static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000            "; /* includes null terminator */
-
-        pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
-
-        /* Limit the nr of standard leaves; 5 for monitor/mwait */
-        pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
-
-        /* 0: Vendor */
-        pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
-        pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
-        pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
-
-        /* 1.eax: Version information.  family : model : stepping */
-        pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
-
-        /* Leaves 2 - 4 are Intel only - zero them out */
-        memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
-        memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
-        memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
-
-        /* Leaf 5 = monitor/mwait */
-
-        /* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
-        pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
-        /* AMD only - set to zero. */
-        pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
-
-        /* 0x800000001: shared feature bits are set dynamically. */
-        memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
-
-        /* 0x800000002-4: Processor Name String Identifier. */
-        pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
-        pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
-        pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
-        pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
-        pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
-        pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
-        pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
-        pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
-        pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
-        pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
-        pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
-        pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
-
-        /* 0x800000005-7 - reserved -> zero */
-        memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
-        memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
-        memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
-
-        /* 0x800000008: only the max virtual and physical address size. */
-        pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0;  /* reserved */
+        if (pCPUM->u8PortableCpuIdLevel > 0)
+        {
+            PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEcx, CR8L,       X86_CPUID_AMD_FEATURE_ECX_CR8L);
+            PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW,      X86_CPUID_AMD_FEATURE_EDX_3DNOW);
+            PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW_EX,   X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
+            PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, FFXSR,      X86_CPUID_AMD_FEATURE_EDX_FFXSR);
+            PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, RDTSCP,     X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
+            PORTABLE_DISABLE_FEATURE_BIT(2, pExtFeatureLeaf->uEcx, LAHF_SAHF,  X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
+            PORTABLE_DISABLE_FEATURE_BIT(3, pExtFeatureLeaf->uEcx, CMOV,       X86_CPUID_AMD_FEATURE_EDX_CMOV);
+
+            Assert(!(pExtFeatureLeaf->uEcx & (  X86_CPUID_AMD_FEATURE_ECX_CMPL
+                                              | X86_CPUID_AMD_FEATURE_ECX_SVM
+                                              | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
+                                              | X86_CPUID_AMD_FEATURE_ECX_CR8L
+                                              | X86_CPUID_AMD_FEATURE_ECX_ABM
+                                              | X86_CPUID_AMD_FEATURE_ECX_SSE4A
+                                              | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
+                                              | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
+                                              | X86_CPUID_AMD_FEATURE_ECX_OSVW
+                                              | X86_CPUID_AMD_FEATURE_ECX_IBS
+                                              | X86_CPUID_AMD_FEATURE_ECX_SSE5
+                                              | X86_CPUID_AMD_FEATURE_ECX_SKINIT
+                                              | X86_CPUID_AMD_FEATURE_ECX_WDT
+                                              | UINT32_C(0xffffc000)
+                                              )));
+            Assert(!(pExtFeatureLeaf->uEdx & (  RT_BIT(10)
+                                              | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
+                                              | RT_BIT(18)
+                                              | RT_BIT(19)
+                                              | RT_BIT(21)
+                                              | X86_CPUID_AMD_FEATURE_EDX_AXMMX
+                                              | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
+                                              | RT_BIT(28)
+                                              )));
+        }
     }
 
@@ -1153 +1370 @@
      * (APIC-ID := 0 and #LogCpus := 0)
      */
-    pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
+    pStdFeatureLeaf->uEbx &= 0x0000ffff;
 #ifdef VBOX_WITH_MULTI_CORE
-    if (    pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
-        &&  pVM->cCpus > 1)
+    if (pVM->cCpus > 1)
     {
         /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
-        pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
-        pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT;  /* necessary for hyper-threading *or* multi-core CPUs */
+        pStdFeatureLeaf->uEbx |= (pVM->cCpus << 16);
+        pStdFeatureLeaf->uEdx |= X86_CPUID_FEATURE_EDX_HTT;  /* necessary for hyper-threading *or* multi-core CPUs */
     }
 #endif
@@ -1170 +1386 @@
      * Safe to expose; restrict the number of calls to 1 for the portable case.
      */
-    if (    pCPUM->u8PortableCpuIdLevel > 0
-        &&  pCPUM->aGuestCpuIdStd[0].eax >= 2
-        && (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
-    {
-        LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
-        pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
+    PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 2, 0);
+    if (   pCPUM->u8PortableCpuIdLevel > 0
+        && pCurLeaf
+        && (pCurLeaf->uEax & 0xff) > 1)
+    {
+        LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
+        pCurLeaf->uEax &= UINT32_C(0xfffffffe);
     }
 
@@ -1185 +1402 @@
      * Safe to expose
      */
-    if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
-    {
-        pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
+    pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 3, 0);
+    if (   !(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN)
+        && pCurLeaf)
+    {
+        pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
         if (pCPUM->u8PortableCpuIdLevel > 0)
-            pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
+            pCurLeaf->uEax = pCurLeaf->uEbx = 0;
     }
 
@@ -1202 +1421 @@
      * Note: These SMP values are constant regardless of ECX
      */
-    pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
-    pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
+    CPUMCPUIDLEAF NewLeaf;
+    pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 4, 0);
+    if (pCurLeaf)
+    {
+        NewLeaf.uLeaf        = 4;
+        NewLeaf.uSubLeaf     = 0;
+        NewLeaf.fSubLeafMask = 0;
+        NewLeaf.uEax         = 0;
+        NewLeaf.uEbx         = 0;
+        NewLeaf.uEcx         = 0;
+        NewLeaf.uEdx         = 0;
+        NewLeaf.fFlags       = 0;
 #ifdef VBOX_WITH_MULTI_CORE
-    if (   pVM->cCpus > 1
-        && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
-    {
-        AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
-        /* One logical processor with possibly multiple cores. */
-        /* See  http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
-        pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26);   /* 6 bits only -> 64 cores! */
-    }
+        if (   pVM->cCpus > 1
+            && pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
+        {
+            AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
+            /* One logical processor with possibly multiple cores. */
+            /* See  http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
+            NewLeaf.uEax |= ((pVM->cCpus - 1) << 26);   /* 6 bits only -> 64 cores! */
+        }
 #endif
+        rc = cpumR3CpuIdInsert(&pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
+        AssertLogRelRCReturn(rc, rc);
+    }
 
     /* Cpuid 5:     Monitor/mwait Leaf
@@ -1224 +1456 @@
      * Safe to expose
      */
-    if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
-        pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
-
-    pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
-    /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
-     * Expose MWAIT extended features to the guest.  For now we expose
-     * just MWAIT break on interrupt feature (bit 1).
-     */
-    bool fMWaitExtensions;
-    rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
-    if (fMWaitExtensions)
-    {
-        pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
-        /** @todo: for now we just expose host's MWAIT C-states, although conceptually
-           it shall be part of our power management virtualization model */
+    pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 4, 0);
+    if (pCurLeaf)
+    {
+        if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
+            pCurLeaf->uEax = pCurLeaf->uEbx = 0;
+
+        pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
+        if (fMWaitExtensions)
+        {
+            pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
+            /** @todo: for now we just expose host's MWAIT C-states, although conceptually
+               it shall be part of our power management virtualization model */
 #if 0
-        /* MWAIT sub C-states */
-        pCPUM->aGuestCpuIdStd[5].edx =
-                (0 << 0)  /* 0 in C0 */ |
-                (2 << 4)  /* 2 in C1 */ |
-                (2 << 8)  /* 2 in C2 */ |
-                (2 << 12) /* 2 in C3 */ |
-                (0 << 16) /* 0 in C4 */
-                ;
+            /* MWAIT sub C-states */
+            pCurLeaf->uEdx =
+                    (0 << 0)  /* 0 in C0 */ |
+                    (2 << 4)  /* 2 in C1 */ |
+                    (2 << 8)  /* 2 in C2 */ |
+                    (2 << 12) /* 2 in C3 */ |
+                    (0 << 16) /* 0 in C4 */
+                    ;
 #endif
-    }
-    else
-        pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
+        }
+        else
+            pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
+    }
 
     /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
@@ -1270 +1500 @@
      * VIA:               Reserved
      */
-    if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
-    {
-        Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
-
-        pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
-
-        if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
+    pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000007), 0);
+    if (pCurLeaf)
+    {
+        Assert(pCPUM->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
+
+        pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
+
+        if (pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
         {
             /* Only expose the TSC invariant capability bit to the guest. */
-            pCPUM->aGuestCpuIdExt[7].edx    &= 0
+            pCurLeaf->uEdx                  &= 0
                                             //| X86_CPUID_AMD_ADVPOWER_EDX_TS
                                             //| X86_CPUID_AMD_ADVPOWER_EDX_FID
@@ -1300 +1531 @@
         }
         else
-            pCPUM->aGuestCpuIdExt[7].edx    = 0;
+            pCurLeaf->uEdx = 0;
     }
 
@@ -1312 +1543 @@
      *                    EBX, ECX, EDX - reserved
      */
-    if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
+    pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000008), 0);
+    if (pCurLeaf)
     {
         /* Only expose the virtual and physical address sizes to the guest. */
-        pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
-        pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0;  /* reserved */
+        pCurLeaf->uEax &= UINT32_C(0x0000ffff);
+        pCurLeaf->uEbx = pCurLeaf->uEdx = 0;  /* reserved */
         /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
          * NC (0-7) Number of cores; 0 equals 1 core */
-        pCPUM->aGuestCpuIdExt[8].ecx = 0;
+        pCurLeaf->uEcx = 0;
 #ifdef VBOX_WITH_MULTI_CORE
         if (    pVM->cCpus > 1
-            &&  pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
+            &&  pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
         {
             /* Legacy method to determine the number of cores. */
-            pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
-            pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
+            pCurLeaf->uEcx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
+            if (pExtFeatureLeaf)
+                pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
         }
 #endif
     }
 
-    /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
-     * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
-     * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
-     * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
-     */
-    bool fNt4LeafLimit;
-    rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
-    if (fNt4LeafLimit && pCPUM->aGuestCpuIdStd[0].eax > 3)
-        pCPUM->aGuestCpuIdStd[0].eax = 3;
-
-    /*
-     * Limit it the number of entries and fill the remaining with the defaults.
+
+    /*
+     * Limit it the number of entries, zapping the remainder.
      *
      * The limits are masking off stuff about power saving and similar, this
@@ -1348 +1572 @@
      * info too in these leaves (like words about having a constant TSC).
      */
-    if (pCPUM->aGuestCpuIdStd[0].eax > 5)
-        pCPUM->aGuestCpuIdStd[0].eax = 5;
-    for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
-        pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
-
-    if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
-        pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
-    for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
-           ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
-           : 0;
-         i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
-         i++)
-        pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
+    pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 0, 0);
+    if (pCurLeaf)
+    {
+        if (pCurLeaf->uEax > 5)
+        {
+            pCurLeaf->uEax = 5;
+            cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
+                                   UINT32_C(0x00000006), UINT32_C(0x000fffff));
+        }
+
+        /* NT4 hack, no zapping of extra leaves here. */
+        if (fNt4LeafLimit && pCurLeaf->uEax > 3)
+            pCurLeaf->uEax = 3;
+    }
+
+    pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000000), 0);
+    if (pCurLeaf)
+    {
+        if (pCurLeaf->uEax > UINT32_C(0x80000008))
+        {
+            pCurLeaf->uEax = UINT32_C(0x80000008);
+            cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
+                                   UINT32_C(0x80000008), UINT32_C(0x800fffff));
+        }
+    }
 
     /*
@@ -1370 +1606 @@
      * temperature/hz/++ stuff, include it as well (static).
      */
-    if (    pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
-        &&  pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
-    {
-        pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
-        pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
-        for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
-             i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
-             i++)
-            pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
-    }
-    else
-        for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
-            pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
+    pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0xc0000000), 0);
+    if (pCurLeaf)
+    {
+        if (   pCurLeaf->uEax >= UINT32_C(0xc0000000)
+            && pCurLeaf->uEax <= UINT32_C(0xc0000004))
+        {
+            pCurLeaf->uEax = RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000002));
+            cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
+                                   UINT32_C(0xc0000002), UINT32_C(0xc00fffff));
+
+            pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
+                                          UINT32_C(0xc0000001), 0);
+            if (pCurLeaf)
+                pCurLeaf->uEdx = 0; /* all features hidden */
+        }
+        else
+            cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
+                                   UINT32_C(0xc0000000), UINT32_C(0xc00fffff));
+    }
 
     /*
@@ -1391 +1633 @@
      * Currently we do not support any hypervisor-specific interface.
      */
-    pCPUM->aGuestCpuIdHyper[0].eax = UINT32_C(0x40000001);
-    pCPUM->aGuestCpuIdHyper[0].ebx = pCPUM->aGuestCpuIdHyper[0].ecx
-                                   = pCPUM->aGuestCpuIdHyper[0].edx = 0x786f4256;   /* 'VBox' */
-    pCPUM->aGuestCpuIdHyper[1].eax = 0x656e6f6e;                            /* 'none' */
-    pCPUM->aGuestCpuIdHyper[1].ebx = pCPUM->aGuestCpuIdHyper[1].ecx
-                                   = pCPUM->aGuestCpuIdHyper[1].edx = 0;    /* Reserved */
+    NewLeaf.uLeaf        = UINT32_C(0x40000000);
+    NewLeaf.uSubLeaf     = 0;
+    NewLeaf.fSubLeafMask = 0;
+    NewLeaf.uEax         = UINT32_C(0x40000001);
+    NewLeaf.uEbx         = 0x786f4256 /* 'VBox' */;
+    NewLeaf.uEcx         = 0x786f4256 /* 'VBox' */;
+    NewLeaf.uEdx         = 0x786f4256 /* 'VBox' */;
+    NewLeaf.fFlags       = 0;
+    rc = cpumR3CpuIdInsert(&pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
+    AssertLogRelRCReturn(rc, rc);
+
+    NewLeaf.uLeaf        = UINT32_C(0x40000001);
+    NewLeaf.uEax         = 0x656e6f6e;                            /* 'none' */
+    NewLeaf.uEbx         = 0;
+    NewLeaf.uEcx         = 0;
+    NewLeaf.uEdx         = 0;
+    NewLeaf.fFlags       = 0;
+    rc = cpumR3CpuIdInsert(&pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
+    AssertLogRelRCReturn(rc, rc);
 
     /*
      * Mini CPU selection support for making Mac OS X happy.
      */
-    if (pCPUM->enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
-    {
-        /** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
-         * Restrict the reported CPU family+model+stepping of intel CPUs.  This is
-         * probably going to be a temporary hack, so don't depend on this.
-         * The 1st byte of the value is the stepping, the 2nd byte value is the model
-         * number and the 3rd byte value is the family, and the 4th value must be zero.
-         */
-        uint32_t uMaxIntelFamilyModelStep;
-        rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &uMaxIntelFamilyModelStep, UINT32_MAX);
-        AssertRCReturn(rc, rc);
-        uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pCPUM->aGuestCpuIdStd[1].eax),
-                                                                ASMGetCpuModelIntel(pCPUM->aGuestCpuIdStd[1].eax),
-                                                                ASMGetCpuFamily(pCPUM->aGuestCpuIdStd[1].eax),
+    if (pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
+    {
+        uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
+                                                                ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
+                                                                ASMGetCpuFamily(pStdFeatureLeaf->uEax),
                                                                 0);
         if (uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
         {
-            uint32_t uNew = pCPUM->aGuestCpuIdStd[1].eax & UINT32_C(0xf0003000);
+            uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
             uNew |= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
             uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
@@ -1426 +1672 @@
                 uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
             LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
-                    pCPUM->aGuestCpuIdStd[1].eax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
-            pCPUM->aGuestCpuIdStd[1].eax = uNew;
+                    pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
+            pStdFeatureLeaf->uEax = uNew;
         }
     }
 
-    /*
-     * Load CPUID overrides from configuration.
-     * Note: Kind of redundant now, but allows unchanged overrides
-     */
-    /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
-     * Overrides the CPUID leaf values. */
-    PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
-    rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0],     RT_ELEMENTS(pCPUM->aGuestCpuIdStd),     pOverrideCfg);
-    AssertRCReturn(rc, rc);
-    rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0],     RT_ELEMENTS(pCPUM->aGuestCpuIdExt),     pOverrideCfg);
-    AssertRCReturn(rc, rc);
-    rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
-    AssertRCReturn(rc, rc);
-
-    /*
-     * Check if PAE was explicitely enabled by the user.
-     */
+
+    /*
+     * Move the MSR and CPUID arrays over on the hypervisor heap, and explode
+     * guest CPU features again.
+     */
+    void *pvFree = pCPUM->GuestInfo.paCpuIdLeavesR3;
+    int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCPUM, pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves);
+    RTMemFree(pvFree);
+
+    pvFree = pCPUM->GuestInfo.paMsrRangesR3;
+    int rc2 = MMHyperDupMem(pVM, pvFree,
+                            sizeof(pCPUM->GuestInfo.paMsrRangesR3[0]) * pCPUM->GuestInfo.cMsrRanges, 32,
+                            MM_TAG_CPUM_MSRS, (void **)&pCPUM->GuestInfo.paMsrRangesR3);
+    RTMemFree(pvFree);
+    AssertLogRelRCReturn(rc1, rc1);
+    AssertLogRelRCReturn(rc2, rc2);
+
+    pCPUM->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCPUM->GuestInfo.paMsrRangesR3);
+    pCPUM->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCPUM->GuestInfo.paMsrRangesR3);
+    cpumR3MsrRegStats(pVM);
+
+    /*
+     * Some more configuration that we're applying at the end of everything
+     * via the CPUMSetGuestCpuIdFeature API.
+     */
+
+    /* Check if PAE was explicitely enabled by the user. */
     bool fEnable;
     rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);      AssertRCReturn(rc, rc);
@@ -1453 +1709 @@
         CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
 
-    /*
-     * We don't normally enable NX for raw-mode, so give the user a chance to
-     * force it on.
-     */
+    /* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
     rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);                 AssertRCReturn(rc, rc);
     if (fEnable)
         CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
 
-    /*
-     * We don't enable the Hypervisor Present bit by default, but it may
-     * be needed by some guests.
-     */
+    /* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
     rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false);                AssertRCReturn(rc, rc);
     if (fEnable)
@@ -1488 +1738 @@
 {
     LogFlow(("CPUMR3Relocate\n"));
+
+    pVM->cpum.s.GuestInfo.paMsrRangesRC   = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
+    pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
 
     /* Recheck the guest DRx values in raw-mode. */
@@ -1552 +1805 @@
  * Used by CPUMR3Reset and CPU hot plugging.
  *
- * @param   pVCpu               Pointer to the VMCPU.
- */
-VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
+ * @param   pVM         Pointer to the cross context VM structure.
+ * @param   pVCpu       Pointer to the cross context virtual CPU structure of
+ *                      the CPU that is being reset.  This may differ from the
+ *                      current EMT.
+ */
+VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
 {
     /** @todo anything different for VCPU > 0? */
@@ -1635 +1891 @@
                                                         supports all bits, since a zero value here should be read as 0xffbf. */
 
+    /*
+     * MSRs.
+     */
     /* Init PAT MSR */
     pCtx->msrPAT                    = UINT64_C(0x0007040600070406); /** @todo correct? */
@@ -1642 +1901 @@
     Assert(!pCtx->msrEFER);
 
+    /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
+       is supposed to be here, just trying provide useful/sensible values. */
+    PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
+    if (pRange)
+    {
+        pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
+                                               | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
+                                               | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
+                                               | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
+        pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
+                            | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
+        pRange->fWrGpMask  &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
+    }
+
+    /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
+
     /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
      *        called from each EMT while we're getting called by CPUMR3Reset()
      *        iteratively on the same thread. Fix later.  */
-#if 0
+#if 0 /** @todo r=bird: This we will do in TM, not here. */
     /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
     CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
@@ -1673 +1948 @@
     for (VMCPUID i = 0; i < pVM->cCpus; i++)
     {
-        CPUMR3ResetCpu(&pVM->aCpus[i]);
+        CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
 
 #ifdef VBOX_WITH_CRASHDUMP_MAGIC
@@ -1725 +2000 @@
     SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
     SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
+}
+
+
+static int cpumR3LoadCpuIdOneGuestArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
+{
+    uint32_t cCpuIds;
+    int rc = SSMR3GetU32(pSSM, &cCpuIds);
+    if (RT_SUCCESS(rc))
+    {
+        if (cCpuIds < 64)
+        {
+            for (uint32_t i = 0; i < cCpuIds; i++)
+            {
+                CPUMCPUID CpuId;
+                rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
+                if (RT_FAILURE(rc))
+                    break;
+
+                CPUMCPUIDLEAF NewLeaf;
+                NewLeaf.uLeaf           = uBase + i;
+                NewLeaf.uSubLeaf        = 0;
+                NewLeaf.fSubLeafMask    = 0;
+                NewLeaf.uEax            = CpuId.eax;
+                NewLeaf.uEbx            = CpuId.ebx;
+                NewLeaf.uEcx            = CpuId.ecx;
+                NewLeaf.uEdx            = CpuId.edx;
+                NewLeaf.fFlags          = 0;
+                rc = cpumR3CpuIdInsert(ppaLeaves, pcLeaves, &NewLeaf);
+            }
+        }
+        else
+            rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
+    }
+    if (RT_FAILURE(rc))
+    {
+        RTMemFree(*ppaLeaves);
+        *ppaLeaves = NULL;
+        *pcLeaves = 0;
+    }
+    return rc;
+}
+
+
+static int cpumR3LoadCpuIdGuestArrays(PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
+{
+    *ppaLeaves = NULL;
+    *pcLeaves = 0;
+
+    int rc = cpumR3LoadCpuIdOneGuestArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
+    if (RT_SUCCESS(rc))
+        rc = cpumR3LoadCpuIdOneGuestArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
+    if (RT_SUCCESS(rc))
+        rc = cpumR3LoadCpuIdOneGuestArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
+
+    return rc;
 }
 
@@ -1809 +2139 @@
             && !(aHostRaw##set [1].reg & bit) \
             && !(aHostOverride##set [1].reg & bit) \
-            && !(aGuestOverride##set [1].reg & bit) \
            ) \
         { \
@@ -1823 +2152 @@
             && !(aHostRaw##set [1].reg & bit) \
             && !(aHostOverride##set [1].reg & bit) \
-            && !(aGuestOverride##set [1].reg & bit) \
            ) \
             LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
@@ -1832 +2160 @@
             && !(aHostRaw##set [1].reg & bit) \
             && !(aHostOverride##set [1].reg & bit) \
-            && !(aGuestOverride##set [1].reg & bit) \
            ) \
             LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
@@ -1845 +2172 @@
             && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
             && !(aHostOverride##set [1].reg & bit) \
-            && !(aGuestOverride##set [1].reg & bit) \
            ) \
         { \
@@ -1860 +2186 @@
             && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
             && !(aHostOverride##set [1].reg & bit) \
-            && !(aGuestOverride##set [1].reg & bit) \
            ) \
             LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
@@ -1870 +2195 @@
             && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
             && !(aHostOverride##set [1].reg & bit) \
-            && !(aGuestOverride##set [1].reg & bit) \
            ) \
             LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
@@ -1885 +2209 @@
                  : aHostRawStd[1].reg      & (StdBit)) \
             && !(aHostOverrideExt[1].reg   & (ExtBit)) \
-            && !(aGuestOverrideExt[1].reg  & (ExtBit)) \
            ) \
         { \
@@ -1901 +2224 @@
                  : aHostRawStd[1].reg      & (StdBit)) \
             && !(aHostOverrideExt[1].reg   & (ExtBit)) \
-            && !(aGuestOverrideExt[1].reg  & (ExtBit)) \
            ) \
             LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
@@ -1912 +2234 @@
                  : aHostRawStd[1].reg      & (StdBit)) \
             && !(aHostOverrideExt[1].reg   & (ExtBit)) \
-            && !(aGuestOverrideExt[1].reg  & (ExtBit)) \
            ) \
             LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
@@ -1921 +2242 @@
      * Load them into stack buffers first.
      */
-    CPUMCPUID   aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
-    uint32_t    cGuestCpuIdStd;
-    int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
-    if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
-        return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
-    SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
-
-    CPUMCPUID   aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
-    uint32_t    cGuestCpuIdExt;
-    rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
-    if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
-        return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
-    SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
-
-    CPUMCPUID   aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
-    uint32_t    cGuestCpuIdCentaur;
-    rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
-    if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
-        return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
-    SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
+    PCPUMCPUIDLEAF paLeaves;
+    uint32_t       cLeaves;
+    int rc = cpumR3LoadCpuIdGuestArrays(pSSM, uVersion, &paLeaves, &cLeaves);
+    AssertRCReturn(rc, rc);
+
+    /** @todo we'll be leaking paLeaves on error return... */
 
     CPUMCPUID   GuestCpuIdDef;
@@ -1951 +2258 @@
     if (cRawStd > RT_ELEMENTS(aRawStd))
         return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
-    SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
+    rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
+    AssertRCReturn(rc, rc);
+    for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
+        ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
 
     CPUMCPUID   aRawExt[32];
@@ -1960 +2270 @@
     rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
     AssertRCReturn(rc, rc);
-
-    /*
-     * Note that we support restoring less than the current amount of standard
-     * leaves because we've been allowed more is newer version of VBox.
-     *
-     * So, pad new entries with the default.
-     */
-    for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
-        aGuestCpuIdStd[i] = GuestCpuIdDef;
-
-    for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
-        aGuestCpuIdExt[i] = GuestCpuIdDef;
-
-    for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
-        aGuestCpuIdCentaur[i] = GuestCpuIdDef;
-
-    for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
-        ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
-
     for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
         ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
@@ -1999 +2290 @@
      * Note! We currently only need the feature leaves, so skip rest.
      */
-    PCFGMNODE   pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
-    CPUMCPUID   aGuestOverrideStd[2];
-    memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
-    cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
-
-    CPUMCPUID   aGuestOverrideExt[2];
-    memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
-    cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
-
-    pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
+    PCFGMNODE   pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
     CPUMCPUID   aHostOverrideStd[2];
     memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
@@ -2259 +2541 @@
      *      "EMU?" - Can this be emulated?
      */
+    CPUMCPUID aGuestCpuIdStd[2];
+    RT_ZERO(aGuestCpuIdStd);
+    cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
+
     /* CPUID(1).ecx */
     CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);    // -> EMU
@@ -2328 +2614 @@
 
     /* CPUID(0x80000000). */
-    if (    aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
-        &&  aGuestCpuIdExt[0].eax <  UINT32_C(0x8000007f))
+    CPUMCPUID aGuestCpuIdExt[2];
+    RT_ZERO(aGuestCpuIdExt);
+    if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
     {
         /** @todo deal with no 0x80000001 on the host. */
@@ -2407 +2694 @@
      * We're good, commit the CPU ID leaves.
      */
-    memcpy(&pVM->cpum.s.aGuestCpuIdStd[0],     &aGuestCpuIdStd[0],     sizeof(aGuestCpuIdStd));
-    memcpy(&pVM->cpum.s.aGuestCpuIdExt[0],     &aGuestCpuIdExt[0],     sizeof(aGuestCpuIdExt));
-    memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
-    pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
+    MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
+    pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
+    pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
+    pVM->cpum.s.GuestInfo.DefCpuId = GuestCpuIdDef;
+    rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
+    RTMemFree(paLeaves);
+    AssertLogRelRCReturn(rc, rc);
+
 
 #undef CPUID_CHECK_RET

trunk/src/VBox/VMM/VMMR3/EM.cpp

@@ -2398 +2398 @@
                         PGMR3ResetCpu(pVM, pVCpu);
                         TRPMR3ResetCpu(pVCpu);
-                        CPUMR3ResetCpu(pVCpu);
+                        CPUMR3ResetCpu(pVM, pVCpu);
                         EMR3ResetCpu(pVCpu);
                         HMR3ResetCpu(pVCpu);

trunk/src/VBox/VMM/VMMR3/PGM.cpp

@@ -2168 +2168 @@
     }
 
+    /** @todo query from CPUM. */
     pVM->pgm.s.GCPhysInvAddrMask = 0;
     for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)

trunk/src/VBox/VMM/VMMR3/VM.cpp

@@ -4380 +4380 @@
     PDMR3ResetCpu(pVCpu);
     TRPMR3ResetCpu(pVCpu);
-    CPUMR3ResetCpu(pVCpu);
+    CPUMR3ResetCpu(pVM, pVCpu);
     EMR3ResetCpu(pVCpu);
     HMR3ResetCpu(pVCpu);

trunk/src/VBox/VMM/VMMR3/VMM.cpp

@@ -1420 +1420 @@
 
     PGMR3ResetCpu(pVM, pVCpu);
-    CPUMR3ResetCpu(pVCpu);
+    CPUMR3ResetCpu(pVM, pVCpu);
 
     return VINF_EM_WAIT_SIPI;

trunk/src/VBox/VMM/VMMR3/VMMTests.cpp

@@ -872 +872 @@
      * Do the experiments.
      */
-    uint32_t uMsr   = 0xc0011011;
-    uint64_t uValue = 0x10000;
+    uint32_t uMsr   = 0x00000277;
+    uint64_t uValue = UINT64_C(0x0007010600070106);
 #if 0
+    uValue &= ~(RT_BIT_64(17) | RT_BIT_64(16) | RT_BIT_64(15) | RT_BIT_64(14) | RT_BIT_64(13));
+    uValue |= RT_BIT_64(13);
     rc = VMMR3CallRC(pVM, RCPtrEP, 6, pVM->pVMRC, uMsr, RT_LODWORD(uValue), RT_HIDWORD(uValue),
                      RCPtrValues, RCPtrValues + sizeof(uint64_t));
     RTPrintf("uMsr=%#010x before=%#018llx written=%#018llx after=%#018llx rc=%Rrc\n",
              uMsr, pauValues[0], uValue, pauValues[1], rc);
-#endif
+#elif 1
+    const uint64_t uOrgValue = uValue;
+    uint32_t       cChanges = 0;
+    for (int iBit = 63; iBit >= 58; iBit--)
+    {
+        uValue = uOrgValue & ~RT_BIT_64(iBit);
+        rc = VMMR3CallRC(pVM, RCPtrEP, 6, pVM->pVMRC, uMsr, RT_LODWORD(uValue), RT_HIDWORD(uValue),
+                         RCPtrValues, RCPtrValues + sizeof(uint64_t));
+        RTPrintf("uMsr=%#010x before=%#018llx written=%#018llx after=%#018llx rc=%Rrc\nclear bit=%u -> %s\n",
+                 uMsr, pauValues[0], uValue, pauValues[1], rc, iBit,
+                 (pauValues[0] ^  pauValues[1]) & RT_BIT_64(iBit) ?  "changed" : "unchanged");
+        cChanges += RT_BOOL(pauValues[0] ^ pauValues[1]);
+
+        uValue = uOrgValue | RT_BIT_64(iBit);
+        rc = VMMR3CallRC(pVM, RCPtrEP, 6, pVM->pVMRC, uMsr, RT_LODWORD(uValue), RT_HIDWORD(uValue),
+                         RCPtrValues, RCPtrValues + sizeof(uint64_t));
+        RTPrintf("uMsr=%#010x before=%#018llx written=%#018llx after=%#018llx rc=%Rrc\nset   bit=%u -> %s\n",
+                 uMsr, pauValues[0], uValue, pauValues[1], rc, iBit,
+                 (pauValues[0] ^  pauValues[1]) & RT_BIT_64(iBit) ?  "changed" : "unchanged");
+        cChanges += RT_BOOL(pauValues[0] ^ pauValues[1]);
+    }
+    RTPrintf("%u change(s)\n", cChanges);
+#else
+    uint64_t fWriteable = 0;
     for (uint32_t i = 0; i <= 63; i++)
     {
         uValue = RT_BIT_64(i);
+# if 0
+        if (uValue & (0x7))
+            continue;
+# endif
         rc = VMMR3CallRC(pVM, RCPtrEP, 6, pVM->pVMRC, uMsr, RT_LODWORD(uValue), RT_HIDWORD(uValue),
                          RCPtrValues, RCPtrValues + sizeof(uint64_t));
         RTPrintf("uMsr=%#010x before=%#018llx written=%#018llx after=%#018llx rc=%Rrc\n",
                  uMsr, pauValues[0], uValue, pauValues[1], rc);
+        if (RT_SUCCESS(rc))
+            fWriteable |= RT_BIT_64(i);
     }
 
@@ -900 +931 @@
     RTPrintf("uMsr=%#010x before=%#018llx written=%#018llx after=%#018llx rc=%Rrc\n",
              uMsr, pauValues[0], uValue, pauValues[1], rc);
+
+    uValue = fWriteable;
+    rc = VMMR3CallRC(pVM, RCPtrEP, 6, pVM->pVMRC, uMsr, RT_LODWORD(uValue), RT_HIDWORD(uValue),
+                     RCPtrValues, RCPtrValues + sizeof(uint64_t));
+    RTPrintf("uMsr=%#010x before=%#018llx written=%#018llx after=%#018llx rc=%Rrc [fWriteable]\n",
+             uMsr, pauValues[0], uValue, pauValues[1], rc);
+
+#endif
 
     /*

trunk/src/VBox/VMM/VMMRC/VMMRC.cpp

@@ -5 +5 @@
 
 /*
- * Copyright (C) 2006-2012 Oracle Corporation
+ * Copyright (C) 2006-2013 Oracle Corporation
  *
  * This file is part of VirtualBox Open Source Edition (OSE), as
@@ -49 +49 @@
 static DECLCALLBACK(int) vmmGCTestTmpPFHandlerCorruptFS(PVM pVM, PCPUMCTXCORE pRegFrame);
 DECLASM(bool)   vmmRCSafeMsrRead(uint32_t uMsr, uint64_t *pu64Value);
+DECLASM(bool)   vmmRCSafeMsrWrite(uint32_t uMsr, uint64_t u64Value);
 
 
@@ -378 +379 @@
 
 
+/**
+ * Tries to write the given value to an MSR, returns the effect and restors the
+ * original value.
+ *
+ * This is called directly via VMMR3CallRC.
+ *
+ * @returns VBox status code.
+ * @param   pVM             The VM handle.
+ * @param   uMsr            The MSR to start at.
+ * @param   u32ValueLow     The low part of the value to write.
+ * @param   u32ValueHi      The high part of the value to write.
+ * @param   puValueBefore   The value before writing.
+ * @param   puValueAfter    The value read back after writing.
+ */
+extern "C" VMMRCDECL(int)
+VMMRCTestTestWriteMsr(PVM pVM, uint32_t uMsr, uint32_t u32ValueLow, uint32_t u32ValueHi,
+                      uint64_t *puValueBefore, uint64_t *puValueAfter)
+{
+    AssertPtrReturn(puValueBefore, VERR_INVALID_POINTER);
+    AssertPtrReturn(puValueAfter, VERR_INVALID_POINTER);
+    ASMIntDisable();
+
+    int      rc           = VINF_SUCCESS;
+    uint64_t uValueBefore = UINT64_MAX;
+    uint64_t uValueAfter  = UINT64_MAX;
+    if (vmmRCSafeMsrRead(uMsr, &uValueBefore))
+    {
+        if (!vmmRCSafeMsrWrite(uMsr, RT_MAKE_U64(u32ValueLow, u32ValueHi)))
+            rc = VERR_WRITE_PROTECT;
+        if (!vmmRCSafeMsrRead(uMsr, &uValueAfter) && RT_SUCCESS(rc))
+            rc = VERR_READ_ERROR;
+        vmmRCSafeMsrWrite(uMsr, uValueBefore);
+    }
+    else
+        rc = VERR_ACCESS_DENIED;
+
+    *puValueBefore = uValueBefore;
+    *puValueAfter  = uValueAfter;
+    return rc;
+}
+
+
 
 /**

trunk/src/VBox/VMM/VMMRC/VMMRCA.asm

@@ -235 +235 @@
     pushf
     cli
+    push    esi
+    push    edi
+    push    ebx
+    push    ebp
 
     mov     ecx, [ebp + 8]              ; The MSR to read.
@@ -247 +251 @@
     mov     [ecx + 4], edx
 
+    mov     eax, 1
+.return:
+    pop     ebp
+    pop     ebx
+    pop     edi
+    pop     esi
     popf
-    mov     eax, 1
     leave
     ret
 
 .trapped:
-    popf
     mov     eax, 0
-    leave
-    ret
+    jmp     .return
 ENDPROC vmmRCSafeMsrRead
 
@@ -271 +278 @@
     pushf
     cli
+    push    esi
+    push    edi
+    push    ebx
+    push    ebp
 
     mov     ecx, [ebp + 8]              ; The MSR to write to.
@@ -279 +290 @@
     wrmsr
 
+    mov     eax, 1
+.return:
+    pop     ebp
+    pop     ebx
+    pop     edi
+    pop     esi
     popf
-    mov     eax, 1
     leave
     ret
 
 .trapped:
-    popf
     mov     eax, 0
-    leave
-    ret
+    jmp     .return
 ENDPROC vmmRCSafeMsrWrite
 

trunk/src/VBox/VMM/include/CPUMInternal.h

@@ -22 +22 @@
 # include <VBox/cdefs.h>
 # include <VBox/types.h>
+# include <VBox/vmm/stam.h>
 # include <iprt/x86.h>
 #else
@@ -108 +109 @@
 #endif
 #endif
+
+
+/**
+ * MSR read functions.
+ */
+typedef enum CPUMMSRRDFN
+{
+    /** Invalid zero value. */
+    kCpumMsrRdFn_Invalid = 0,
+    /** Return the CPUMMSRRANGE::uInitOrReadValue. */
+    kCpumMsrRdFn_FixedValue,
+    /** Alias to the MSR range starting at the MSR given by
+     * CPUMMSRRANGE::uInitOrReadValue.  Must be used in pair with
+     * kCpumMsrWrFn_MsrAlias. */
+    kCpumMsrRdFn_MsrAlias,
+    /** Write only register, GP all read attempts. */
+    kCpumMsrRdFn_WriteOnly,
+
+    kCpumMsrRdFn_Ia32P5McAddr,
+    kCpumMsrRdFn_Ia32P5McType,
+    kCpumMsrRdFn_Ia32TimestampCounter,
+    kCpumMsrRdFn_Ia32ApicBase,
+    kCpumMsrRdFn_Ia32FeatureControl,
+    kCpumMsrRdFn_Ia32SmmMonitorCtl,
+    kCpumMsrRdFn_Ia32PmcN,
+    kCpumMsrRdFn_Ia32MonitorFilterLineSize,
+    kCpumMsrRdFn_Ia32MPerf,
+    kCpumMsrRdFn_Ia32APerf,
+    kCpumMsrRdFn_Ia32MtrrCap,               /**< Takes real CPU value for reference.  */
+    kCpumMsrRdFn_Ia32MtrrPhysBaseN,         /**< Takes register number. */
+    kCpumMsrRdFn_Ia32MtrrPhysMaskN,         /**< Takes register number. */
+    kCpumMsrRdFn_Ia32MtrrFixed,             /**< Takes CPUMCPU offset. */
+    kCpumMsrRdFn_Ia32MtrrDefType,
+    kCpumMsrRdFn_Ia32Pat,
+    kCpumMsrRdFn_Ia32SysEnterCs,
+    kCpumMsrRdFn_Ia32SysEnterEsp,
+    kCpumMsrRdFn_Ia32SysEnterEip,
+    kCpumMsrRdFn_Ia32McgCap,
+    kCpumMsrRdFn_Ia32McgStatus,
+    kCpumMsrRdFn_Ia32McgCtl,
+    kCpumMsrRdFn_Ia32DebugCtl,
+    kCpumMsrRdFn_Ia32SmrrPhysBase,
+    kCpumMsrRdFn_Ia32SmrrPhysMask,
+    kCpumMsrRdFn_Ia32PlatformDcaCap,
+    kCpumMsrRdFn_Ia32CpuDcaCap,
+    kCpumMsrRdFn_Ia32Dca0Cap,
+    kCpumMsrRdFn_Ia32PerfEvtSelN,           /**< Range value indicates the register number. */
+    kCpumMsrRdFn_Ia32PerfStatus,            /**< Range value returned. */
+    kCpumMsrRdFn_Ia32PerfCtl,               /**< Range value returned. */
+    kCpumMsrRdFn_Ia32FixedCtrN,             /**< Takes register number of start of range. */
+    kCpumMsrRdFn_Ia32PerfCapabilities,      /**< Takes reference value. */
+    kCpumMsrRdFn_Ia32FixedCtrCtrl,
+    kCpumMsrRdFn_Ia32PerfGlobalStatus,      /**< Takes reference value. */
+    kCpumMsrRdFn_Ia32PerfGlobalCtrl,
+    kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
+    kCpumMsrRdFn_Ia32PebsEnable,
+    kCpumMsrRdFn_Ia32ClockModulation,       /**< Range value returned. */
+    kCpumMsrRdFn_Ia32ThermInterrupt,        /**< Range value returned. */
+    kCpumMsrRdFn_Ia32ThermStatus,           /**< Range value returned. */
+    kCpumMsrRdFn_Ia32Therm2Ctl,             /**< Range value returned. */
+    kCpumMsrRdFn_Ia32MiscEnable,            /**< Range value returned. */
+    kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN,  /**< Takes bank number. */
+    kCpumMsrRdFn_Ia32McNCtl2,               /**< Takes register number of start of range. */
+    kCpumMsrRdFn_Ia32DsArea,
+    kCpumMsrRdFn_Ia32TscDeadline,
+    kCpumMsrRdFn_Ia32X2ApicN,
+    kCpumMsrRdFn_Ia32VmxBase,               /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxPinbasedCtls,       /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxProcbasedCtls,      /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxExitCtls,           /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxEntryCtls,          /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxMisc,               /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxCr0Fixed0,          /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxCr0Fixed1,          /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxCr4Fixed0,          /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxCr4Fixed1,          /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxVmcsEnum,           /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxProcBasedCtls2,     /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxEptVpidCap,         /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxTruePinbasedCtls,   /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls,  /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxTrueExitCtls,       /**< Takes real value as reference. */
+    kCpumMsrRdFn_Ia32VmxTrueEntryCtls,      /**< Takes real value as reference. */
+
+    kCpumMsrRdFn_Amd64Efer,
+    kCpumMsrRdFn_Amd64SyscallTarget,
+    kCpumMsrRdFn_Amd64LongSyscallTarget,
+    kCpumMsrRdFn_Amd64CompSyscallTarget,
+    kCpumMsrRdFn_Amd64SyscallFlagMask,
+    kCpumMsrRdFn_Amd64FsBase,
+    kCpumMsrRdFn_Amd64GsBase,
+    kCpumMsrRdFn_Amd64KernelGsBase,
+    kCpumMsrRdFn_Amd64TscAux,
+
+    kCpumMsrRdFn_IntelEblCrPowerOn,
+    kCpumMsrRdFn_IntelPlatformInfo100MHz,
+    kCpumMsrRdFn_IntelPlatformInfo133MHz,
+    kCpumMsrRdFn_IntelPkgCStConfigControl,
+    kCpumMsrRdFn_IntelPmgIoCaptureBase,
+    kCpumMsrRdFn_IntelLastBranchFromToN,
+    kCpumMsrRdFn_IntelLastBranchFromN,
+    kCpumMsrRdFn_IntelLastBranchToN,
+    kCpumMsrRdFn_IntelLastBranchTos,
+    kCpumMsrRdFn_IntelBblCrCtl,
+    kCpumMsrRdFn_IntelBblCrCtl3,
+    kCpumMsrRdFn_IntelI7TemperatureTarget,  /**< Range value returned. */
+    kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/**< Takes register number. */
+    kCpumMsrRdFn_IntelI7MiscPwrMgmt,
+    kCpumMsrRdFn_IntelP6CrN,
+    kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
+    kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
+    kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
+    kCpumMsrRdFn_IntelI7SandyAesNiCtl,
+    kCpumMsrRdFn_IntelI7TurboRatioLimit,    /**< Returns range value. */
+    kCpumMsrRdFn_IntelI7LbrSelect,
+    kCpumMsrRdFn_IntelI7SandyErrorControl,
+    kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/**< Returns range value. */
+    kCpumMsrRdFn_IntelI7PowerCtl,
+    kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
+    kCpumMsrRdFn_IntelI7PebsLdLat,
+    kCpumMsrRdFn_IntelI7PkgCnResidencyN,     /**< Takes C-state number. */
+    kCpumMsrRdFn_IntelI7CoreCnResidencyN,    /**< Takes C-state number. */
+    kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7SandyVrMiscConfig,   /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7SandyRaplPowerUnit,  /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN,     /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplPkgPowerLimit,   /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplPkgPerfStatus,   /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplPkgPowerInfo,    /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplDramPowerLimit,  /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplDramPerfStatus,  /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplDramPowerInfo,   /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplPp0PowerLimit,   /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplPp0Policy,       /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplPp0PerfStatus,   /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplPp1PowerLimit,   /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */
+    kCpumMsrRdFn_IntelI7RaplPp1Policy,       /**< Takes real value as reference. */
+
+    kCpumMsrRdFn_P6LastBranchFromIp,
+    kCpumMsrRdFn_P6LastBranchToIp,
+    kCpumMsrRdFn_P6LastIntFromIp,
+    kCpumMsrRdFn_P6LastIntToIp,
+
+    kCpumMsrRdFn_AmdFam15hTscRate,
+    kCpumMsrRdFn_AmdFam15hLwpCfg,
+    kCpumMsrRdFn_AmdFam15hLwpCbAddr,
+    kCpumMsrRdFn_AmdFam10hMc4MiscN,
+    kCpumMsrRdFn_AmdK8PerfCtlN,
+    kCpumMsrRdFn_AmdK8PerfCtrN,
+    kCpumMsrRdFn_AmdK8SysCfg,               /**< Range value returned. */
+    kCpumMsrRdFn_AmdK8HwCr,
+    kCpumMsrRdFn_AmdK8IorrBaseN,
+    kCpumMsrRdFn_AmdK8IorrMaskN,
+    kCpumMsrRdFn_AmdK8TopOfMemN,
+    kCpumMsrRdFn_AmdK8NbCfg1,
+    kCpumMsrRdFn_AmdK8McXcptRedir,
+    kCpumMsrRdFn_AmdK8CpuNameN,
+    kCpumMsrRdFn_AmdK8HwThermalCtrl,        /**< Range value returned. */
+    kCpumMsrRdFn_AmdK8SwThermalCtrl,
+    kCpumMsrRdFn_AmdK8McCtlMaskN,
+    kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
+    kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
+    kCpumMsrRdFn_AmdK8IntPendingMessage,
+    kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
+    kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
+    kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
+    kCpumMsrRdFn_AmdFam10hPStateCurLimit,   /**< Returns range value. */
+    kCpumMsrRdFn_AmdFam10hPStateControl,    /**< Returns range value. */
+    kCpumMsrRdFn_AmdFam10hPStateStatus,     /**< Returns range value. */
+    kCpumMsrRdFn_AmdFam10hPStateN,          /**< Returns range value. This isn't an register index! */
+    kCpumMsrRdFn_AmdFam10hCofVidControl,    /**< Returns range value. */
+    kCpumMsrRdFn_AmdFam10hCofVidStatus,     /**< Returns range value. */
+    kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
+    kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
+    kCpumMsrRdFn_AmdK8SmmBase,
+    kCpumMsrRdFn_AmdK8SmmAddr,
+    kCpumMsrRdFn_AmdK8SmmMask,
+    kCpumMsrRdFn_AmdK8VmCr,
+    kCpumMsrRdFn_AmdK8IgnNe,
+    kCpumMsrRdFn_AmdK8SmmCtl,
+    kCpumMsrRdFn_AmdK8VmHSavePa,
+    kCpumMsrRdFn_AmdFam10hVmLockKey,
+    kCpumMsrRdFn_AmdFam10hSmmLockKey,
+    kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
+    kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
+    kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
+    kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
+    kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
+    kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
+    kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
+    kCpumMsrRdFn_AmdK7MicrocodeCtl,         /**< Returns range value. */
+    kCpumMsrRdFn_AmdK7ClusterIdMaybe,       /**< Returns range value. */
+    kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
+    kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
+    kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
+    kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
+    kCpumMsrRdFn_AmdK7DebugStatusMaybe,
+    kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
+    kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
+    kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
+    kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
+    kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
+    kCpumMsrRdFn_AmdK7NodeId,
+    kCpumMsrRdFn_AmdK7DrXAddrMaskN,      /**< Takes register index. */
+    kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
+    kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
+    kCpumMsrRdFn_AmdK7LoadStoreCfg,
+    kCpumMsrRdFn_AmdK7InstrCacheCfg,
+    kCpumMsrRdFn_AmdK7DataCacheCfg,
+    kCpumMsrRdFn_AmdK7BusUnitCfg,
+    kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
+    kCpumMsrRdFn_AmdFam15hFpuCfg,
+    kCpumMsrRdFn_AmdFam15hDecoderCfg,
+    kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
+    kCpumMsrRdFn_AmdFam15hCombUnitCfg,
+    kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
+    kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
+    kCpumMsrRdFn_AmdFam15hExecUnitCfg,
+    kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
+    kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
+    kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
+    kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
+    kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
+    kCpumMsrRdFn_AmdFam10hIbsOpRip,
+    kCpumMsrRdFn_AmdFam10hIbsOpData,
+    kCpumMsrRdFn_AmdFam10hIbsOpData2,
+    kCpumMsrRdFn_AmdFam10hIbsOpData3,
+    kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
+    kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
+    kCpumMsrRdFn_AmdFam10hIbsCtl,
+    kCpumMsrRdFn_AmdFam14hIbsBrTarget,
+
+    /** End of valid MSR read function indexes. */
+    kCpumMsrRdFn_End
+} CPUMMSRRDFN;
+
+/**
+ * MSR write functions.
+ */
+typedef enum CPUMMSRWRFN
+{
+    /** Invalid zero value. */
+    kCpumMsrWrFn_Invalid = 0,
+    /** Writes are ignored, the fWrGpMask is observed though. */
+    kCpumMsrWrFn_IgnoreWrite,
+    /** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
+    kCpumMsrWrFn_ReadOnly,
+    /** Alias to the MSR range starting at the MSR given by
+     * CPUMMSRRANGE::uInitOrReadValue.  Must be used in pair with
+     * kCpumMsrRdFn_MsrAlias. */
+    kCpumMsrWrFn_MsrAlias,
+
+    kCpumMsrWrFn_Ia32P5McAddr,
+    kCpumMsrWrFn_Ia32P5McType,
+    kCpumMsrWrFn_Ia32TimestampCounter,
+    kCpumMsrWrFn_Ia32ApicBase,
+    kCpumMsrWrFn_Ia32FeatureControl,
+    kCpumMsrWrFn_Ia32BiosUpdateTrigger,
+    kCpumMsrWrFn_Ia32SmmMonitorCtl,
+    kCpumMsrWrFn_Ia32PmcN,
+    kCpumMsrWrFn_Ia32MonitorFilterLineSize,
+    kCpumMsrWrFn_Ia32MPerf,
+    kCpumMsrWrFn_Ia32APerf,
+    kCpumMsrWrFn_Ia32MtrrPhysBaseN,         /**< Takes register number. */
+    kCpumMsrWrFn_Ia32MtrrPhysMaskN,         /**< Takes register number. */
+    kCpumMsrWrFn_Ia32MtrrFixed,             /**< Takes CPUMCPU offset. */
+    kCpumMsrWrFn_Ia32MtrrDefType,
+    kCpumMsrWrFn_Ia32Pat,
+    kCpumMsrWrFn_Ia32SysEnterCs,
+    kCpumMsrWrFn_Ia32SysEnterEsp,
+    kCpumMsrWrFn_Ia32SysEnterEip,
+    kCpumMsrWrFn_Ia32McgStatus,
+    kCpumMsrWrFn_Ia32McgCtl,
+    kCpumMsrWrFn_Ia32DebugCtl,
+    kCpumMsrWrFn_Ia32SmrrPhysBase,
+    kCpumMsrWrFn_Ia32SmrrPhysMask,
+    kCpumMsrWrFn_Ia32PlatformDcaCap,
+    kCpumMsrWrFn_Ia32Dca0Cap,
+    kCpumMsrWrFn_Ia32PerfEvtSelN,           /**< Range value indicates the register number. */
+    kCpumMsrWrFn_Ia32PerfCtl,
+    kCpumMsrWrFn_Ia32FixedCtrN,             /**< Takes register number of start of range. */
+    kCpumMsrWrFn_Ia32PerfCapabilities,
+    kCpumMsrWrFn_Ia32FixedCtrCtrl,
+    kCpumMsrWrFn_Ia32PerfGlobalStatus,
+    kCpumMsrWrFn_Ia32PerfGlobalCtrl,
+    kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
+    kCpumMsrWrFn_Ia32PebsEnable,
+    kCpumMsrWrFn_Ia32ClockModulation,
+    kCpumMsrWrFn_Ia32ThermInterrupt,
+    kCpumMsrWrFn_Ia32ThermStatus,
+    kCpumMsrWrFn_Ia32Therm2Ctl,
+    kCpumMsrWrFn_Ia32MiscEnable,
+    kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN,  /**< Takes bank number. */
+    kCpumMsrWrFn_Ia32McNCtl2,               /**< Takes register number of start of range. */
+    kCpumMsrWrFn_Ia32DsArea,
+    kCpumMsrWrFn_Ia32TscDeadline,
+    kCpumMsrWrFn_Ia32X2ApicN,
+
+    kCpumMsrWrFn_Amd64Efer,
+    kCpumMsrWrFn_Amd64SyscallTarget,
+    kCpumMsrWrFn_Amd64LongSyscallTarget,
+    kCpumMsrWrFn_Amd64CompSyscallTarget,
+    kCpumMsrWrFn_Amd64SyscallFlagMask,
+    kCpumMsrWrFn_Amd64FsBase,
+    kCpumMsrWrFn_Amd64GsBase,
+    kCpumMsrWrFn_Amd64KernelGsBase,
+    kCpumMsrWrFn_Amd64TscAux,
+    kCpumMsrWrFn_IntelEblCrPowerOn,
+    kCpumMsrWrFn_IntelPkgCStConfigControl,
+    kCpumMsrWrFn_IntelPmgIoCaptureBase,
+    kCpumMsrWrFn_IntelLastBranchFromToN,
+    kCpumMsrWrFn_IntelLastBranchFromN,
+    kCpumMsrWrFn_IntelLastBranchToN,
+    kCpumMsrWrFn_IntelLastBranchTos,
+    kCpumMsrWrFn_IntelBblCrCtl,
+    kCpumMsrWrFn_IntelBblCrCtl3,
+    kCpumMsrWrFn_IntelI7TemperatureTarget,
+    kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /**< Takes register number. */
+    kCpumMsrWrFn_IntelI7MiscPwrMgmt,
+    kCpumMsrWrFn_IntelP6CrN,
+    kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
+    kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
+    kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
+    kCpumMsrWrFn_IntelI7SandyAesNiCtl,
+    kCpumMsrWrFn_IntelI7TurboRatioLimit,
+    kCpumMsrWrFn_IntelI7LbrSelect,
+    kCpumMsrWrFn_IntelI7SandyErrorControl,
+    kCpumMsrWrFn_IntelI7PowerCtl,
+    kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
+    kCpumMsrWrFn_IntelI7PebsLdLat,
+    kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
+    kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
+    kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
+    kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
+    kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
+    kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
+    kCpumMsrWrFn_IntelI7RaplPp0Policy,
+    kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
+    kCpumMsrWrFn_IntelI7RaplPp1Policy,
+
+    kCpumMsrWrFn_P6LastIntFromIp,
+    kCpumMsrWrFn_P6LastIntToIp,
+
+    kCpumMsrWrFn_AmdFam15hTscRate,
+    kCpumMsrWrFn_AmdFam15hLwpCfg,
+    kCpumMsrWrFn_AmdFam15hLwpCbAddr,
+    kCpumMsrWrFn_AmdFam10hMc4MiscN,
+    kCpumMsrWrFn_AmdK8PerfCtlN,
+    kCpumMsrWrFn_AmdK8PerfCtrN,
+    kCpumMsrWrFn_AmdK8SysCfg,
+    kCpumMsrWrFn_AmdK8HwCr,
+    kCpumMsrWrFn_AmdK8IorrBaseN,
+    kCpumMsrWrFn_AmdK8IorrMaskN,
+    kCpumMsrWrFn_AmdK8TopOfMemN,
+    kCpumMsrWrFn_AmdK8NbCfg1,
+    kCpumMsrWrFn_AmdK8McXcptRedir,
+    kCpumMsrWrFn_AmdK8CpuNameN,
+    kCpumMsrWrFn_AmdK8HwThermalCtrl,
+    kCpumMsrWrFn_AmdK8SwThermalCtrl,
+    kCpumMsrWrFn_AmdK8McCtlMaskN,
+    kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
+    kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
+    kCpumMsrWrFn_AmdK8IntPendingMessage,
+    kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
+    kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
+    kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
+    kCpumMsrWrFn_AmdFam10hPStateControl,
+    kCpumMsrWrFn_AmdFam10hPStateStatus,
+    kCpumMsrWrFn_AmdFam10hPStateN,
+    kCpumMsrWrFn_AmdFam10hCofVidControl,
+    kCpumMsrWrFn_AmdFam10hCofVidStatus,
+    kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
+    kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
+    kCpumMsrWrFn_AmdK8SmmBase,
+    kCpumMsrWrFn_AmdK8SmmAddr,
+    kCpumMsrWrFn_AmdK8SmmMask,
+    kCpumMsrWrFn_AmdK8VmCr,
+    kCpumMsrWrFn_AmdK8IgnNe,
+    kCpumMsrWrFn_AmdK8SmmCtl,
+    kCpumMsrWrFn_AmdK8VmHSavePa,
+    kCpumMsrWrFn_AmdFam10hVmLockKey,
+    kCpumMsrWrFn_AmdFam10hSmmLockKey,
+    kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
+    kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
+    kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
+    kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
+    kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
+    kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
+    kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
+    kCpumMsrWrFn_AmdK7MicrocodeCtl,
+    kCpumMsrWrFn_AmdK7ClusterIdMaybe,
+    kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
+    kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
+    kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
+    kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
+    kCpumMsrWrFn_AmdK7DebugStatusMaybe,
+    kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
+    kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
+    kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
+    kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
+    kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
+    kCpumMsrWrFn_AmdK7NodeId,
+    kCpumMsrWrFn_AmdK7DrXAddrMaskN,      /**< Takes register index. */
+    kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
+    kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
+    kCpumMsrWrFn_AmdK7LoadStoreCfg,
+    kCpumMsrWrFn_AmdK7InstrCacheCfg,
+    kCpumMsrWrFn_AmdK7DataCacheCfg,
+    kCpumMsrWrFn_AmdK7BusUnitCfg,
+    kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
+    kCpumMsrWrFn_AmdFam15hFpuCfg,
+    kCpumMsrWrFn_AmdFam15hDecoderCfg,
+    kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
+    kCpumMsrWrFn_AmdFam15hCombUnitCfg,
+    kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
+    kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
+    kCpumMsrWrFn_AmdFam15hExecUnitCfg,
+    kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
+    kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
+    kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
+    kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
+    kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
+    kCpumMsrWrFn_AmdFam10hIbsOpRip,
+    kCpumMsrWrFn_AmdFam10hIbsOpData,
+    kCpumMsrWrFn_AmdFam10hIbsOpData2,
+    kCpumMsrWrFn_AmdFam10hIbsOpData3,
+    kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
+    kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
+    kCpumMsrWrFn_AmdFam10hIbsCtl,
+    kCpumMsrWrFn_AmdFam14hIbsBrTarget,
+
+    /** End of valid MSR write function indexes. */
+    kCpumMsrWrFn_End
+} CPUMMSRWRFN;
+
+/**
+ * MSR range.
+ */
+typedef struct CPUMMSRRANGE
+{
+    /** The first MSR. [0] */
+    uint32_t    uFirst;
+    /** The last MSR. [4] */
+    uint32_t    uLast;
+    /** The read function (CPUMMSRRDFN). [8] */
+    uint16_t    enmRdFn;
+    /** The write function (CPUMMSRWRFN). [10] */
+    uint16_t    enmWrFn;
+    /** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
+     * UINT16_MAX if not used by the read and write functions.  [12] */
+    uint16_t    offCpumCpu;
+    /** Reserved for future hacks. [14] */
+    uint16_t    fReserved;
+    /** The init/read value. [16]
+     * When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
+     * offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
+     * offset into CPUM. */
+    uint64_t    uInitOrReadValue;
+    /** The bits to ignore when writing. [24]   */
+    uint64_t    fWrIgnMask;
+    /** The bits that will cause a GP(0) when writing. [32]
+     * This is always checked prior to calling the write function.  Using
+     * UINT64_MAX effectively marks the MSR as read-only. */
+    uint64_t    fWrGpMask;
+    /** The register name, if applicable. [40] */
+    char        szName[56];
+
+#ifdef VBOX_WITH_STATISTICS
+    /** The number of reads. */
+    STAMCOUNTER cReads;
+    /** The number of writes. */
+    STAMCOUNTER cWrites;
+    /** The number of times ignored bits were written. */
+    STAMCOUNTER cIgnoredBits;
+    /** The number of GPs generated. */
+    STAMCOUNTER cGps;
+#endif
+} CPUMMSRRANGE;
+#ifdef VBOX_WITH_STATISTICS
+AssertCompileSize(CPUMMSRRANGE, 128);
+#else
+AssertCompileSize(CPUMMSRRANGE, 96);
+#endif
+/** Pointer to an MSR range. */
+typedef CPUMMSRRANGE *PCPUMMSRRANGE;
+/** Pointer to a const MSR range. */
+typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
+
+
+
+
+/**
+ * CPU features and quirks.
+ * This is mostly exploded CPUID info.
+ */
+typedef struct CPUMFEATURES
+{
+    /** The CPU vendor (CPUMCPUVENDOR). */
+    uint8_t         enmCpuVendor;
+    /** The CPU family. */
+    uint8_t         uFamily;
+    /** The CPU model. */
+    uint8_t         uModel;
+    /** The CPU stepping. */
+    uint8_t         uStepping;
+    /** The microarchitecture. */
+    CPUMMICROARCH   enmMicroarch;
+    /** The maximum physical address with of the CPU. */
+    uint8_t         cMaxPhysAddrWidth;
+    /** Alignment padding.  */
+    uint8_t         abPadding[3];
+
+    /** Supports MSRs.  */
+    uint32_t        fMsr : 1;
+    /** Supports the page size extension (4/2 MB pages). */
+    uint32_t        fPse : 1;
+    /** Supports 36-bit page size extension (4 MB pages can map memory above
+     *  4GB). */
+    uint32_t        fPse36 : 1;
+    /** Supports physical address extension (PAE).  */
+    uint32_t        fPae : 1;
+    /** Page attribute table (PAT) support (page level cache control). */
+    uint32_t        fPat : 1;
+    /** Supports the FXSAVE and FXRSTOR instructions. */
+    uint32_t        fFxSaveRstor : 1;
+    /** Intel SYSENTER/SYSEXIT support */
+    uint32_t        fSysEnter : 1;
+    /** First generation APIC. */
+    uint32_t        fApic : 1;
+    /** Second generation APIC. */
+    uint32_t        fX2Apic : 1;
+    /** Hypervisor present. */
+    uint32_t        fHypervisorPresent : 1;
+    /** MWAIT & MONITOR instructions supported. */
+    uint32_t        fMonitorMWait : 1;
+
+    /** AMD64: Supports long mode.  */
+    uint32_t        fLongMode : 1;
+    /** AMD64: SYSCALL/SYSRET support. */
+    uint32_t        fSysCall : 1;
+    /** AMD64: No-execute page table bit. */
+    uint32_t        fNoExecute : 1;
+    /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
+    uint32_t        fLahfSahf : 1;
+    /** AMD64: Supports RDTSCP. */
+    uint32_t        fRdTscP : 1;
+
+    /** Indicates that FPU instruction and data pointers may leak.
+     * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
+     * is only saved and restored if an exception is pending.   */
+    uint32_t        fLeakyFxSR : 1;
+
+    /** Alignment padding.  */
+    uint32_t        fPadding : 9;
+
+    uint64_t        auPadding[2];
+} CPUMFEATURES;
+AssertCompileSize(CPUMFEATURES, 32);
+/** Pointer to a CPU feature structure. */
+typedef CPUMFEATURES *PCPUMFEATURES;
+/** Pointer to a const CPU feature structure. */
+typedef CPUMFEATURES const *PCCPUMFEATURES;
+
+
+/**
+ * CPU info
+ */
+typedef struct CPUMINFO
+{
+    /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
+    uint32_t                    cMsrRanges;
+    /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
+     * instruction.  Older hardware has been observed to ignore higher bits. */
+    uint32_t                    fMsrMask;
+
+    /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
+    uint32_t                    cCpuIdLeaves;
+    /** The index of the first extended CPUID leaf in the array.
+     *  Set to cCpuIdLeaves if none present. */
+    uint32_t                    iFirstExtCpuIdLeaf;
+    /** How to handle unknown CPUID leaves. */
+    CPUMUKNOWNCPUID             enmUnknownCpuIdMethod;
+    /** For use with CPUMUKNOWNCPUID_DEFAULTS. */
+    CPUMCPUID                   DefCpuId;
+
+    /** Alignment padding.  */
+    uint32_t                    uPadding;
+
+    /** Pointer to the MSR ranges (ring-0 pointer). */
+    R0PTRTYPE(PCPUMMSRRANGE)    paMsrRangesR0;
+    /** Pointer to the CPUID leaves (ring-0 pointer). */
+    R0PTRTYPE(PCPUMCPUIDLEAF)   paCpuIdLeavesR0;
+
+    /** Pointer to the MSR ranges (ring-3 pointer). */
+    R3PTRTYPE(PCPUMMSRRANGE)    paMsrRangesR3;
+    /** Pointer to the CPUID leaves (ring-3 pointer). */
+    R3PTRTYPE(PCPUMCPUIDLEAF)   paCpuIdLeavesR3;
+
+    /** Pointer to the MSR ranges (raw-mode context pointer). */
+    RCPTRTYPE(PCPUMMSRRANGE)    paMsrRangesRC;
+    /** Pointer to the CPUID leaves (raw-mode context pointer). */
+    RCPTRTYPE(PCPUMCPUIDLEAF)   paCpuIdLeavesRC;
+} CPUMINFO;
+/** Pointer to a CPU info structure. */
+typedef CPUMINFO *PCPUMINFO;
+/** Pointer to a const CPU info structure. */
+typedef CPUMINFO const *CPCPUMINFO;
 
 
@@ -310 +923 @@
     } CPUFeaturesExt;
 
-    /** Host CPU manufacturer. */
-    CPUMCPUVENDOR           enmHostCpuVendor;
-    /** Guest CPU manufacturer. */
-    CPUMCPUVENDOR           enmGuestCpuVendor;
-
     /** CR4 mask */
     struct
@@ -322 +930 @@
     } CR4;
 
-    /** Synthetic CPU type? */
-    bool                    fSyntheticCpu;
     /** The (more) portable CPUID level.  */
     uint8_t                 u8PortableCpuIdLevel;
@@ -329 +935 @@
      * This is used to verify load order dependencies (PGM). */
     bool                    fPendingRestore;
-    uint8_t                 abPadding[HC_ARCH_BITS == 64 ? 5 : 1];
+    uint8_t                 abPadding[HC_ARCH_BITS == 64 ? 6 : 2];
 
     /** The standard set of CpuId leaves. */
@@ -345 +951 @@
     uint8_t                 abPadding2[4];
 #endif
+
+    /** Guest CPU info. */
+    CPUMINFO                GuestInfo;
+    /** Guest CPU feature information. */
+    CPUMFEATURES            GuestFeatures;
+    /** Host CPU feature information. */
+    CPUMFEATURES            HostFeatures;
+
+    /** @name MSR statistics.
+     * @{ */
+    STAMCOUNTER             cMsrWrites;
+    STAMCOUNTER             cMsrWritesToIgnoredBits;
+    STAMCOUNTER             cMsrWritesRaiseGp;
+    STAMCOUNTER             cMsrWritesUnknown;
+    STAMCOUNTER             cMsrReads;
+    STAMCOUNTER             cMsrReadsRaiseGp;
+    STAMCOUNTER             cMsrReadsUnknown;
+    /** @} */
 } CPUM;
 /** Pointer to the CPUM instance data residing in the shared VM structure. */
@@ -430 +1054 @@
 RT_C_DECLS_BEGIN
 
+PCPUMCPUIDLEAF      cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf);
+
 #ifdef IN_RING3
 int                 cpumR3DbgInit(PVM pVM);
+PCPUMCPUIDLEAF      cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
+bool                cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
+                                             PCPUMCPUID pLeagcy);
+int                 cpumR3CpuIdInsert(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves, PCPUMCPUIDLEAF pNewLeaf);
+void                cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast);
+int                 cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
+int                 cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
+int                 cpumR3MsrRangesInsert(PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
+int                 cpumR3MsrStrictInitChecks(void);
+int                 cpumR3MsrRegStats(PVM pVM);
+PCPUMMSRRANGE       cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
 #endif
 

trunk/src/VBox/VMM/include/CPUMInternal.mac

@@ -67 +67 @@
     .CPUFeaturesExt.ecx   resd    1
 
-    .enmHostCpuVendor     resd    1
-    .enmGuestCpuVendor    resd    1
-
     ; CR4 masks
     .CR4.AndMask          resd    1
     .CR4.OrMask           resd    1
     ; entered rawmode?
-    .fSyntheticCpu        resb    1
     .u8PortableCpuIdLevel resb    1
     .fPendingRestore      resb    1
 %if RTHCPTR_CB == 8
-    .abPadding            resb    5
+    .abPadding            resb    6
 %else
-    .abPadding            resb    1
+    .abPadding            resb    2
 %endif
 
@@ -93 +89 @@
     .abPadding2           resb    4
 %endif
+
+    .GuestInfo            resb    RTHCPTR_CB*4 + RTRCPTR_CB*2 + 4*10
+    .GuestFeatures        resb    32
+    .HostFeatures         resb    32
+
+    .cMsrWrites                 resq  1
+    .cMsrWritesToIgnoredBits    resq  1
+    .cMsrWritesRaiseGp          resq  1
+    .cMsrWritesUnknown          resq  1
+    .cMsrReads                  resq  1
+    .cMsrReadsRaiseGp           resq  1
+    .cMsrReadsUnknown           resq  1
 endstruc
 

trunk/src/VBox/VMM/testcase/tstVMStruct.h

@@ -32 +32 @@
     GEN_CHECK_OFF(CPUM, CPUFeaturesExt);
     GEN_CHECK_OFF(CPUM, CPUFeaturesExt);
-    GEN_CHECK_OFF(CPUM, enmHostCpuVendor);
-    GEN_CHECK_OFF(CPUM, enmGuestCpuVendor);
     GEN_CHECK_OFF(CPUM, CR4);
 #ifndef VBOX_FOR_DTRACE_LIB
-    GEN_CHECK_OFF(CPUM, fSyntheticCpu);
     GEN_CHECK_OFF(CPUM, u8PortableCpuIdLevel);
     GEN_CHECK_OFF(CPUM, fPendingRestore);

trunk/src/VBox/VMM/tools/Makefile.kmk

@@ -51 +51 @@
 
 
+#
+# CPU report program (CPUM DB).
+#
+PROGRAMS += VBoxCpuReport
+VBoxCpuReport_TEMPLATE := VBoxR3Static
+VBoxCpuReport_DEFS      = IN_VMM_R3
+VBoxCpuReport_INCS      = ../include
+VBoxCpuReport_SOURCES   = \
+        VBoxCpuReport.cpp \
+       ../VMMR3/CPUMR3CpuId.cpp
+VBoxCpuReport_LIBS      = \
+        $(PATH_STAGE_LIB)/SUPR3Static$(VBOX_SUFF_LIB) \
+       $(VBOX_LIB_RUNTIME_STATIC)
+VBoxCpuReport_LDFLAGS.darwin = \
+        -framework IOKit -framework CoreFoundation -framework CoreServices
+
+
 include $(FILE_KBUILD_SUB_FOOTER)