Changeset 66327 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Mar 29, 2017 10:12:02 AM (8 years ago)
- svn:sync-xref-src-repo-rev:
- 114260
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
r66323 r66327 1544 1544 break; 1545 1545 1546 case BS3CG1ENC_MODRM_MbRO: 1547 if (iEncoding == 0) 1548 { 1549 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)) - 1; 1550 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 1551 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT, 1552 1, 0, BS3CG1OPLOC_MEM); 1553 } 1554 else 1555 break; 1556 pThis->cbCurInstr = off; 1557 iEncoding++; 1558 break; 1559 1560 1546 1561 case BS3CG1ENC_FIXED: 1547 1562 if (iEncoding == 0) … … 1805 1820 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX; 1806 1821 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM; 1822 break; 1823 1824 case BS3CG1ENC_MODRM_MbRO: 1825 pThis->iRmOp = 0; 1826 pThis->aOperands[0].cbOp = 1; 1827 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM; 1807 1828 break; 1808 1829 … … 1914 1935 case BS3CG1CPU_GE_80486: 1915 1936 case BS3CG1CPU_GE_Pentium: 1937 case BS3CG1CPU_CLFSH: 1916 1938 return false; 1917 1939 … … 2020 2042 { 2021 2043 ASMCpuIdExSlow(7, 0, 0/*leaf*/, 0, &fEax, &fEbx, &fEcx, &fEdx); 2022 2023 2044 switch (pThis->enmCpuTest) 2024 2045 { … … 2031 2052 } 2032 2053 return false; 2054 2055 case BS3CG1CPU_CLFSH: 2056 if (g_uBs3CpuDetected & BS3CPU_F_CPUID) 2057 { 2058 ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, NULL, &fEdx); 2059 if (fEdx & X86_CPUID_FEATURE_EDX_CLFSH) 2060 return true; 2061 } 2062 return false; 2063 2033 2064 2034 2065 default: -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h
r66323 r66327 69 69 70 70 BS3CG1OP_Ma, 71 BS3CG1OP_MbRO, 71 72 BS3CG1OP_Mq, 72 73 … … 101 102 BS3CG1ENC_MODRM_Vq_Mq, 102 103 BS3CG1ENC_MODRM_Vdq_Wdq, 104 BS3CG1ENC_MODRM_MbRO, 103 105 104 106 BS3CG1ENC_FIXED, … … 150 152 BS3CG1CPU_AVX, 151 153 BS3CG1CPU_AVX2, 154 BS3CG1CPU_CLFSH, 155 152 156 BS3CG1CPU_END 153 157 } BS3CG1CPU;
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