Changeset 66334 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Mar 29, 2017 2:26:23 PM (8 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

114268

Message:

IEM: Fixed UD1 / grp 10 decoding (intel eats modr/m after it).

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAllInstructionsPython.py (modified) (3 diffs)
• IEMAllInstructionsTwoByte0f.cpp.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py

@@ -448 +448 @@
         'byte':     [ 256, ], ##< next opcode byte selects the instruction (default).
         '/r':       [   8, ], ##< modrm.reg selects the instruction.
+        'memreg /r':[  16, ], ##< modrm.reg and (modrm.mod == 3) selects the instruction.
         'mod /r':   [  32, ], ##< modrm.reg and modrm.mod selects the instruction.
         '!11 /r':   [   8, ], ##< modrm.reg selects the instruction with modrm.mod != 0y11.
@@ -494 +495 @@
         if self.sSelector == 'mod /r':
             return (bOpcode >> 3) & 0x1f;
+
+        if self.sSelector == 'memreg /r':
+            return ((bOpcode >> 3) & 0x7) | (int((bOpcode >> 6) == 3) << 3);
 
         if self.sSelector == '!11 /r':
@@ -1207 +1211 @@
     'grp13':        InstructionMap('grp13',     asLeadOpcodes = ['0x0f', '0x72',], sSelector = 'mod /r'),
     'grp14':        InstructionMap('grp14',     asLeadOpcodes = ['0x0f', '0x73',], sSelector = 'mod /r'),
-    'grp15':        InstructionMap('grp15',     asLeadOpcodes = ['0x0f', '0xae',], sSelector = 'mod /r'),
+    'grp15':        InstructionMap('grp15',     asLeadOpcodes = ['0x0f', '0xae',], sSelector = 'memreg /r'),
     'grp16':        InstructionMap('grp16',     asLeadOpcodes = ['0x0f', '0x18',], sSelector = 'mod /r'),
     'grpA17':       InstructionMap('grpA17',    asLeadOpcodes = ['0x0f', '0x78',], sSelector = '/r'), # AMD: EXTRQ weirdness

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h

@@ -6555 +6555 @@
 
 
-/** Opcode 0x0f 0xb9. */
+/**
+ * @opcode      0xb9
+ * @opinvalid   intel-modrm
+ * @optest      op1=1 op2=2 ->
+ * @oponlytest
+ */
 FNIEMOP_DEF(iemOp_Grp10)
 {
-    Log(("iemOp_Grp10 -> #UD\n"));
-    return IEMOP_RAISE_INVALID_OPCODE();
+    /*
+     * AMD does not decode beyond the 0xb9 whereas intel does the modr/m bit
+     * too. See bs3-cpu-decoder-1.c32.  So, we can forward to iemOp_InvalidNeedRM.
+     */
+    /** @todo fix bs3-cpu-generated-1 to deal with this on AMD! */
+    Log(("iemOp_Grp10 aka UD1 -> #UD\n"));
+    IEMOP_MNEMONIC2EX(ud1, "ud1", RM, UD1, ud1, Gb, Eb, DISOPTYPE_INVALID, IEMOPHINT_IGNORES_OP_SIZE); /* just picked Gb,Eb here. */
+    return FNIEMOP_CALL(iemOp_InvalidNeedRM);
 }