VirtualBox

Changeset 66886 in vbox


Ignore:
Timestamp:
May 15, 2017 9:20:40 AM (8 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
115398
Message:

IEM: Implemented vmovups Vps,Wps (VEX.0f 10)

Location:
trunk
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/disopcode.h

    r66815 r66886  
    744744    OP_VLDMXCSR,
    745745    OP_VSTMXCSR,
     746    OP_VMOVUPS,
    746747/** @} */
    747748/** @name VT-x instructions

  • trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

    r66811 r66886  
    68766876
    68776877/**
    6878  * Hook for preparing to use the host FPU for SSE
     6878 * Hook for preparing to use the host FPU for SSE.
    68796879 *
    68806880 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
    … …  
    68836883 */
    68846884DECLINLINE(void) iemFpuPrepareUsageSse(PVMCPU pVCpu)
     6885{
     6886    iemFpuPrepareUsage(pVCpu);
     6887}
     6888
     6889
     6890/**
     6891 * Hook for preparing to use the host FPU for AVX.
     6892 *
     6893 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
     6894 *
     6895 * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
     6896 */
     6897DECLINLINE(void) iemFpuPrepareUsageAvx(PVMCPU pVCpu)
    68856898{
    68866899    iemFpuPrepareUsage(pVCpu);
    … …  
    69516964{
    69526965#if defined(IN_RING3) || defined(VBOX_WITH_KERNEL_USING_XMM)
     6966    CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
     6967#else
     6968    CPUMRZFpuStateActualizeForChange(pVCpu);
     6969#endif
     6970}
     6971
     6972
     6973/**
     6974 * Hook for actualizing the guest YMM0..15 and MXCSR register state for read
     6975 * only.
     6976 *
     6977 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
     6978 *
     6979 * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
     6980 */
     6981DECLINLINE(void) iemFpuActualizeAvxStateForRead(PVMCPU pVCpu)
     6982{
     6983#ifdef IN_RING3
     6984    NOREF(pVCpu);
     6985#else
     6986    CPUMRZFpuStateActualizeAvxForRead(pVCpu);
     6987#endif
     6988}
     6989
     6990
     6991/**
     6992 * Hook for actualizing the guest YMM0..15 and MXCSR register state for
     6993 * read+write.
     6994 *
     6995 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
     6996 *
     6997 * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
     6998 */
     6999DECLINLINE(void) iemFpuActualizeAvxStateForChange(PVMCPU pVCpu)
     7000{
     7001#ifdef IN_RING3
    69537002    CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
    69547003#else
    … …  
    96589707
    96599708
     9709/**
     9710 * Fetches a data oword (octo word), generally AVX related.
     9711 *
     9712 * @returns Strict VBox status code.
     9713 * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
     9714 * @param   pu256Dst            Where to return the qword.
     9715 * @param   iSegReg             The index of the segment register to use for
     9716 *                              this access.  The base and limits are checked.
     9717 * @param   GCPtrMem            The address of the guest memory.
     9718 */
     9719IEM_STATIC VBOXSTRICTRC iemMemFetchDataU256(PVMCPU pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
     9720{
     9721    /* The lazy approach for now... */
     9722    PCRTUINT256U pu256Src;
     9723    VBOXSTRICTRC rc = iemMemMap(pVCpu, (void **)&pu256Src, sizeof(*pu256Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
     9724    if (rc == VINF_SUCCESS)
     9725    {
     9726        pu256Dst->au64[0] = pu256Src->au64[0];
     9727        pu256Dst->au64[1] = pu256Src->au64[1];
     9728        pu256Dst->au64[2] = pu256Src->au64[2];
     9729        pu256Dst->au64[3] = pu256Src->au64[3];
     9730        rc = iemMemCommitAndUnmap(pVCpu, (void *)pu256Src, IEM_ACCESS_DATA_R);
     9731    }
     9732    return rc;
     9733}
     9734
     9735
     9736#ifdef IEM_WITH_SETJMP
     9737/**
     9738 * Fetches a data oword (octo word), generally AVX related.
     9739 *
     9740 * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
     9741 * @param   pu256Dst            Where to return the qword.
     9742 * @param   iSegReg             The index of the segment register to use for
     9743 *                              this access.  The base and limits are checked.
     9744 * @param   GCPtrMem            The address of the guest memory.
     9745 */
     9746IEM_STATIC void iemMemFetchDataU256Jmp(PVMCPU pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
     9747{
     9748    /* The lazy approach for now... */
     9749    PCRTUINT256U pu256Src = (PCRTUINT256U)iemMemMapJmp(pVCpu, sizeof(*pu256Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
     9750    pu256Dst->au64[0] = pu256Src->au64[0];
     9751    pu256Dst->au64[1] = pu256Src->au64[1];
     9752    pu256Dst->au64[2] = pu256Src->au64[2];
     9753    pu256Dst->au64[3] = pu256Src->au64[3];
     9754    iemMemCommitAndUnmapJmp(pVCpu, (void *)pu256Src, IEM_ACCESS_DATA_R);
     9755}
     9756#endif
     9757
     9758
     9759/**
     9760 * Fetches a data oword (octo word) at an aligned address, generally AVX
     9761 * related.
     9762 *
     9763 * Raises \#GP(0) if not aligned.
     9764 *
     9765 * @returns Strict VBox status code.
     9766 * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
     9767 * @param   pu256Dst            Where to return the qword.
     9768 * @param   iSegReg             The index of the segment register to use for
     9769 *                              this access.  The base and limits are checked.
     9770 * @param   GCPtrMem            The address of the guest memory.
     9771 */
     9772IEM_STATIC VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPU pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
     9773{
     9774    /* The lazy approach for now... */
     9775    /** @todo testcase: Ordering of \#SS(0) vs \#GP() vs \#PF on AVX stuff. */
     9776    if (GCPtrMem & 31)
     9777        return iemRaiseGeneralProtectionFault0(pVCpu);
     9778
     9779    PCRTUINT256U pu256Src;
     9780    VBOXSTRICTRC rc = iemMemMap(pVCpu, (void **)&pu256Src, sizeof(*pu256Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
     9781    if (rc == VINF_SUCCESS)
     9782    {
     9783        pu256Dst->au64[0] = pu256Src->au64[0];
     9784        pu256Dst->au64[1] = pu256Src->au64[1];
     9785        pu256Dst->au64[2] = pu256Src->au64[2];
     9786        pu256Dst->au64[3] = pu256Src->au64[3];
     9787        rc = iemMemCommitAndUnmap(pVCpu, (void *)pu256Src, IEM_ACCESS_DATA_R);
     9788    }
     9789    return rc;
     9790}
     9791
     9792
     9793#ifdef IEM_WITH_SETJMP
     9794/**
     9795 * Fetches a data oword (octo word) at an aligned address, generally AVX
     9796 * related, longjmp on error.
     9797 *
     9798 * Raises \#GP(0) if not aligned.
     9799 *
     9800 * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
     9801 * @param   pu256Dst            Where to return the qword.
     9802 * @param   iSegReg             The index of the segment register to use for
     9803 *                              this access.  The base and limits are checked.
     9804 * @param   GCPtrMem            The address of the guest memory.
     9805 */
     9806DECL_NO_INLINE(IEM_STATIC, void) iemMemFetchDataU256AlignedSseJmp(PVMCPU pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
     9807{
     9808    /* The lazy approach for now... */
     9809    /** @todo testcase: Ordering of \#SS(0) vs \#GP() vs \#PF on AVX stuff. */
     9810    if ((GCPtrMem & 31) == 0)
     9811    {
     9812        PCRTUINT256U pu256Src = (PCRTUINT256U)iemMemMapJmp(pVCpu, sizeof(*pu256Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
     9813        pu256Dst->au64[0] = pu256Src->au64[0];
     9814        pu256Dst->au64[1] = pu256Src->au64[1];
     9815        pu256Dst->au64[2] = pu256Src->au64[2];
     9816        pu256Dst->au64[3] = pu256Src->au64[3];
     9817        iemMemCommitAndUnmapJmp(pVCpu, (void *)pu256Src, IEM_ACCESS_DATA_R);
     9818        return;
     9819    }
     9820
     9821    VBOXSTRICTRC rcStrict = iemRaiseGeneralProtectionFault0(pVCpu);
     9822    longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), VBOXSTRICTRC_VAL(rcStrict));
     9823}
     9824#endif
     9825
     9826
    96609827
    96619828/**
    … …  
    1092511092        if ((pVCpu)->iem.s.CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87.FSW & X86_FSW_ES) \
    1092611093            return iemRaiseMathFault(pVCpu); \
     11094    } while (0)
     11095#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
     11096    do { \
     11097        if (   (IEM_GET_CTX(pVCpu)->aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
     11098            || !(IEM_GET_CTX(pVCpu)->cr4 & X86_CR4_OSXSAVE) \
     11099            || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
     11100            return iemRaiseUndefinedOpcode(pVCpu); \
     11101        if (IEM_GET_CTX(pVCpu)->cr0 & X86_CR0_TS) \
     11102            return iemRaiseDeviceNotAvailable(pVCpu); \
    1092711103    } while (0)
    1092811104#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
    … …  
    1120411380    } while (0)
    1120511381
     11382#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_pXState, a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
     11383#define IEM_MC_STORE_YREG_U128_ZX(a_iYRegDst, a_u128Src) \
     11384    do { PX86XSAVEAREA pXStateTmp = IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState); \
     11385         uintptr_t const iYRegDstTmp = (a_iYRegDst); \
     11386         pXStateTmp->x87.aXMM[iYRegDstTmp].au64[0]       = (a_u128Src).au64[0]; \
     11387         pXStateTmp->x87.aXMM[iYRegDstTmp].au64[1]       = (a_u128Src).au64[1]; \
     11388         pXStateTmp->u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
     11389         pXStateTmp->u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
     11390         IEM_MC_INT_CLEAR_ZMM_256_UP(pXStateTmp, a_iYRegDst); \
     11391    } while (0)
     11392#define IEM_MC_STORE_YREG_U256_ZX(a_iYRegDst, a_u256Src) \
     11393    do { PX86XSAVEAREA pXStateTmp = IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState); \
     11394         uintptr_t const iYRegDstTmp = (a_iYRegDst); \
     11395         pXStateTmp->x87.aXMM[iYRegDstTmp].au64[0]       = (a_u256Src).au64[0]; \
     11396         pXStateTmp->x87.aXMM[iYRegDstTmp].au64[1]       = (a_u256Src).au64[1]; \
     11397         pXStateTmp->u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
     11398         pXStateTmp->u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
     11399         IEM_MC_INT_CLEAR_ZMM_256_UP(pXStateTmp, a_iYRegDst); \
     11400    } while (0)
     11401#define IEM_MC_COPY_YREG_U256_ZX(a_iYRegDst, a_iYRegSrc) \
     11402    do { PX86XSAVEAREA pXStateTmp = IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState); \
     11403         uintptr_t const iYRegDstTmp = (a_iYRegDst); \
     11404         uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
     11405         pXStateTmp->x87.aXMM[iYRegDstTmp].au64[0]       = pXStateTmp->x87.aXMM[iYRegSrcTmp].au64[0]; \
     11406         pXStateTmp->x87.aXMM[iYRegDstTmp].au64[1]       = pXStateTmp->x87.aXMM[iYRegSrcTmp].au64[1]; \
     11407         pXStateTmp->u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pXStateTmp->u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
     11408         pXStateTmp->u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pXStateTmp->u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
     11409         IEM_MC_INT_CLEAR_ZMM_256_UP(pXStateTmp, a_iYRegDst); \
     11410    } while (0)
     11411#define IEM_MC_COPY_YREG_U128_ZX(a_iYRegDst, a_iYRegSrc) \
     11412    do { PX86XSAVEAREA pXStateTmp = IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState); \
     11413         uintptr_t const iYRegDstTmp = (a_iYRegDst); \
     11414         uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
     11415         pXStateTmp->x87.aXMM[iYRegDstTmp].au64[0]       = pXStateTmp->x87.aXMM[iYRegSrcTmp].au64[0]; \
     11416         pXStateTmp->x87.aXMM[iYRegDstTmp].au64[1]       = pXStateTmp->x87.aXMM[iYRegSrcTmp].au64[1]; \
     11417         pXStateTmp->u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
     11418         pXStateTmp->u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
     11419         IEM_MC_INT_CLEAR_ZMM_256_UP(pXStateTmp, a_iYRegDst); \
     11420    } while (0)
     11421
    1120611422#ifndef IEM_WITH_SETJMP
    1120711423# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
    … …  
    1130311519# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
    1130411520    iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
     11521#endif
     11522
     11523#ifndef IEM_WITH_SETJMP
     11524# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
     11525    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
     11526# define IEM_MC_FETCH_MEM_U256_ALIGN_SSE(a_u256Dst, a_iSeg, a_GCPtrMem) \
     11527    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
     11528#else
     11529# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
     11530    iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
     11531# define IEM_MC_FETCH_MEM_U256_ALIGN_SSE(a_u256Dst, a_iSeg, a_GCPtrMem) \
     11532    iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
    1130511533#endif
    1130611534
    … …  
    1181012038/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
    1181112039#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
     12040
     12041/** Prepares for using the AVX state.
     12042 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
     12043 * Ensures the guest AVX state in the CPUMCTX is up to date.
     12044 * @note This will include the AVX512 state too when support for it is added
     12045 *       due to the zero extending feature of VEX instruction. */
     12046#define IEM_MC_PREPARE_AVX_USAGE()              iemFpuPrepareUsageAvx(pVCpu)
     12047/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
     12048#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ()   iemFpuActualizeAvxStateForRead(pVCpu)
     12049/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
     12050#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
    1181212051
    1181312052/**
    … …  
    1220012439    { \
    1220112440        if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))) \
     12441        { /* likely */ } \
     12442        else \
     12443            return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \
     12444    } while (0)
     12445
     12446
     12447/**
     12448 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
     12449 * repnz or size prefixes are present, or if in real or v8086 mode.
     12450 */
     12451#define IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX() \
     12452    do \
     12453    { \
     12454        if (RT_LIKELY(   !(  pVCpu->iem.s.fPrefixes \
     12455                           & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \
     12456                      && !IEM_IS_REAL_OR_V86_MODE(pVCpu) )) \
     12457        { /* likely */ } \
     12458        else \
     12459            return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \
     12460    } while (0)
     12461
     12462
     12463/**
     12464 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
     12465 * repnz or size prefixes are present, or if the VEX.VVVV field doesn't indicate
     12466 * register 0, or if in real or v8086 mode.
     12467 */
     12468#define IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV() \
     12469    do \
     12470    { \
     12471        if (RT_LIKELY(   !(  pVCpu->iem.s.fPrefixes \
     12472                           & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \
     12473                      && !pVCpu->iem.s.uVex3rdReg \
     12474                      && !IEM_IS_REAL_OR_V86_MODE(pVCpu) )) \
    1220212475        { /* likely */ } \
    1220312476        else \

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h

    r66814 r66886  
    43544354            if (bXop2 & 0x80 /* XOP.W */)
    43554355                pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_SIZE_REX_W;
    4356             pVCpu->iem.s.uRexReg    = ~bRm >> (7 - 3);
    4357             pVCpu->iem.s.uRexIndex  = ~bRm >> (6 - 3);
    4358             pVCpu->iem.s.uRexB      = ~bRm >> (5 - 3);
     4356            pVCpu->iem.s.uRexReg    = (~bRm >> (7 - 3)) & 0x8;
     4357            pVCpu->iem.s.uRexIndex  = (~bRm >> (6 - 3)) & 0x8;
     4358            pVCpu->iem.s.uRexB      = (~bRm >> (5 - 3)) & 0x8;
    43594359            pVCpu->iem.s.uVex3rdReg = (~bXop2 >> 3) & 0xf;
    43604360            pVCpu->iem.s.uVexLength = (bXop2 >> 2) & 1;
    … …  
    62226222        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx)
    62236223        {
    6224             /* Note! The real mode, v8086 mode and invalid prefix checks are
    6225                      done once the instruction is fully decoded. */
     6224            /* Note! The real mode, v8086 mode and invalid prefix checks are done once
     6225                     the instruction is fully decoded.  Even when XCR0=3 and CR4.OSXSAVE=0. */
    62266226            uint8_t bVex2;   IEM_OPCODE_GET_NEXT_U8(&bVex2);
    62276227            uint8_t bOpcode; IEM_OPCODE_GET_NEXT_U8(&bOpcode);
    … …  
    62296229            if (bVex2 & 0x80 /* VEX.W */)
    62306230                pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_SIZE_REX_W;
    6231             pVCpu->iem.s.uRexReg    = ~bRm >> (7 - 3);
    6232             pVCpu->iem.s.uRexIndex  = ~bRm >> (6 - 3);
    6233             pVCpu->iem.s.uRexB      = ~bRm >> (5 - 3);
     6231            pVCpu->iem.s.uRexReg    = (~bRm >> (7 - 3)) & 0x8;
     6232            pVCpu->iem.s.uRexIndex  = (~bRm >> (6 - 3)) & 0x8;
     6233            pVCpu->iem.s.uRexB      = (~bRm >> (5 - 3)) & 0x8;
    62346234            pVCpu->iem.s.uVex3rdReg = (~bVex2 >> 3) & 0xf;
    62356235            pVCpu->iem.s.uVexLength = (bVex2 >> 2) & 1;
    … …  
    62946294        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx)
    62956295        {
    6296             /* Note! The real mode, v8086 mode and invalid prefix checks are
    6297                      done once the instruction is fully decoded. */
     6296            /* Note! The real mode, v8086 mode and invalid prefix checks are done once
     6297                     the instruction is fully decoded.  Even when XCR0=3 and CR4.OSXSAVE=0. */
    62986298            uint8_t bOpcode; IEM_OPCODE_GET_NEXT_U8(&bOpcode);
    62996299            pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_VEX;
    6300             pVCpu->iem.s.uRexReg    = ~bRm >> (7 - 3);
     6300            pVCpu->iem.s.uRexReg    = (~bRm >> (7 - 3)) & 0x8;
    63016301            pVCpu->iem.s.uVex3rdReg = (~bRm >> 3) & 0xf;
    63026302            pVCpu->iem.s.uVexLength = (bRm >> 2) & 1;

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h

    r66812 r66886  
    5050
    5151
    52 /** Opcode VEX.0F 0x10 - vmovups Vps, Wps */
    53 FNIEMOP_STUB(iemOp_vmovups_Vps_Wps);
     52/**
     53 * @opcode      0x10
     54 * @oppfx       none
     55 * @opcpuid     avx
     56 * @opgroup     og_avx_simdfp_datamove
     57 * @opxcpttype  4UA
     58 * @optest      op1=1 op2=2 -> op1=2
     59 * @optest      op1=0 op2=-22 -> op1=-22
     60 */
     61FNIEMOP_DEF(iemOp_vmovups_Vps_Wps)
     62{
     63    IEMOP_MNEMONIC2(VEX_RM, VMOVUPS, vmovups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     64    Assert(pVCpu->iem.s.uVexLength <= 1);
     65    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     66    if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
     67    {
     68        /*
     69         * Register, register.
     70         */
     71        IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
     72        IEM_MC_BEGIN(0, 0);
     73        IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
     74        IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
     75        if (pVCpu->iem.s.uVexLength == 0)
     76            IEM_MC_COPY_YREG_U128_ZX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
     77                                     (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
     78        else
     79            IEM_MC_COPY_YREG_U256_ZX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
     80                                     (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
     81        IEM_MC_ADVANCE_RIP();
     82        IEM_MC_END();
     83    }
     84    else if (pVCpu->iem.s.uVexLength == 0)
     85    {
     86        /*
     87         * 128-bit: Memory, register.
     88         */
     89        IEM_MC_BEGIN(0, 2);
     90        IEM_MC_LOCAL(RTUINT128U,                uSrc);
     91        IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     92
     93        IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
     94        IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
     95        IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
     96        IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
     97
     98        IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
     99        IEM_MC_STORE_YREG_U128_ZX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
     100
     101        IEM_MC_ADVANCE_RIP();
     102        IEM_MC_END();
     103    }
     104    else
     105    {
     106        /*
     107         * 256-bit: Memory, register.
     108         */
     109        IEM_MC_BEGIN(0, 2);
     110        IEM_MC_LOCAL(RTUINT256U,                uSrc);
     111        IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     112
     113        IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
     114        IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
     115        IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
     116        IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
     117
     118        IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
     119        IEM_MC_STORE_YREG_U256_ZX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
     120
     121        IEM_MC_ADVANCE_RIP();
     122        IEM_MC_END();
     123    }
     124    return VINF_SUCCESS;
     125
     126}
     127
    54128/** Opcode VEX.66.0F 0x10 - vmovupd Vpd, Wpd */
    55129FNIEMOP_STUB(iemOp_vmovupd_Vpd_Wpd);

  • trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp

    r66810 r66886  
    121121#define IEMOP_HLP_DONE_VEX_DECODING_L_ZERO_NO_VVV()         do { } while (0)
    122122#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX()            do { } while (0)
     123#define IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX()             do { } while (0)
     124#define IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV() do { } while (0)
    123125#define IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES()                                    do { } while (0)
     126
     127
    124128#define IEMOP_HLP_DONE_DECODING()                           do { } while (0)
    125129#define IEMOP_HLP_DONE_VEX_DECODING()                       do { } while (0)
    … …  
    352356#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT()          do {} while (0)
    353357#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT()          do {} while (0)
     358#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT()           do {} while (0)
    354359#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO()              do {} while (0)
    355360#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
    … …  
    517522#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc)       do { (void)fSseWrite; } while (0)
    518523
     524#define IEM_MC_STORE_YREG_U128_ZX(a_iYRegDst, a_u128Value)  do { CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxWrite; } while (0)
     525#define IEM_MC_STORE_YREG_U256_ZX(a_iYRegDst, a_u256Value)  do { CHK_TYPE(RTUINT256U, a_u256Value); (void)fAvxWrite; } while (0)
     526#define IEM_MC_COPY_YREG_U256_ZX(a_iYRegDst, a_iYRegSrc)    do { (void)fAvxWrite; } while (0)
     527#define IEM_MC_COPY_YREG_U128_ZX(a_iYRegDst, a_iYRegSrc)    do { (void)fAvxWrite; } while (0)
     528
    519529#define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem)                do { CHK_GCPTR(a_GCPtrMem); } while (0)
    520530#define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16)            do { CHK_TYPE(uint16_t, a_GCPtrMem16); } while (0)
    … …  
    555565#define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem)            do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Dst);} while (0)
    556566#define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem)  do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Dst);} while (0)
     567#define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem)            do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT256U, a_u256Dst);} while (0)
     568#define IEM_MC_FETCH_MEM_U256_ALIGN_SSE(a_u256Dst, a_iSeg, a_GCPtrMem)  do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT256U, a_u256Dst);} while (0)
    557569
    558570#define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value)              do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint8_t,  a_u8Value); CHK_SEG_IDX(a_iSeg); } while (0)
    … …  
    649661#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW)                                                do { (void)fFpuWrite; } while (0)
    650662#define IEM_MC_PREPARE_FPU_USAGE() \
    651     const int fFpuRead = 1, fFpuWrite = 1, fFpuHost = 1, fSseRead = 1, fSseWrite = 1, fSseHost = 1
     663    const int fFpuRead = 1, fFpuWrite = 1, fFpuHost = 1, fSseRead = 1, fSseWrite = 1, fSseHost = 1, fAvxRead = 1, fAvxWrite = 1, fAvxHost = 1
    652664#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ()   const int fFpuRead = 1, fSseRead = 1
    653665#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() const int fFpuRead = 1, fFpuWrite = 1, fSseRead = 1, fSseWrite = 1
    … …  
    655667#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ()   const int fSseRead = 1
    656668#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() const int fSseRead = 1, fSseWrite = 1
     669#define IEM_MC_PREPARE_AVX_USAGE()              const int fAvxRead = 1, fAvxWrite = 1, fAvxHost = 1
     670#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ()   const int fAvxRead = 1
     671#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() const int fAvxRead = 1, fAvxWrite = 1
    657672
    658673#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c

    r66815 r66886  
    4242*   Defined Constants And Macros                                                                                                 *
    4343*********************************************************************************************************************************/
     44#define BS3CG1_WITH_VEX
     45
    4446#define P_CS        X86_OP_PRF_CS
    4547#define P_SS        X86_OP_PRF_SS
    … …  
    9294    BS3CG1OPLOC_INVALID = 0,
    9395    BS3CG1OPLOC_CTX,
     96    BS3CG1OPLOC_CTX_ZX_VLMAX,
    9497    BS3CG1OPLOC_IMM,
    9598    BS3CG1OPLOC_MEM,
    … …  
    11161119
    11171120
    1118 /**
    1119  * Inserts a 2-byte VEX prefix.
    1120  *
    1121  * @returns New offDst value.
    1122  * @param   pThis       The state.
    1123  * @param   offDst      The current instruction offset.
    1124  * @param   uVexL       The VEX.L value.
    1125  * @param   uVexV       The VEX.V value (caller inverted it already).
    1126  * @param   uVexR       The VEX.R value (caller inverted it already).
    1127  */
    1128 DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex2bPrefix(PBS3CG1STATE pThis, unsigned offDst,
    1129                                                            uint8_t uVexV, uint8_t uVexL, uint8_t uVexR)
    1130 {
    1131     uint8_t b = uVexR << 7;
    1132     b        |= uVexV << 3;
    1133     b        |= uVexL << 2;
    1134     switch (pThis->enmPrefixKind)
    1135     {
    1136         case BS3CG1PFXKIND_NO_F2_F3_66:     b |= 0; break;
    1137         case BS3CG1PFXKIND_REQ_66:          b |= 1; break;
    1138         case BS3CG1PFXKIND_REQ_F3:          b |= 2; break;
    1139         case BS3CG1PFXKIND_REQ_F2:          b |= 3; break;
    1140         default:
    1141             Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n");
    1142             break;
    1143     }
    1144 
    1145     pThis->abCurInstr[offDst]     = 0xc5; /* vex2 */
    1146     pThis->abCurInstr[offDst + 1] = b;
    1147     return offDst + 2;
    1148 }
    1149 
    1150 
    1151 /**
    1152  * Inserts a 3-byte VEX prefix.
    1153  *
    1154  * @returns New offDst value.
    1155  * @param   pThis       The state.
    1156  * @param   offDst      The current instruction offset.
    1157  * @param   uVexL       The VEX.L value.
    1158  * @param   uVexV       The VEX.V value (caller inverted it already).
    1159  * @param   uVexR       The VEX.R value (caller inverted it already).
    1160  * @param   uVexR       The VEX.X value (caller inverted it already).
    1161  * @param   uVexR       The VEX.B value (caller inverted it already).
    1162  * @param   uVexR       The VEX.W value (straight).
    1163  */
    1164 DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex3bPrefix(PBS3CG1STATE pThis, unsigned offDst, uint8_t uVexV, uint8_t uVexL,
    1165                                                            uint8_t uVexR, uint8_t uVexX, uint8_t uVexB, uint8_t uVexW)
    1166 {
    1167     uint8_t b1;
    1168     uint8_t b2;
    1169     b1        = uVexR << 7;
    1170     b1       |= uVexX << 6;
    1171     b1       |= uVexB << 5;
    1172     b1       |= 1; /* VEX.mmmmm = 1*/ /** @todo three byte opcode tables */
    1173     b2        = uVexV << 3;
    1174     b2       |= uVexW << 7;
    1175     b2       |= uVexL << 2;
    1176     switch (pThis->enmPrefixKind)
    1177     {
    1178         case BS3CG1PFXKIND_NO_F2_F3_66:     b2 |= 0; break;
    1179         case BS3CG1PFXKIND_REQ_66:          b2 |= 1; break;
    1180         case BS3CG1PFXKIND_REQ_F3:          b2 |= 2; break;
    1181         case BS3CG1PFXKIND_REQ_F2:          b2 |= 3; break;
    1182         default:
    1183             Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n", pThis->enmPrefixKind);
    1184             break;
    1185     }
    1186 
    1187     pThis->abCurInstr[offDst]     = 0xc4; /* vex3 */
    1188     pThis->abCurInstr[offDst + 1] = b1;
    1189     pThis->abCurInstr[offDst + 2] = b2;
    1190     return offDst + 3;
    1191 }
    1192 
    1193 
    11941121DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertReqPrefix(PBS3CG1STATE pThis, unsigned offDst)
    11951122{
    … …  
    13261253
    13271254
    1328 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Eb_Gb(PBS3CG1STATE pThis, unsigned iEncoding)
     1255static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Eb_Gb(PBS3CG1STATE pThis, unsigned iEncoding)
    13291256{
    13301257    unsigned off;
    … …  
    13571284
    13581285
    1359 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gb_Eb(PBS3CG1STATE pThis, unsigned iEncoding)
     1286static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Gb_Eb(PBS3CG1STATE pThis, unsigned iEncoding)
    13601287{
    13611288    unsigned off;
    … …  
    13881315
    13891316
    1390 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ev__OR__BS3CG1ENC_MODRM_Ev_Gv(PBS3CG1STATE pThis,
     1317static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Gv_Ev__OR__MODRM_Ev_Gv(PBS3CG1STATE pThis,
    13911318                                                                                                unsigned iEncoding)
    13921319{
    … …  
    14681395
    14691396
    1470 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wss_WO_Vss(PBS3CG1STATE pThis, unsigned iEncoding)
     1397static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Wss_WO_Vss(PBS3CG1STATE pThis, unsigned iEncoding)
    14711398{
    14721399    unsigned off;
    … …  
    14971424
    14981425
    1499 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wsd_WO_Vsd(PBS3CG1STATE pThis, unsigned iEncoding)
     1426static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Wsd_WO_Vsd(PBS3CG1STATE pThis, unsigned iEncoding)
    15001427{
    15011428    unsigned off;
    … …  
    15261453
    15271454
    1528 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wps_WO_Vps__OR__BS3CG1ENC_MODRM_Wpd_WO_Vpd(PBS3CG1STATE pThis, unsigned iEncoding)
     1455static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Wps_WO_Vps__OR__MODRM_Wpd_WO_Vpd(PBS3CG1STATE pThis, unsigned iEncoding)
    15291456{
    15301457    unsigned off;
    … …  
    15571484
    15581485
    1559 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_WqZxReg_WO_Vq(PBS3CG1STATE pThis, unsigned iEncoding)
     1486static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_WqZxReg_WO_Vq(PBS3CG1STATE pThis, unsigned iEncoding)
    15601487{
    15611488    unsigned off;
    … …  
    15861513
    15871514
    1588 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Pq_WO_Uq(PBS3CG1STATE pThis, unsigned iEncoding)
     1515static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Pq_WO_Uq(PBS3CG1STATE pThis, unsigned iEncoding)
    15891516{
    15901517    unsigned off;
    … …  
    16101537
    16111538
    1612 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_WO_UqHi(PBS3CG1STATE pThis, unsigned iEncoding)
     1539static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vq_WO_UqHi(PBS3CG1STATE pThis, unsigned iEncoding)
    16131540{
    16141541    unsigned off;
    … …  
    16341561
    16351562
    1636 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_WO_Mq(PBS3CG1STATE pThis, unsigned iEncoding)
     1563static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vq_WO_Mq(PBS3CG1STATE pThis, unsigned iEncoding)
    16371564{
    16381565    unsigned off;
    … …  
    16561583
    16571584
    1658 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqHi_WO_Uq(PBS3CG1STATE pThis, unsigned iEncoding)
     1585static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_VqHi_WO_Uq(PBS3CG1STATE pThis, unsigned iEncoding)
    16591586{
    16601587    unsigned off;
    … …  
    16801607
    16811608
    1682 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqHi_WO_Mq(PBS3CG1STATE pThis, unsigned iEncoding)
     1609static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_VqHi_WO_Mq(PBS3CG1STATE pThis, unsigned iEncoding)
    16831610{
    16841611    unsigned off;
    … …  
    17021629
    17031630
    1704 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vdq_WO_Wdq(PBS3CG1STATE pThis, unsigned iEncoding)
     1631static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vdq_WO_Wdq(PBS3CG1STATE pThis, unsigned iEncoding)
    17051632{
    17061633    unsigned off;
    … …  
    17331660
    17341661
    1735 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vps_WO_Wps__OR__BS3CG1ENC_MODRM_Vpd_WO_Wpd(PBS3CG1STATE pThis,
    1736                                                                                                     unsigned iEncoding)
     1662static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vps_WO_Wps__OR__MODRM_Vpd_WO_Wpd(PBS3CG1STATE pThis,
     1663                                                                                                          unsigned iEncoding)
    17371664{
    17381665    unsigned off;
    … …  
    17651692
    17661693
    1767 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZx_WO_Wss(PBS3CG1STATE pThis, unsigned iEncoding)
     1694static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_VssZx_WO_Wss(PBS3CG1STATE pThis, unsigned iEncoding)
    17681695{
    17691696    unsigned off;
    … …  
    17941721
    17951722
    1796 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZx_WO_Wsd__OR__MODRM_VqZx_WO_Wq(PBS3CG1STATE pThis,
     1723static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_VsdZx_WO_Wsd__OR__MODRM_VqZx_WO_Wq(PBS3CG1STATE pThis,
    17971724                                                                                                  unsigned iEncoding)
    17981725{
    … …  
    18241751
    18251752
    1826 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZx_WO_Nq(PBS3CG1STATE pThis, unsigned iEncoding)
     1753static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_VqZx_WO_Nq(PBS3CG1STATE pThis, unsigned iEncoding)
    18271754{
    18281755    unsigned off;
    … …  
    18481775
    18491776
    1850 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_RO_Ma(PBS3CG1STATE pThis, unsigned iEncoding)
     1777static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Gv_RO_Ma(PBS3CG1STATE pThis, unsigned iEncoding)
    18511778{
    18521779    unsigned off;
    … …  
    18911818
    18921819
    1893 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Mb_RO(PBS3CG1STATE pThis, unsigned iEncoding)
     1820static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Mb_RO(PBS3CG1STATE pThis, unsigned iEncoding)
    18941821{
    18951822    unsigned off;
    … …  
    19081835
    19091836
    1910 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Md_RO(PBS3CG1STATE pThis, unsigned iEncoding)
     1837static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Md_RO(PBS3CG1STATE pThis, unsigned iEncoding)
    19111838{
    19121839    unsigned off;
    … …  
    19251852
    19261853
    1927 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Md_WO(PBS3CG1STATE pThis, unsigned iEncoding)
     1854static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Md_WO(PBS3CG1STATE pThis, unsigned iEncoding)
    19281855{
    19291856    unsigned off;
    … …  
    19421869
    19431870
    1944 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_VEX_MODRM_Md_WO(PBS3CG1STATE pThis, unsigned iEncoding)
     1871static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Mq_WO_Vq(PBS3CG1STATE pThis, unsigned iEncoding)
    19451872{
    19461873    unsigned off;
    19471874    if (iEncoding == 0)
    19481875    {
    1949         /** @todo three by opcode needs some tweaking. */
    1950         off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
    1951         off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
    1952         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
    1953                                        (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
    1954                                        4, 0, BS3CG1OPLOC_MEM_WO);
     1876        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
     1877        off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
     1878        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 8, 0, BS3CG1OPLOC_MEM_WO);
    19551879    }
    19561880    else if (iEncoding == 1)
    19571881    {
    1958         off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    1959         off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
    1960         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
    1961                                        (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
    1962                                        4, 0, BS3CG1OPLOC_MEM_WO);
    1963     }
    1964     else if (iEncoding == 2)
    1965     {
    1966         off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0x7 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    1967         off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
    1968         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
    1969                                        (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
    1970                                        4, 0, BS3CG1OPLOC_MEM_WO);
    1971         pThis->fInvalidEncoding = true;
    1972     }
    1973     else if (iEncoding == 3)
    1974     {
    1975         off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    1976         off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
    1977         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
    1978                                        (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
    1979                                        4, 0, BS3CG1OPLOC_MEM_WO);
    1980         pThis->fInvalidEncoding = true;
    1981     }
    1982     else if (iEncoding == 4)
    1983     {
    1984         pThis->abCurInstr[0] = P_OZ;
    1985         off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    1986         off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
    1987         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
    1988                                        (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
    1989                                        4, 0, BS3CG1OPLOC_MEM_WO);
    1990         pThis->fInvalidEncoding = true;
    1991     }
    1992     else if (iEncoding == 5)
    1993     {
    1994         pThis->abCurInstr[0] = P_RZ;
    1995         off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    1996         off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
    1997         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
    1998                                        (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
    1999                                        4, 0, BS3CG1OPLOC_MEM_WO);
    2000         pThis->fInvalidEncoding = true;
    2001     }
    2002     else if (iEncoding == 6)
    2003     {
    2004         pThis->abCurInstr[0] = P_RN;
    2005         off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    2006         off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
    2007         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
    2008                                        (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
    2009                                        4, 0, BS3CG1OPLOC_MEM_WO);
    2010         pThis->fInvalidEncoding = true;
    2011     }
    2012     else if (iEncoding == 7)
    2013     {
    2014         off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
    2015         off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
    2016         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
    2017                                        (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
    2018                                        4, 0, BS3CG1OPLOC_MEM_WO);
    2019     }
    2020 #if ARCH_BITS == 64
    2021     else if (BS3_MODE_IS_64BIT_CODE(pThis->bMode))
    2022     {
    2023         if (iEncoding == 8)
    2024         {
    2025             pThis->abCurInstr[0] = REX_____;
    2026             off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    2027             off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
    2028             off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
    2029                                            (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
    2030                                            4, 0, BS3CG1OPLOC_MEM_WO);
    2031             pThis->fInvalidEncoding = true;
    2032         }
    2033         else
    2034             return 0;
    2035     }
    2036 #endif
     1882        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
     1883        off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
     1884        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 8, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM_WO);
     1885    }
    20371886    else
    20381887        return 0;
    … …  
    20421891
    20431892
    2044 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Mq_WO_Vq(PBS3CG1STATE pThis, unsigned iEncoding)
     1893static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Mq_WO_VqHi(PBS3CG1STATE pThis, unsigned iEncoding)
    20451894{
    20461895    unsigned off;
    20471896    if (iEncoding == 0)
    20481897    {
    2049         pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
     1898        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_HI;
    20501899        off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    20511900        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 8, 0, BS3CG1OPLOC_MEM_WO);
    … …  
    20531902    else if (iEncoding == 1)
    20541903    {
    2055         pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
     1904        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_HI;
    20561905        off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    20571906        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 8, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM_WO);
    … …  
    20641913
    20651914
    2066 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Mq_WO_VqHi(PBS3CG1STATE pThis, unsigned iEncoding)
    2067 {
    2068     unsigned off;
    2069     if (iEncoding == 0)
    2070     {
    2071         pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_HI;
    2072         off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    2073         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 8, 0, BS3CG1OPLOC_MEM_WO);
    2074     }
    2075     else if (iEncoding == 1)
    2076     {
    2077         pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_HI;
    2078         off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    2079         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 8, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM_WO);
    2080     }
    2081     else
    2082         return 0;
    2083     pThis->cbCurInstr = off;
    2084     return iEncoding + 1;
    2085 }
    2086 
    2087 
    2088 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_FIXED(PBS3CG1STATE pThis, unsigned iEncoding)
     1915static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_FIXED(PBS3CG1STATE pThis, unsigned iEncoding)
    20891916{
    20901917    unsigned off;
    … …  
    21011928
    21021929
    2103 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_FIXED_AL_Ib(PBS3CG1STATE pThis, unsigned iEncoding)
     1930static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_FIXED_AL_Ib(PBS3CG1STATE pThis, unsigned iEncoding)
    21041931{
    21051932    unsigned off;
    … …  
    21171944
    21181945
    2119 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_FIXED_rAX_Iz(PBS3CG1STATE pThis, unsigned iEncoding)
     1946static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_FIXED_rAX_Iz(PBS3CG1STATE pThis, unsigned iEncoding)
    21201947{
    21211948    unsigned off;
    … …  
    21822009
    21832010
    2184 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MOD_EQ_3(PBS3CG1STATE pThis, unsigned iEncoding)
     2011static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_MOD_EQ_3(PBS3CG1STATE pThis, unsigned iEncoding)
    21852012{
    21862013    unsigned off;
    … …  
    22052032
    22062033
    2207 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MOD_NE_3(PBS3CG1STATE pThis, unsigned iEncoding)
     2034static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_MOD_NE_3(PBS3CG1STATE pThis, unsigned iEncoding)
    22082035{
    22092036    unsigned off;
    … …  
    22322059
    22332060
     2061/*
     2062 *
     2063 * VEX
     2064 * VEX
     2065 * VEX
     2066 *
     2067 */
     2068#ifdef BS3CG1_WITH_VEX
     2069
     2070/**
     2071 * Inserts a 2-byte VEX prefix.
     2072 *
     2073 * @returns New offDst value.
     2074 * @param   pThis       The state.
     2075 * @param   offDst      The current instruction offset.
     2076 * @param   uVexL       The VEX.L value.
     2077 * @param   uVexV       The VEX.V value (caller inverted it already).
     2078 * @param   uVexR       The VEX.R value (caller inverted it already).
     2079 */
     2080DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex2bPrefix(PBS3CG1STATE pThis, unsigned offDst,
     2081                                                           uint8_t uVexV, uint8_t uVexL, uint8_t uVexR)
     2082{
     2083    uint8_t b = uVexR << 7;
     2084    b        |= uVexV << 3;
     2085    b        |= uVexL << 2;
     2086    switch (pThis->enmPrefixKind)
     2087    {
     2088        case BS3CG1PFXKIND_NO_F2_F3_66:     b |= 0; break;
     2089        case BS3CG1PFXKIND_REQ_66:          b |= 1; break;
     2090        case BS3CG1PFXKIND_REQ_F3:          b |= 2; break;
     2091        case BS3CG1PFXKIND_REQ_F2:          b |= 3; break;
     2092        default:
     2093            Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n");
     2094            break;
     2095    }
     2096
     2097    pThis->abCurInstr[offDst]     = 0xc5; /* vex2 */
     2098    pThis->abCurInstr[offDst + 1] = b;
     2099    return offDst + 2;
     2100}
     2101
     2102
     2103/**
     2104 * Inserts a 3-byte VEX prefix.
     2105 *
     2106 * @returns New offDst value.
     2107 * @param   pThis       The state.
     2108 * @param   offDst      The current instruction offset.
     2109 * @param   uVexL       The VEX.L value.
     2110 * @param   uVexV       The VEX.V value (caller inverted it already).
     2111 * @param   uVexR       The VEX.R value (caller inverted it already).
     2112 * @param   uVexR       The VEX.X value (caller inverted it already).
     2113 * @param   uVexR       The VEX.B value (caller inverted it already).
     2114 * @param   uVexR       The VEX.W value (straight).
     2115 */
     2116DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex3bPrefix(PBS3CG1STATE pThis, unsigned offDst, uint8_t uVexV, uint8_t uVexL,
     2117                                                           uint8_t uVexR, uint8_t uVexX, uint8_t uVexB, uint8_t uVexW)
     2118{
     2119    uint8_t b1;
     2120    uint8_t b2;
     2121    b1        = uVexR << 7;
     2122    b1       |= uVexX << 6;
     2123    b1       |= uVexB << 5;
     2124    b1       |= 1; /* VEX.mmmmm = 1*/ /** @todo three byte opcode tables */
     2125    b2        = uVexV << 3;
     2126    b2       |= uVexW << 7;
     2127    b2       |= uVexL << 2;
     2128    switch (pThis->enmPrefixKind)
     2129    {
     2130        case BS3CG1PFXKIND_NO_F2_F3_66:     b2 |= 0; break;
     2131        case BS3CG1PFXKIND_REQ_66:          b2 |= 1; break;
     2132        case BS3CG1PFXKIND_REQ_F3:          b2 |= 2; break;
     2133        case BS3CG1PFXKIND_REQ_F2:          b2 |= 3; break;
     2134        default:
     2135            Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n", pThis->enmPrefixKind);
     2136            break;
     2137    }
     2138
     2139    pThis->abCurInstr[offDst]     = 0xc4; /* vex3 */
     2140    pThis->abCurInstr[offDst + 1] = b1;
     2141    pThis->abCurInstr[offDst + 2] = b2;
     2142    return offDst + 3;
     2143}
     2144
     2145
     2146static unsigned Bs3Cg1EncodeNext_VEX_MODRM_Vps_WO_Wps(PBS3CG1STATE pThis, unsigned iEncoding)
     2147{
     2148    unsigned off;
     2149    /* 128-bit wide stuff goes first, then we'll update the operand widths afterwards. */
     2150    if (iEncoding == 0)
     2151    {
     2152        off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
     2153        off = Bs3Cg1InsertOpcodes(pThis, off);
     2154        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
     2155        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0;
     2156        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1;
     2157    }
     2158    else if (iEncoding == 1)
     2159    {
     2160        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2161        off = Bs3Cg1InsertOpcodes(pThis, off);
     2162        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 4, 5);
     2163        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM5;
     2164        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM4;
     2165    }
     2166    else if (iEncoding == 2)
     2167    {
     2168        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W - ignored*/);
     2169        off = Bs3Cg1InsertOpcodes(pThis, off);
     2170        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 5, 4);
     2171        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM4;
     2172        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM5;
     2173    }
     2174    else if (iEncoding == 3)
     2175    {
     2176        off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
     2177        off = Bs3Cg1InsertOpcodes(pThis, off);
     2178        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 16, 0, BS3CG1OPLOC_MEM);
     2179        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2;
     2180    }
     2181    else if (iEncoding == 4)
     2182    {
     2183        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2184        off = Bs3Cg1InsertOpcodes(pThis, off);
     2185        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 16, 0, BS3CG1OPLOC_MEM);
     2186        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
     2187    }
     2188    else if (iEncoding == 5)
     2189    {
     2190        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W - ignored */);
     2191        off = Bs3Cg1InsertOpcodes(pThis, off);
     2192        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 16, 0, BS3CG1OPLOC_MEM);
     2193        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
     2194    }
     2195    else if (iEncoding == 6)
     2196    {
     2197        off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
     2198        off = Bs3Cg1InsertOpcodes(pThis, off);
     2199        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 16, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM);
     2200        if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
     2201            pThis->bAlignmentXcpt = X86_XCPT_GP;
     2202        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
     2203    }
     2204    else if (iEncoding == 7)
     2205    {
     2206        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2207        off = Bs3Cg1InsertOpcodes(pThis, off);
     2208        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 16, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM);
     2209        if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
     2210            pThis->bAlignmentXcpt = X86_XCPT_GP;
     2211        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
     2212    }
     2213    /* 128-bit invalid encodings: */
     2214    else if (iEncoding == 8)
     2215    {
     2216        off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, 0 /*L*/, 1 /*~R*/); /* Bad V value */
     2217        off = Bs3Cg1InsertOpcodes(pThis, off);
     2218        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
     2219        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0;
     2220        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1;
     2221        pThis->fInvalidEncoding = true;
     2222    }
     2223    else if (iEncoding == 9)
     2224    {
     2225        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2226        off = Bs3Cg1InsertOpcodes(pThis, off);
     2227        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 4, 5);
     2228        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM5;
     2229        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM4;
     2230        pThis->fInvalidEncoding = true;
     2231    }
     2232    /* 256-bit encodings: */
     2233    else if (iEncoding == 10)
     2234    {
     2235        off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/);
     2236        off = Bs3Cg1InsertOpcodes(pThis, off);
     2237        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
     2238        pThis->aOperands[pThis->iRmOp].cbOp      = 32;
     2239        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_YMM0;
     2240        pThis->aOperands[pThis->iRegOp].cbOp     = 32;
     2241        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM1;
     2242    }
     2243    else if (iEncoding == 11)
     2244    {
     2245        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2246        off = Bs3Cg1InsertOpcodes(pThis, off);
     2247        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 4, 5);
     2248        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_YMM5;
     2249        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM4;
     2250    }
     2251    else if (iEncoding == 12)
     2252    {
     2253        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W - ignored*/);
     2254        off = Bs3Cg1InsertOpcodes(pThis, off);
     2255        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 5, 4);
     2256        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_YMM4;
     2257        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM5;
     2258    }
     2259    else if (iEncoding == 13)
     2260    {
     2261        off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/);
     2262        off = Bs3Cg1InsertOpcodes(pThis, off);
     2263        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 32, 0, BS3CG1OPLOC_MEM);
     2264        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM2;
     2265    }
     2266    else if (iEncoding == 14)
     2267    {
     2268        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2269        off = Bs3Cg1InsertOpcodes(pThis, off);
     2270        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 32, 0, BS3CG1OPLOC_MEM);
     2271        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM3;
     2272    }
     2273    else if (iEncoding == 15)
     2274    {
     2275        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W - ignored */);
     2276        off = Bs3Cg1InsertOpcodes(pThis, off);
     2277        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 32, 0, BS3CG1OPLOC_MEM);
     2278        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM3;
     2279    }
     2280    else if (iEncoding == 16)
     2281    {
     2282        off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/);
     2283        off = Bs3Cg1InsertOpcodes(pThis, off);
     2284        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 32, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM);
     2285        if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
     2286            pThis->bAlignmentXcpt = X86_XCPT_GP;
     2287        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM3;
     2288    }
     2289    else if (iEncoding == 17)
     2290    {
     2291        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2292        off = Bs3Cg1InsertOpcodes(pThis, off);
     2293        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 32, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM);
     2294        if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
     2295            pThis->bAlignmentXcpt = X86_XCPT_GP;
     2296        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM3;
     2297    }
     2298    /* 256-bit invalid encodings: */
     2299    else if (iEncoding == 18)
     2300    {
     2301        off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V - invalid */, 1 /*L*/, 1 /*~R*/); /* Bad V value */
     2302        off = Bs3Cg1InsertOpcodes(pThis, off);
     2303        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
     2304        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_YMM0;
     2305        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM1;
     2306        pThis->fInvalidEncoding = true;
     2307    }
     2308    else if (iEncoding == 19)
     2309    {
     2310        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V - invalid */, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2311        off = Bs3Cg1InsertOpcodes(pThis, off);
     2312        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 4, 5);
     2313        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_YMM5;
     2314        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM4;
     2315        pThis->fInvalidEncoding = true;
     2316    }
     2317    else if (iEncoding == 20)
     2318    {
     2319        pThis->abCurInstr[0] = P_RN;
     2320        off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2321        off = Bs3Cg1InsertOpcodes(pThis, off);
     2322        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 4, 5);
     2323        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_YMM5;
     2324        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM4;
     2325        pThis->fInvalidEncoding = true;
     2326    }
     2327    else if (iEncoding == 21)
     2328    {
     2329        pThis->abCurInstr[0] = P_RZ;
     2330        off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2331        off = Bs3Cg1InsertOpcodes(pThis, off);
     2332        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 4, 5);
     2333        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_YMM5;
     2334        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM4;
     2335        pThis->fInvalidEncoding = true;
     2336    }
     2337    else if (iEncoding == 22)
     2338    {
     2339        pThis->abCurInstr[0] = P_OZ;
     2340        off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2341        off = Bs3Cg1InsertOpcodes(pThis, off);
     2342        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 4, 5);
     2343        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_YMM5;
     2344        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM4;
     2345        pThis->fInvalidEncoding = true;
     2346    }
     2347    else if (iEncoding == 23)
     2348    {
     2349        pThis->abCurInstr[0] = P_LK;
     2350        off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2351        off = Bs3Cg1InsertOpcodes(pThis, off);
     2352        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 4, 5);
     2353        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_YMM5;
     2354        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM4;
     2355        pThis->fInvalidEncoding = true;
     2356    }
     2357#if ARCH_BITS == 64
     2358    /* 64-bit mode registers */
     2359    else if (BS3_MODE_IS_64BIT_CODE(pThis->bMode))
     2360    {
     2361        if (iEncoding == 24)
     2362        {
     2363            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 0 /*~R*/);
     2364            off = Bs3Cg1InsertOpcodes(pThis, off);
     2365            pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 3, 4);
     2366            pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_YMM4;
     2367            pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM11;
     2368        }
     2369        else if (iEncoding == 25)
     2370        {
     2371            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 0 /*~R*/, 1 /*~X*/, 0 /*~B*/, 0 /*W*/);
     2372            off = Bs3Cg1InsertOpcodes(pThis, off);
     2373            pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 4);
     2374            pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_YMM12;
     2375            pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_YMM9;
     2376        }
     2377        else
     2378            return 0;
     2379    }
     2380#endif
     2381    else
     2382        return 0;
     2383    pThis->cbCurInstr = off;
     2384    return iEncoding + 1;
     2385}
     2386
     2387
     2388static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_Md_WO(PBS3CG1STATE pThis, unsigned iEncoding)
     2389{
     2390    unsigned off;
     2391    if (iEncoding == 0)
     2392    {
     2393        /** @todo three by opcode needs some tweaking. */
     2394        off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
     2395        off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
     2396        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
     2397                                       (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
     2398                                       4, 0, BS3CG1OPLOC_MEM_WO);
     2399    }
     2400    else if (iEncoding == 1)
     2401    {
     2402        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2403        off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
     2404        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
     2405                                       (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
     2406                                       4, 0, BS3CG1OPLOC_MEM_WO);
     2407    }
     2408    else if (iEncoding == 2)
     2409    {
     2410        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0x7 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2411        off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
     2412        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
     2413                                       (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
     2414                                       4, 0, BS3CG1OPLOC_MEM_WO);
     2415        pThis->fInvalidEncoding = true;
     2416    }
     2417    else if (iEncoding == 3)
     2418    {
     2419        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2420        off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
     2421        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
     2422                                       (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
     2423                                       4, 0, BS3CG1OPLOC_MEM_WO);
     2424        pThis->fInvalidEncoding = true;
     2425    }
     2426    else if (iEncoding == 4)
     2427    {
     2428        pThis->abCurInstr[0] = P_OZ;
     2429        off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2430        off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
     2431        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
     2432                                       (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
     2433                                       4, 0, BS3CG1OPLOC_MEM_WO);
     2434        pThis->fInvalidEncoding = true;
     2435    }
     2436    else if (iEncoding == 5)
     2437    {
     2438        pThis->abCurInstr[0] = P_RZ;
     2439        off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2440        off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
     2441        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
     2442                                       (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
     2443                                       4, 0, BS3CG1OPLOC_MEM_WO);
     2444        pThis->fInvalidEncoding = true;
     2445    }
     2446    else if (iEncoding == 6)
     2447    {
     2448        pThis->abCurInstr[0] = P_RN;
     2449        off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2450        off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
     2451        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
     2452                                       (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
     2453                                       4, 0, BS3CG1OPLOC_MEM_WO);
     2454        pThis->fInvalidEncoding = true;
     2455    }
     2456    else if (iEncoding == 7)
     2457    {
     2458        off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
     2459        off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
     2460        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
     2461                                       (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
     2462                                       4, 0, BS3CG1OPLOC_MEM_WO);
     2463    }
     2464#if ARCH_BITS == 64
     2465    else if (BS3_MODE_IS_64BIT_CODE(pThis->bMode))
     2466    {
     2467        if (iEncoding == 8)
     2468        {
     2469            pThis->abCurInstr[0] = REX_____;
     2470            off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
     2471            off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
     2472            off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
     2473                                           (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
     2474                                           4, 0, BS3CG1OPLOC_MEM_WO);
     2475            pThis->fInvalidEncoding = true;
     2476        }
     2477        else
     2478            return 0;
     2479    }
     2480#endif
     2481    else
     2482        return 0;
     2483    pThis->cbCurInstr = off;
     2484    return iEncoding + 1;
     2485}
     2486
     2487#endif /* BS3CG1_WITH_VEX */
     2488
     2489
     2490
    22342491/**
    22352492 * Encodes the next instruction.
    … …  
    22492506    {
    22502507        case BS3CG1ENC_MODRM_Eb_Gb:
    2251             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Eb_Gb(pThis, iEncoding);
     2508            return Bs3Cg1EncodeNext_MODRM_Eb_Gb(pThis, iEncoding);
    22522509        case BS3CG1ENC_MODRM_Gb_Eb:
    2253             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gb_Eb(pThis, iEncoding);
     2510            return Bs3Cg1EncodeNext_MODRM_Gb_Eb(pThis, iEncoding);
    22542511        case BS3CG1ENC_MODRM_Gv_Ev:
    22552512        case BS3CG1ENC_MODRM_Ev_Gv:
    2256             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ev__OR__BS3CG1ENC_MODRM_Ev_Gv(pThis, iEncoding);
     2513            return Bs3Cg1EncodeNext_MODRM_Gv_Ev__OR__MODRM_Ev_Gv(pThis, iEncoding);
    22572514
    22582515        case BS3CG1ENC_MODRM_Wss_WO_Vss:
    2259             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wss_WO_Vss(pThis, iEncoding);
     2516            return Bs3Cg1EncodeNext_MODRM_Wss_WO_Vss(pThis, iEncoding);
    22602517        case BS3CG1ENC_MODRM_Wsd_WO_Vsd:
    2261             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wsd_WO_Vsd(pThis, iEncoding);
     2518            return Bs3Cg1EncodeNext_MODRM_Wsd_WO_Vsd(pThis, iEncoding);
    22622519        case BS3CG1ENC_MODRM_Wps_WO_Vps:
    22632520        case BS3CG1ENC_MODRM_Wpd_WO_Vpd:
    2264             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wps_WO_Vps__OR__BS3CG1ENC_MODRM_Wpd_WO_Vpd(pThis, iEncoding);
     2521            return Bs3Cg1EncodeNext_MODRM_Wps_WO_Vps__OR__MODRM_Wpd_WO_Vpd(pThis, iEncoding);
    22652522        case BS3CG1ENC_MODRM_WqZxReg_WO_Vq:
    2266             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_WqZxReg_WO_Vq(pThis, iEncoding);
     2523            return Bs3Cg1EncodeNext_MODRM_WqZxReg_WO_Vq(pThis, iEncoding);
    22672524
    22682525        case BS3CG1ENC_MODRM_Pq_WO_Uq:
    2269             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Pq_WO_Uq(pThis, iEncoding);
     2526            return Bs3Cg1EncodeNext_MODRM_Pq_WO_Uq(pThis, iEncoding);
    22702527
    22712528        case BS3CG1ENC_MODRM_Vq_WO_UqHi:
    2272             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_WO_UqHi(pThis, iEncoding);
     2529            return Bs3Cg1EncodeNext_MODRM_Vq_WO_UqHi(pThis, iEncoding);
    22732530        case BS3CG1ENC_MODRM_Vq_WO_Mq:
    2274             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_WO_Mq(pThis, iEncoding);
     2531            return Bs3Cg1EncodeNext_MODRM_Vq_WO_Mq(pThis, iEncoding);
    22752532        case BS3CG1ENC_MODRM_VqHi_WO_Uq:
    2276             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqHi_WO_Uq(pThis, iEncoding);
     2533            return Bs3Cg1EncodeNext_MODRM_VqHi_WO_Uq(pThis, iEncoding);
    22772534        case BS3CG1ENC_MODRM_VqHi_WO_Mq:
    2278             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqHi_WO_Mq(pThis, iEncoding);
     2535            return Bs3Cg1EncodeNext_MODRM_VqHi_WO_Mq(pThis, iEncoding);
    22792536        case BS3CG1ENC_MODRM_Vdq_WO_Wdq:
    2280             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vdq_WO_Wdq(pThis, iEncoding);
     2537            return Bs3Cg1EncodeNext_MODRM_Vdq_WO_Wdq(pThis, iEncoding);
    22812538        case BS3CG1ENC_MODRM_Vpd_WO_Wpd:
    22822539        case BS3CG1ENC_MODRM_Vps_WO_Wps:
    2283             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vps_WO_Wps__OR__BS3CG1ENC_MODRM_Vpd_WO_Wpd(pThis, iEncoding);
     2540            return Bs3Cg1EncodeNext_MODRM_Vps_WO_Wps__OR__MODRM_Vpd_WO_Wpd(pThis, iEncoding);
    22842541        case BS3CG1ENC_MODRM_VssZx_WO_Wss:
    2285             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZx_WO_Wss(pThis, iEncoding);
     2542            return Bs3Cg1EncodeNext_MODRM_VssZx_WO_Wss(pThis, iEncoding);
    22862543        case BS3CG1ENC_MODRM_VsdZx_WO_Wsd:
    22872544        case BS3CG1ENC_MODRM_VqZx_WO_Wq:
    2288             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZx_WO_Wsd__OR__MODRM_VqZx_WO_Wq(pThis, iEncoding);
     2545            return Bs3Cg1EncodeNext_MODRM_VsdZx_WO_Wsd__OR__MODRM_VqZx_WO_Wq(pThis, iEncoding);
    22892546        case BS3CG1ENC_MODRM_VqZx_WO_Nq:
    2290             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZx_WO_Nq(pThis, iEncoding);
     2547            return Bs3Cg1EncodeNext_MODRM_VqZx_WO_Nq(pThis, iEncoding);
    22912548
    22922549        case BS3CG1ENC_MODRM_Gv_RO_Ma:
    2293             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_RO_Ma(pThis, iEncoding);
     2550            return Bs3Cg1EncodeNext_MODRM_Gv_RO_Ma(pThis, iEncoding);
    22942551
    22952552        case BS3CG1ENC_MODRM_Mb_RO:
    2296             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Mb_RO(pThis, iEncoding);
     2553            return Bs3Cg1EncodeNext_MODRM_Mb_RO(pThis, iEncoding);
    22972554        case BS3CG1ENC_MODRM_Md_RO:
    2298             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Md_RO(pThis, iEncoding);
     2555            return Bs3Cg1EncodeNext_MODRM_Md_RO(pThis, iEncoding);
    22992556        case BS3CG1ENC_MODRM_Md_WO:
    2300             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Md_WO(pThis, iEncoding);
     2557            return Bs3Cg1EncodeNext_MODRM_Md_WO(pThis, iEncoding);
     2558        case BS3CG1ENC_MODRM_Mq_WO_Vq:
     2559            return Bs3Cg1EncodeNext_MODRM_Mq_WO_Vq(pThis, iEncoding);
     2560        case BS3CG1ENC_MODRM_Mq_WO_VqHi:
     2561            return Bs3Cg1EncodeNext_MODRM_Mq_WO_VqHi(pThis, iEncoding);
     2562
     2563        case BS3CG1ENC_FIXED:
     2564            return Bs3Cg1EncodeNext_FIXED(pThis, iEncoding);
     2565        case BS3CG1ENC_FIXED_AL_Ib:
     2566            return Bs3Cg1EncodeNext_FIXED_AL_Ib(pThis, iEncoding);
     2567        case BS3CG1ENC_FIXED_rAX_Iz:
     2568            return Bs3Cg1EncodeNext_FIXED_rAX_Iz(pThis, iEncoding);
     2569
     2570        case BS3CG1ENC_MODRM_MOD_EQ_3:
     2571            return Bs3Cg1EncodeNext_MODRM_MOD_EQ_3(pThis, iEncoding);
     2572        case BS3CG1ENC_MODRM_MOD_NE_3:
     2573            return Bs3Cg1EncodeNext_MODRM_MOD_NE_3(pThis, iEncoding);
     2574
     2575        /*
     2576         * VEX stuff
     2577         */
     2578#ifdef BS3CG1_WITH_VEX
     2579        case BS3CG1ENC_VEX_MODRM_Vps_WO_Wps:
     2580            return Bs3Cg1EncodeNext_VEX_MODRM_Vps_WO_Wps(pThis, iEncoding);
     2581
    23012582        case BS3CG1ENC_VEX_MODRM_Md_WO:
    2302             return Bs3Cg1EncodeNext_BS3CG1ENC_VEX_MODRM_Md_WO(pThis, iEncoding);
    2303         case BS3CG1ENC_MODRM_Mq_WO_Vq:
    2304             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Mq_WO_Vq(pThis, iEncoding);
    2305         case BS3CG1ENC_MODRM_Mq_WO_VqHi:
    2306             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Mq_WO_VqHi(pThis, iEncoding);
    2307 
    2308         case BS3CG1ENC_FIXED:
    2309             return Bs3Cg1EncodeNext_BS3CG1ENC_FIXED(pThis, iEncoding);
    2310         case BS3CG1ENC_FIXED_AL_Ib:
    2311             return Bs3Cg1EncodeNext_BS3CG1ENC_FIXED_AL_Ib(pThis, iEncoding);
    2312         case BS3CG1ENC_FIXED_rAX_Iz:
    2313             return Bs3Cg1EncodeNext_BS3CG1ENC_FIXED_rAX_Iz(pThis, iEncoding);
    2314 
    2315         case BS3CG1ENC_MODRM_MOD_EQ_3:
    2316             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MOD_EQ_3(pThis, iEncoding);
    2317         case BS3CG1ENC_MODRM_MOD_NE_3:
    2318             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MOD_NE_3(pThis, iEncoding);
     2583            return Bs3Cg1EncodeNext_VEX_MODRM_Md_WO(pThis, iEncoding);
     2584
     2585#endif /* BS3CG1_WITH_VEX */
    23192586
    23202587        default:
    … …  
    25452812            /* Unused or invalid instructions mostly. */
    25462813            break;
     2814
     2815#ifdef BS3CG1_WITH_VEX
     2816
     2817        case BS3CG1ENC_VEX_MODRM_Vps_WO_Wps:
     2818            pThis->iRmOp             = 1;
     2819            pThis->iRegOp            = 0;
     2820            pThis->aOperands[0].cbOp = 16;
     2821            pThis->aOperands[1].cbOp = 16;
     2822            pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
     2823            pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
     2824            break;
     2825
     2826#endif /* BS3CG1_WITH_VEX */
    25472827
    25482828        default:
    … …  
    29023182        BS3CG1DST       idxField;
    29033183        BS3PTRUNION     PtrField;
    2904 
    2905         /* Expand the destiation field (can be escaped). */
     3184        bool            fZxVlMax;
     3185
     3186        /* Expand the destiation field (can be escaped). Set fZxVlMax. */
    29063187        switch (bOpcode & BS3CG1_CTXOP_DST_MASK)
    29073188        {
    … …  
    29103191                if (idxField == BS3CG1DST_INVALID)
    29113192                    idxField = BS3CG1DST_OP1;
     3193                fZxVlMax = pEflCtx != NULL && pThis->aOperands[0].enmLocation == BS3CG1OPLOC_CTX_ZX_VLMAX;
    29123194                break;
    29133195
    … …  
    29163198                if (idxField == BS3CG1DST_INVALID)
    29173199                    idxField = BS3CG1DST_OP2;
     3200                fZxVlMax = pEflCtx != NULL && pThis->aOperands[1].enmLocation == BS3CG1OPLOC_CTX_ZX_VLMAX;
    29183201                break;
    29193202
    29203203            case BS3CG1_CTXOP_EFL:
    29213204                idxField = BS3CG1DST_EFL;
     3205                fZxVlMax = false;
    29223206                break;
    29233207
    … …  
    29303214                        if (idxField > BS3CG1DST_INVALID)
    29313215                        {
    2932                             uint8_t idxField2 = pThis->aOperands[idxField - BS3CG1DST_OP1].idxField;
     3216                            unsigned idxOp     = idxField - BS3CG1DST_OP1;
     3217                            uint8_t  idxField2 = pThis->aOperands[idxOp].idxField;
    29333218                            if (idxField2 != BS3CG1DST_INVALID)
    29343219                                idxField = idxField2;
     3220                            fZxVlMax = pEflCtx != NULL && pThis->aOperands[idxOp].enmLocation == BS3CG1OPLOC_CTX_ZX_VLMAX;
    29353221                            break;
    29363222                        }
    … …  
    29443230                return Bs3TestFailed("Malformed context instruction: Destination");
    29453231        }
    2946 
    29473232
    29483233        /* Expand value size (can be escaped). */
    … …  
    29893274             * Deal with fields up to 8-byte wide.
    29903275             */
     3276
    29913277            /* Get the value. */
    29923278            uint64_t uValue;
    … …  
    30843370            /** @todo other FPU fields and FPU state formats. */
    30853371            else
    3086                 return Bs3TestFailedF("Todo implement me: cbDst=%u idxField=%d offField=%#x", cbDst, idxField, offField);
     3372                return Bs3TestFailedF("Todo implement me: cbDst=%u idxField=%d offField=%#x (<= 8)", cbDst, idxField, offField);
    30873373
    30883374#ifdef BS3CG1_DEBUG_CTX_MOD
    … …  
    31323418
    31333419                case 4:
    3134                     if ((unsigned)(idxField - BS3CG1DST_XMM0_DW0_ZX) <= (unsigned)(BS3CG1DST_XMM15_DW0_ZX - BS3CG1DST_XMM0_DW0_ZX))
     3420                    if (   (unsigned)(idxField - BS3CG1DST_XMM0_DW0_ZX) <= (unsigned)(BS3CG1DST_XMM15_DW0_ZX - BS3CG1DST_XMM0_DW0_ZX)
     3421                        || fZxVlMax)
    31353422                    {
    31363423                        PtrField.pu32[1] = 0;
    … …  
    31493436
    31503437                case 8:
    3151                     if ((unsigned)(idxField - BS3CG1DST_XMM0_LO_ZX) <= (unsigned)(BS3CG1DST_XMM15_LO_ZX - BS3CG1DST_XMM0_LO_ZX))
     3438                    if (   (unsigned)(idxField - BS3CG1DST_XMM0_LO_ZX) <= (unsigned)(BS3CG1DST_XMM15_LO_ZX - BS3CG1DST_XMM0_LO_ZX)
     3439                        || fZxVlMax)
    31523440                        PtrField.pu64[1] = 0;
    31533441                    else if ((unsigned)(idxField - BS3CG1DST_MM0) <= (unsigned)(BS3CG1DST_MM7 - BS3CG1DST_MM0))
    … …  
    31763464            }
    31773465#endif
    3178 
     3466            if (fZxVlMax)
     3467            {
     3468                uintptr_t iReg = ((uintptr_t)PtrField.pu8 - (uintptr_t)&pThis->pExtCtx->Ctx.x87.aXMM[0])
     3469                               / sizeof(pThis->pExtCtx->Ctx.x87.aXMM[0]);
     3470                pThis->pExtCtx->Ctx.x.u.YmmHi.aYmmHi[iReg].au64[0] = 0;
     3471                pThis->pExtCtx->Ctx.x.u.YmmHi.aYmmHi[iReg].au64[1] = 0;
     3472#ifdef BS3CG1_DEBUG_CTX_MOD
     3473                BS3CG1_DPRINTF(("dbg:    --> cleared YMM%u_HI\n", iReg));
     3474#endif
     3475            }
    31793476        }
    31803477        /*
    … …  
    31913488                uint8_t     ab[sizeof(X86ZMMREG)];
    31923489                uint32_t    au32[sizeof(X86ZMMREG) / sizeof(uint32_t)];
     3490                uint64_t    au64[sizeof(X86ZMMREG) / sizeof(uint64_t)];
    31933491            } Value;
    3194             unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
     3492            unsigned const  offField = g_aoffBs3Cg1DstFields[idxField];
     3493            unsigned        iReg;
    31953494
    31963495            if (!pThis->fWorkExtCtx)
    … …  
    32373536                }
    32383537            }
    3239             /* The YMM (AVX) and the first 16 ZMM (AVX512) registers have split storage in
    3240                the state, so they need special handling.  */
     3538            /* The YMM (AVX) registers have split storage in the state, so they need special handling. */
     3539            else if ((iReg = idxField - BS3CG1DST_YMM0) < 16U)
     3540            {
     3541                /* The first 128-bits in XMM land. */
     3542                PtrField.pu64 = &pThis->pExtCtx->Ctx.x87.aXMM[iReg].au64[0];
     3543                switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
     3544                {
     3545                    case BS3CG1_CTXOP_ASSIGN:
     3546                        PtrField.pu64[0]  =  Value.au64[0];
     3547                        PtrField.pu64[1]  =  Value.au64[1];
     3548                        break;
     3549                    case BS3CG1_CTXOP_OR:
     3550                        PtrField.pu64[0] |=  Value.au64[0];
     3551                        PtrField.pu64[1] |=  Value.au64[1];
     3552                        break;
     3553                    case BS3CG1_CTXOP_AND:
     3554                        PtrField.pu64[0] &=  Value.au64[0];
     3555                        PtrField.pu64[1] &=  Value.au64[1];
     3556                        break;
     3557                    case BS3CG1_CTXOP_AND_INV:
     3558                        PtrField.pu64[0] &= ~Value.au64[0];
     3559                        PtrField.pu64[1] &= ~Value.au64[1];
     3560                        break;
     3561                }
     3562
     3563                /* The second 128-bit in YMM_HI land. */
     3564                PtrField.pu64 = &pThis->pExtCtx->Ctx.x.u.YmmHi.aYmmHi[iReg].au64[0];
     3565                switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
     3566                {
     3567                    case BS3CG1_CTXOP_ASSIGN:
     3568                        PtrField.pu64[0]  =  Value.au64[2];
     3569                        PtrField.pu64[1]  =  Value.au64[3];
     3570                        break;
     3571                    case BS3CG1_CTXOP_OR:
     3572                        PtrField.pu64[0] |=  Value.au64[2];
     3573                        PtrField.pu64[1] |=  Value.au64[3];
     3574                        break;
     3575                    case BS3CG1_CTXOP_AND:
     3576                        PtrField.pu64[0] &=  Value.au64[2];
     3577                        PtrField.pu64[1] &=  Value.au64[3];
     3578                        break;
     3579                    case BS3CG1_CTXOP_AND_INV:
     3580                        PtrField.pu64[0] &= ~Value.au64[2];
     3581                        PtrField.pu64[1] &= ~Value.au64[3];
     3582                        break;
     3583                }
     3584                PtrField.pb = NULL;
     3585            }
     3586            /* AVX512 needs handling like above, but more complicated. */
    32413587            else
    3242             {
    32433588                return Bs3TestFailedF("TODO: implement me: cbDst=%d idxField=%d (AVX and other weird state)", cbDst, idxField);
    3244             }
    32453589
    32463590            if (PtrField.pb)
    … …  
    32713615                BS3CG1_DPRINTF(("dbg:    --> %s: %.*Rhxs\n", g_aszBs3Cg1DstFields[idxField].sz, cbDst, PtrField.pb));
    32723616#endif
     3617
     3618                if (fZxVlMax)
     3619                {
     3620                    uintptr_t iReg = ((uintptr_t)PtrField.pu8 - (uintptr_t)&pThis->pExtCtx->Ctx.x87.aXMM[0])
     3621                                   / sizeof(pThis->pExtCtx->Ctx.x87.aXMM[0]);
     3622                    if (cbDst < 16)
     3623                    {
     3624                        for (i = cbDst / 4; i < 4; i++)
     3625                            PtrField.pu32[i++] = 0;
     3626#ifdef BS3CG1_DEBUG_CTX_MOD
     3627                        BS3CG1_DPRINTF(("dbg:    --> cleared high %u bytes of XMM%u\n", 16 - cbDst, iReg));
     3628#endif
     3629                    }
     3630                    pThis->pExtCtx->Ctx.x.u.YmmHi.aYmmHi[iReg].au64[0] = 0;
     3631                    pThis->pExtCtx->Ctx.x.u.YmmHi.aYmmHi[iReg].au64[1] = 0;
     3632#ifdef BS3CG1_DEBUG_CTX_MOD
     3633                    BS3CG1_DPRINTF(("dbg:    --> cleared YMM%u_HI\n", iReg));
     3634#endif
     3635                }
    32733636            }
    32743637        }
    … …  
    34453808                                               pExpect->Ctx.x87.aXMM[i].au64[1],
    34463809                                               pExpect->Ctx.x87.aXMM[i].au64[0]);
     3810                if (pExpect->fXcr0Saved & XSAVE_C_YMM)
     3811                    for (i = 0; i < (ARCH_BITS == 64 ? 16 : 8); i++)
     3812                        if (   pResult->Ctx.x.u.YmmHi.aYmmHi[i].au64[0] != pExpect->Ctx.x.u.YmmHi.aYmmHi[i].au64[0]
     3813                            || pResult->Ctx.x.u.YmmHi.aYmmHi[i].au64[1] != pExpect->Ctx.x.u.YmmHi.aYmmHi[i].au64[1])
     3814                            fOkay = Bs3TestFailedF("YMM%u_HI: %#010RX64'%016RX64, expected %#010RX64'%08RX64", i,
     3815                                                   pResult->Ctx.x.u.YmmHi.aYmmHi[i].au64[1],
     3816                                                   pResult->Ctx.x.u.YmmHi.aYmmHi[i].au64[0],
     3817                                                   pExpect->Ctx.x.u.YmmHi.aYmmHi[i].au64[1],
     3818                                                   pExpect->Ctx.x.u.YmmHi.aYmmHi[i].au64[0]);
    34473819            }
    34483820            else
    … …  
    35713943        Bs3TestPrintf("xcr0=%RX64\n", pThis->pResultExtCtx->fXcr0Saved);
    35723944    Bs3TestPrintf("\n");
     3945ASMHalt();
    35733946    return false;
    35743947}
    … …  
    38074180        for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aXMM); i++)
    38084181        {
    3809             pExtCtx->Ctx.x87.aXMM[i].au16[0] = i;
    3810             pExtCtx->Ctx.x87.aXMM[i].au16[1] = i;
    3811             pExtCtx->Ctx.x87.aXMM[i].au16[2] = i;
    3812             pExtCtx->Ctx.x87.aXMM[i].au16[3] = i;
    3813             pExtCtx->Ctx.x87.aXMM[i].au16[4] = i;
    3814             pExtCtx->Ctx.x87.aXMM[i].au16[5] = i;
    3815             pExtCtx->Ctx.x87.aXMM[i].au16[6] = i;
    3816             pExtCtx->Ctx.x87.aXMM[i].au16[7] = i;
     4182            pExtCtx->Ctx.x87.aXMM[i].au16[0] = i | UINT16_C(0x8f00);
     4183            pExtCtx->Ctx.x87.aXMM[i].au16[1] = i | UINT16_C(0x8e00);
     4184            pExtCtx->Ctx.x87.aXMM[i].au16[2] = i | UINT16_C(0x8d00);
     4185            pExtCtx->Ctx.x87.aXMM[i].au16[3] = i | UINT16_C(0x8c00);
     4186            pExtCtx->Ctx.x87.aXMM[i].au16[4] = i | UINT16_C(0x8b00);
     4187            pExtCtx->Ctx.x87.aXMM[i].au16[5] = i | UINT16_C(0x8a00);
     4188            pExtCtx->Ctx.x87.aXMM[i].au16[6] = i | UINT16_C(0x8900);
     4189            pExtCtx->Ctx.x87.aXMM[i].au16[7] = i | UINT16_C(0x8800);
    38174190        }
    38184191        if (pExtCtx->fXcr0Nominal & XSAVE_C_YMM)
    3819             for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi); i++)
     4192            for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x.u.YmmHi.aYmmHi); i++)
    38204193            {
    3821                 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[0] = i << 8;
    3822                 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[1] = i << 8;
    3823                 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[2] = i << 8;
    3824                 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[3] = i << 8;
    3825                 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[4] = i << 8;
    3826                 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[5] = i << 8;
    3827                 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[6] = i << 8;
    3828                 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[7] = i << 8;
     4194                pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[0] = (i << 8) | (i << 12) | 0xff;
     4195                pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[1] = (i << 8) | (i << 12) | 0xfe;
     4196                pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[2] = (i << 8) | (i << 12) | 0xfd;
     4197                pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[3] = (i << 8) | (i << 12) | 0xfc;
     4198                pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[4] = (i << 8) | (i << 12) | 0xfb;
     4199                pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[5] = (i << 8) | (i << 12) | 0xfa;
     4200                pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[6] = (i << 8) | (i << 12) | 0xf9;
     4201                pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[7] = (i << 8) | (i << 12) | 0xf8;
    38294202            }
    38304203
    … …  
    40704443#if 0
    40714444    /* (for debugging) */
    4072     if (bMode != BS3_MODE_PP32)
     4445    if (bMode != BS3_MODE_PPV86)
    40734446        return BS3TESTDOMODE_SKIPPED;
    40744447#endif
    … …  
    40834456#if 0
    40844457    /* (for debugging) */
    4085     //if (bMode == BS3_MODE_PP32)
     4458    if (bMode == BS3_MODE_PPV86)
    40864459    {
    40874460        Bs3TestTerm();

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h

    r66815 r66886  
    141141    BS3CG1ENC_MODRM_Mq_WO_VqHi,
    142142
     143    BS3CG1ENC_VEX_MODRM_Vps_WO_Wps,
    143144    BS3CG1ENC_VEX_MODRM_Md_WO,
    144145
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