Changeset 7730 in vbox for trunk/src/VBox/VMM

Timestamp:

Apr 3, 2008 4:30:35 PM (17 years ago)

Author:

vboxsync

Message:

Added CPUMSet/GetGuestEFER.
Corrected NX bit handling.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• CPUMAllRegs.cpp (modified) (3 diffs)
• PGMAllBth.h (modified) (3 diffs)
• PGMAllGst.h (modified) (5 diffs)

trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

@@ -639 +639 @@
 }
 
+CPUMDECL(void) CPUMSetGuestEFER(PVM pVM, uint64_t val)
+{
+    pVM->cpum.s.Guest.msrEFER = val;
+}
 
 CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit)
@@ -686 +690 @@
     return pVM->cpum.s.Guest.ldtr;
 }
-
 
 CPUMDECL(uint32_t) CPUMGetGuestCR0(PVM pVM)
@@ -851 +854 @@
     }
     return VINF_SUCCESS;
+}
+
+CPUMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM)
+{
+    return pVM->cpum.s.Guest.msrEFER;
 }
 

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -1622 +1622 @@
 PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
 {
-    bool fWriteProtect   = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
-    bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
-    bool fWriteFault     = !!(uErr & X86_TRAP_PF_RW);
+    bool fWriteProtect      = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
+    bool fUserLevelFault    = !!(uErr & X86_TRAP_PF_US);
+    bool fWriteFault        = !!(uErr & X86_TRAP_PF_RW);
+# if PGM_WITH_NX(PGM_GST_TYPE)
+    bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
+# endif
 
     STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
@@ -1639 +1642 @@
     if (    (uErr & X86_TRAP_PF_RSVD)
         ||  !pPdpeSrc->n.u1Present
-        ||  ((uErr & X86_TRAP_PF_ID) &&  pPdpeSrc->n.u1NoExecute)
+# if PGM_WITH_NX(PGM_GST_TYPE)
+        ||  (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) &&  pPdpeSrc->n.u1NoExecute)
+# endif
         ||  (fWriteFault && !pPdpeSrc->n.u1Write && (fUserLevelFault || fWriteProtect))
         ||  (fUserLevelFault && !pPdpeSrc->n.u1User) )
@@ -1685 +1690 @@
     if (    (uErr & X86_TRAP_PF_RSVD)
         ||  !pPdeSrc->n.u1Present
-#  if PGM_WITH_NX(PGM_GST_TYPE)
-        ||  ((uErr & X86_TRAP_PF_ID) &&  pPdeSrc->n.u1NoExecute)
-#  endif
+# if PGM_WITH_NX(PGM_GST_TYPE)
+        ||  (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) &&  pPdeSrc->n.u1NoExecute)
+# endif
         ||  (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault || fWriteProtect))
         ||  (fUserLevelFault && !pPdeSrc->n.u1User) )

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -150 +150 @@
     return VINF_SUCCESS;
 
-#elif PGM_GST_TYPE == PGM_TYPE_32BIT \
-   || PGM_GST_TYPE == PGM_TYPE_PAE \
-   || PGM_GST_TYPE == PGM_TYPE_AMD64
-        
-#if PGM_GST_TYPE == PGM_TYPE_AMD64
+#elif PGM_GST_TYPE == PGM_TYPE_AMD64
     /* later */
+    /* check level 3 & 4 bits as well (r/w, u/s, nxe) */
     AssertFailed();
     return VERR_NOT_IMPLEMENTED;
-#endif
-
+
+#elif PGM_GST_TYPE == PGM_GST_32BIT || PGM_GST_TYPE == PGM_GST_PAE
 
     /*
      * Get the PDE.
      */
-#if PGM_GST_TYPE == PGM_TYPE_32BIT
+# if PGM_GST_TYPE == PGM_TYPE_32BIT
     const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
-#else /* PAE */
-    X86PDEPAE   Pde;
+# else /* PAE */
+    X86PDEPAE    Pde;
+    bool         fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
+
+    /* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
+     * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
+     */
     Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
-#endif
+# endif
 
     /*
@@ -203 +205 @@
 # if PGM_WITH_NX(PGM_GST_TYPE)
             /* The NX bit is determined by a bitwise OR between the PT and PD */
-            if (Pde.u & X86_PTE_PAE_NX)
-                *pfFlags |= X86_PTE_PAE_NX;
+            if (fNoExecuteBitValid)
+                *pFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);
 # endif
         }
@@ -216 +218 @@
          */
         if (pfFlags)
+        {
             *pfFlags = (Pde.u & ~(GST_PTE_PG_MASK | X86_PTE_PAT))
                      | ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
+# if PGM_WITH_NX(PGM_GST_TYPE)
+            /* The NX bit is determined by a bitwise OR between the PT and PD */
+            if (fNoExecuteBitValid)
+                *pfFlags |= (Pde.u & X86_PTE_PAE_NX);
+# endif
+        }
         if (pGCPhys)
             *pGCPhys = (Pde.u & GST_PDE_BIG_PG_MASK) | (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK)); /** @todo pse36 */
@@ -249 +258 @@
 #if PGM_GST_TYPE == PGM_TYPE_AMD64
     /* later */
+    /* check level 3 & 4 bits as well (r/w, u/s, nxe) */
     AssertFailed();
     return VERR_NOT_IMPLEMENTED;
@@ -261 +271 @@
         PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
 #else /* PAE */
+        /* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
+         * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
+         */
         PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
         Assert(pPde);