- Timestamp:
- Nov 19, 2019 11:07:48 AM (5 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/PC/DevDMA.cpp
r81984 r81985 49 49 #include <VBox/err.h> 50 50 51 #include <VBox/AssertGuest.h> 51 52 #include <VBox/log.h> 52 53 #include <iprt/assert.h> … … 110 111 uint8_t u8Mode; /* Channel mode. */ 111 112 uint8_t abPadding[7]; 112 } DMAChannel; 113 } DMAChannel, DMACHANNEL; 114 typedef DMACHANNEL *PDMACHANNEL; 113 115 114 116 /* State information for a DMA controller (DMA8 or DMA16). */ … … 143 145 PPDMDEVINSR3 pDevIns; /* Device instance. */ 144 146 R3PTRTYPE(PCPDMDMACHLP) pHlp; /* PDM DMA helpers. */ 147 STAMPROFILE StatRun; 145 148 } DMAState, DMASTATE; 146 149 /** Pointer to the shared DMA state information. */ … … 260 263 if (cb == 1) 261 264 { 262 DMAControl *dc = (DMAControl *)pvUser; 263 DMAChannel *ch; 264 int chidx, reg, is_count; 265 265 PDMACONTROLLER dc = (PDMACONTROLLER)pvUser; 266 unsigned const reg = (offPort >> dc->is16bit) & 0x0f; 267 unsigned const chidx = reg >> 1; 268 unsigned const is_count = reg & 1; 269 PDMACHANNEL ch = &RT_SAFE_SUBSCRIPT(dc->ChState, chidx); 266 270 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */ 267 reg = (offPort >> dc->is16bit) & 0x0f; 268 chidx = reg >> 1; 269 is_count = reg & 1; 270 ch = &dc->ChState[chidx]; 271 271 272 if (dmaReadBytePtr(dc)) 272 273 { … … 307 308 if (cb == 1) 308 309 { 309 DMAControl *dc = (DMAControl *)pvUser; 310 DMAChannel *ch; 311 int chidx, reg, val, dir; 312 int bptr; 313 314 reg = (offPort >> dc->is16bit) & 0x0f; 315 chidx = reg >> 1; 316 ch = &dc->ChState[chidx]; 317 318 dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1; 310 PDMACONTROLLER dc = (PDMACONTROLLER)pvUser; 311 unsigned const reg = (offPort >> dc->is16bit) & 0x0f; 312 unsigned const chidx = reg >> 1; 313 PDMACHANNEL ch = &RT_SAFE_SUBSCRIPT(dc->ChState, chidx); 314 int const dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1; 315 int val; 316 int bptr; 317 319 318 if (reg & 1) 320 319 val = ch->u16BaseCount - ch->u16CurCount; … … 341 340 if (cb == 1) 342 341 { 343 DMAControl *dc = (DMAControl *)pvUser;344 unsigned chidx = 0;342 PDMACONTROLLER dc = (PDMACONTROLLER)pvUser; 343 unsigned chidx = 0; 345 344 346 345 unsigned const reg = (offPort >> dc->is16bit) & 0x0f; … … 374 373 break; 375 374 case CTL_W_MODE: 376 { 377 int op, opmode; 378 379 chidx = u32 & 3; 380 op = (u32 >> 2) & 3; 381 opmode = (u32 >> 6) & 3; 382 Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n", 383 chidx, op, IS_MODE_AI(u32) ? "" : "no ", 384 IS_MODE_DEC(u32) ? "de" : "in", opmode)); 385 386 dc->ChState[chidx].u8Mode = u32; 387 break; 388 } 375 chidx = u32 & 3; 376 dc->ChState[chidx].u8Mode = u32; 377 Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n", 378 chidx, (u32 >> 2) & 3, IS_MODE_AI(u32) ? "" : "no ", IS_MODE_DEC(u32) ? "de" : "in", (u32 >> 6) & 3)); 379 break; 389 380 case CTL_W_CLRBPTR: 390 381 dc->fHiByte = false; … … 400 391 break; 401 392 default: 402 A ssert(0);393 ASSERT_GUEST_MSG_FAILED(("reg=%u\n", reg)); 403 394 break; 404 395 } … … 422 413 if (cb == 1) 423 414 { 424 DMAControl *dc = (DMAControl *)pvUser;425 uint8_t val = 0;415 PDMACONTROLLER dc = (PDMACONTROLLER)pvUser; 416 uint8_t val = 0; 426 417 427 418 unsigned const reg = (offPort >> dc->is16bit) & 0x0f; … … 441 432 break; 442 433 case CTL_R_MODE: 443 val = dc->ChState[dc->u8ModeCtr].u8Mode | 3;434 val = RT_SAFE_SUBSCRIPT(dc->ChState, dc->u8ModeCtr).u8Mode | 3; 444 435 dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3; 445 436 break; … … 483 474 { 484 475 RT_NOREF(pDevIns); 485 DMAControl *dc = (DMAControl *)pvUser;486 int reg;476 PDMACONTROLLER dc = (PDMACONTROLLER)pvUser; 477 int reg; 487 478 488 479 if (cb == 1) … … 513 504 { 514 505 RT_NOREF(pDevIns); 515 DMAControl *dc = (DMAControl *)pvUser;516 intreg;506 PDMACONTROLLER dc = (PDMACONTROLLER)pvUser; 507 unsigned reg; 517 508 518 509 if (cb == 1) … … 553 544 if (cb == 1) 554 545 { 555 DMAControl *dc = (DMAControl *)pvUser; 556 int reg; 557 558 reg = offPort & 7; 546 PDMACONTROLLER dc = (PDMACONTROLLER)pvUser; 547 unsigned const reg = offPort & 7; 548 559 549 *pu32 = dc->au8PageHi[reg]; 560 550 Log2(("Read %#x to from high page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg))); … … 573 563 if (cb == 1) 574 564 { 575 DMAControl *dc = (DMAControl *)pvUser;576 int reg;565 PDMACONTROLLER dc = (PDMACONTROLLER)pvUser; 566 unsigned const reg = offPort & 7; 577 567 578 568 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */ 579 reg = offPort & 7;580 569 dc->au8PageHi[reg] = u32; 581 570 Log2(("Wrote %#x to high page register %#x (channel %d)\n", u32, offPort, DMAPG2CX(reg))); … … 602 591 opmode = (ch->u8Mode >> 6) & 3; 603 592 604 Log3(("DMA address %screment, mode %d\n", 605 IS_MODE_DEC(ch->u8Mode) ? "de" : "in", 606 ch->u8Mode >> 6)); 593 Log3(("DMA address %screment, mode %d\n", IS_MODE_DEC(ch->u8Mode) ? "de" : "in", ch->u8Mode >> 6)); 607 594 608 595 /* Addresses and counts are shifted for 16-bit channels. */ … … 638 625 DMAControl *dc; 639 626 int ctlidx, chidx, mask; 627 STAM_PROFILE_START(&pThis->StatRun, a); 640 628 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED); 641 629 642 630 /* Run all controllers and channels. */ 643 for (ctlidx = 0; ctlidx < 2; ++ctlidx)631 for (ctlidx = 0; ctlidx < RT_ELEMENTS(pThis->DMAC); ++ctlidx) 644 632 { 645 633 dc = &pThis->DMAC[ctlidx]; … … 658 646 659 647 PDMCritSectLeave(pDevIns->pCritSectRoR3); 648 STAM_PROFILE_STOP(&pThis->StatRun, a); 660 649 return 0; 661 650 } … … 1043 1032 AssertRCReturn(rc, rc); 1044 1033 1034 /* 1035 * Statistics. 1036 */ 1037 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRun, STAMTYPE_PROFILE, "DmaRun", STAMUNIT_TICKS_PER_CALL, "Profiling dmaRun()."); 1038 1045 1039 return VINF_SUCCESS; 1046 1040 } … … 1090 1084 /* .uReserved0 = */ 0, 1091 1085 /* .szName = */ "8237A", 1092 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ ,1086 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE, 1093 1087 /* .fClass = */ PDM_DEVREG_CLASS_DMA, 1094 1088 /* .cMaxInstances = */ 1,
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