Changeset 84132 in vbox for trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp

Timestamp:

May 2, 2020 6:26:46 PM (5 years ago)

Author:

vboxsync

Message:

AMD IOMMU: bugref:9654 Exclusion range.

File:

• trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp (modified) (8 diffs)

trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp

@@ -580 +580 @@
 #define IOMMU_DEV_TAB_ENTRY_QWORD_3_VALID_MASK      UINT64_C(0xffc0000000000000)
 /** Pointer to a device table entry. */
-typedef DEV_TAB_ENTRY_T *PDEVTAB_ENTRY_T;
+typedef DEV_TAB_ENTRY_T *PDEV_TAB_ENTRY_T;
 /** Pointer to a const device table entry. */
 typedef DEV_TAB_ENTRY_T const *PCDEV_TAB_ENTRY_T;
@@ -1310 +1310 @@
     struct
     {
-        RT_GCC_EXTENSION uint64_t   u12Rsvd0 : 12;      /**< Bits 11:0  - Reserved. */
-        RT_GCC_EXTENSION uint64_t   u40ExclLimit : 40;  /**< Bits 51:12 - Exclusion Range Limit. */
+        RT_GCC_EXTENSION uint64_t   u52ExclLimit : 52;  /**< Bits 51:0 - Exclusion Range Limit (last 12 bits are treated as 1s). */
         RT_GCC_EXTENSION uint64_t   u12Rsvd1 : 12;      /**< Bits 63:52 - Reserved. */
     } n;
@@ -1318 +1317 @@
 } IOMMU_EXCL_RANGE_LIMIT_T;
 AssertCompileSize(IOMMU_EXCL_RANGE_LIMIT_T, 8);
-#define IOMMU_EXCL_RANGE_LIMIT_VALID_MASK   UINT64_C(0x000ffffffffff000)
+#define IOMMU_EXCL_RANGE_LIMIT_VALID_MASK   UINT64_C(0x000fffffffffffff)
 
 /**
@@ -2548 +2547 @@
 {
     RT_NOREF(pDevIns, iReg);
-    pThis->ExclRangeLimit.u64 = u64Value & IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
+    u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
+    u64Value |= UINT64_C(0xfff);
+    pThis->ExclRangeLimit.u64 = u64Value;
     return VINF_SUCCESS;
 }
@@ -3405 +3406 @@
 
 
+
+/**
+ * Returns whether the device virtual address is allowed to be excluded from
+ * translation and permission checks.
+ *
+ * @returns @c true if the DVA is excluded, @c false otherwise.
+ * @param   pThis           The IOMMU device state.
+ * @param   pDevTabEntry    The device table entry.
+ * @param   uDva            The device virtual address.
+ */
+static bool iommuAmdIsDvaSubjectToExclRange(PCIOMMU pThis, PCDEV_TAB_ENTRY_T pDevTabEntry, uint64_t uDva)
+{
+    /* Check if the exclusion range is enabled. */
+    if (pThis->ExclRangeBaseAddr.n.u1ExclEnable)
+    {
+        /* Check if the device virtual address falls within the exclusion range. */
+        uint64_t const uDvaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
+        uint64_t const uDvaExclLast  = pThis->ExclRangeLimit.n.u52ExclLimit;
+        if (uDvaExclLast - uDva >= uDvaExclFirst)
+        {
+            /* Check if device access to addresses in the exclusion can be forwarded untranslated. */
+            if (    pThis->ExclRangeBaseAddr.n.u1AllowAll
+                ||  pDevTabEntry->n.u1AllowExclusion)
+                return true;
+        }
+    }
+    return false;
+}
+
+
 /**
  * Reads a device table entry from guest memory given the device ID.
@@ -3416 +3447 @@
  * @thread  Any.
  */
-static int iommuAmdReadDevTabEntry(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, DEV_TAB_ENTRY_T *pDevTabEntry)
+static int iommuAmdReadDevTabEntry(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDEV_TAB_ENTRY_T pDevTabEntry)
 {
     PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
@@ -3490 +3521 @@
                 }
 
-                /** @todo IOMMU: Traverse the I/O page table and translate. */
-                return VERR_NOT_IMPLEMENTED;
+                /* Check if the exclusion range is active. */
+                if (!iommuAmdIsDvaSubjectToExclRange(pThis, &DevTabEntry, uDva))
+                {
+                    /** @todo IOMMU: Traverse the I/O page table and translate. */
+                    return VERR_NOT_IMPLEMENTED;
+                }
             }
         }
@@ -3774 +3809 @@
         pHlp->pfnPrintf(pHlp, "  Exclusion Range Limit                   = %#RX64\n", ExclRangeLimit.u64);
         if (fVerbose)
-            pHlp->pfnPrintf(pHlp, "    Range limit                             = %#RX64\n", ExclRangeLimit.n.u40ExclLimit);
+            pHlp->pfnPrintf(pHlp, "    Range limit                             = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
     }
     /* Extended Feature Register. */