VirtualBox

Ignore:
Timestamp:
Sep 2, 2020 11:15:07 AM (4 years ago)
Author:
vboxsync
Message:

AMD IOMMU: bugref:9654 Fix crash in iommuAmdR3DbgInfo, some comment and nits.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp

    r85988 r85995  
    31323132
    31333133    LogFlowFunc(("pThis=%p pszArgs=%s\n", pThis, pszArgs));
    3134     bool const fVerbose = !strncmp(pszArgs, RT_STR_TUPLE("verbose")) ? true : false;
     3134    bool fVerbose;
     3135    if (   pszArgs
     3136        && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
     3137        fVerbose = true;
     3138    else
     3139        fVerbose = false;
    31353140
    31363141    pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
    … …  
    31393144    {
    31403145        DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
    3141         pHlp->pfnPrintf(pHlp, "  Device Table BAR [%u]                   = %#RX64\n", i, DevTabBar.u64);
     3146        pHlp->pfnPrintf(pHlp, "  Device Table BAR %u                      = %#RX64\n", i, DevTabBar.u64);
    31423147        if (fVerbose)
    31433148        {
    … …  
    31533158        uint32_t const cEntries    = iommuAmdGetBufMaxEntries(uEncodedLen);
    31543159        uint32_t const cbBuffer    = iommuAmdGetTotalBufLength(uEncodedLen);
    3155         pHlp->pfnPrintf(pHlp, "  Command buffer BAR                      = %#RX64\n", CmdBufBar.u64);
     3160        pHlp->pfnPrintf(pHlp, "  Command Buffer BAR                      = %#RX64\n", CmdBufBar.u64);
    31563161        if (fVerbose)
    31573162        {
    … …  
    31673172        uint32_t const cEntries    = iommuAmdGetBufMaxEntries(uEncodedLen);
    31683173        uint32_t const cbBuffer    = iommuAmdGetTotalBufLength(uEncodedLen);
    3169         pHlp->pfnPrintf(pHlp, "  Event log BAR                           = %#RX64\n", EvtLogBar.u64);
     3174        pHlp->pfnPrintf(pHlp, "  Event Log BAR                           = %#RX64\n", EvtLogBar.u64);
    31703175        if (fVerbose)
    31713176        {
    … …  
    32443249        IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
    32453250        pHlp->pfnPrintf(pHlp, "  Extended Feature Register               = %#RX64\n", ExtFeat.u64);
    3246         pHlp->pfnPrintf(pHlp, "    Prefetch support                        = %RTbool\n", ExtFeat.n.u1PrefetchSup);
    32473251        if (fVerbose)
    32483252        {
     3253            pHlp->pfnPrintf(pHlp, "    Prefetch support                        = %RTbool\n", ExtFeat.n.u1PrefetchSup);
    32493254            pHlp->pfnPrintf(pHlp, "    PPR support                             = %RTbool\n",  ExtFeat.n.u1PprSup);
    32503255            pHlp->pfnPrintf(pHlp, "    x2APIC support                          = %RTbool\n",  ExtFeat.n.u1X2ApicSup);
    … …  
    33083313    }
    33093314    /* Hardware Event (Lo) Register. */
    3310     pHlp->pfnPrintf(pHlp, "  Hardware Event (Lo)                         = %#RX64\n", pThis->HwEvtLo);
     3315    pHlp->pfnPrintf(pHlp, "  Hardware Event (Lo)                     = %#RX64\n", pThis->HwEvtLo);
    33113316    /* Hardware Event Status. */
    33123317    {
    … …  
    33933398    {
    33943399        DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
    3395         pHlp->pfnPrintf(pHlp, "  Device-specific Control                 = %#RX64\n",   DevSpecificStatus.u64);
     3400        pHlp->pfnPrintf(pHlp, "  Device-specific Status                  = %#RX64\n",   DevSpecificStatus.u64);
    33963401        if (fVerbose)
    33973402        {
    … …  
    35443549    }
    35453550    /* Reserved Register. */
    3546     pHlp->pfnPrintf(pHlp, "  Reserved Register                           = %#RX64\n", pThis->RsvdReg);
     3551    pHlp->pfnPrintf(pHlp, "  Reserved Register                       = %#RX64\n", pThis->RsvdReg);
    35473552    /* Command Buffer Head Pointer Register. */
    35483553    {
    35493554        CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
    3550         pHlp->pfnPrintf(pHlp, "  Command Buffer Head Pointer             = %#RX64\n", CmdBufHeadPtr.u64);
    3551         pHlp->pfnPrintf(pHlp, "    Pointer                                 = %#x\n",  CmdBufHeadPtr.n.off);
     3555        pHlp->pfnPrintf(pHlp, "  Command Buffer Head Pointer             = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
     3556                        CmdBufHeadPtr.n.off);
    35523557    }
    35533558    /* Command Buffer Tail Pointer Register. */
    35543559    {
    35553560        CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
    3556         pHlp->pfnPrintf(pHlp, "  Command Buffer Tail Pointer             = %#RX64\n", CmdBufTailPtr.u64);
    3557         pHlp->pfnPrintf(pHlp, "    Pointer                                 = %#x\n",  CmdBufTailPtr.n.off);
     3561        pHlp->pfnPrintf(pHlp, "  Command Buffer Tail Pointer             = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
     3562                        CmdBufTailPtr.n.off);
    35583563    }
    35593564    /* Event Log Head Pointer Register. */
    35603565    {
    35613566        EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
    3562         pHlp->pfnPrintf(pHlp, "  Event Log Head Pointer                  = %#RX64\n", EvtLogHeadPtr.u64);
    3563         pHlp->pfnPrintf(pHlp, "    Pointer                                 = %#x\n",  EvtLogHeadPtr.n.off);
     3567        pHlp->pfnPrintf(pHlp, "  Event Log Head Pointer                  = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
     3568                        EvtLogHeadPtr.n.off);
    35643569    }
    35653570    /* Event Log Tail Pointer Register. */
    35663571    {
    35673572        EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
    3568         pHlp->pfnPrintf(pHlp, "  Event Log Head Pointer                  = %#RX64\n", EvtLogTailPtr.u64);
    3569         pHlp->pfnPrintf(pHlp, "    Pointer                                 = %#x\n",  EvtLogTailPtr.n.off);
     3573        pHlp->pfnPrintf(pHlp, "  Event Log Head Pointer                  = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
     3574                        EvtLogTailPtr.n.off);
    35703575    }
    35713576    /* Status Register. */
    … …  
    35963601    {
    35973602        PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
    3598         pHlp->pfnPrintf(pHlp, "  PPR Log Head Pointer                    = %#RX64\n", PprLogHeadPtr.u64);
    3599         pHlp->pfnPrintf(pHlp, "    Pointer                                 = %#x\n",  PprLogHeadPtr.n.off);
     3603        pHlp->pfnPrintf(pHlp, "  PPR Log Head Pointer                    = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
     3604                        PprLogHeadPtr.n.off);
    36003605    }
    36013606    /* PPR Log Tail Pointer. */
    36023607    {
    36033608        PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
    3604         pHlp->pfnPrintf(pHlp, "  PPR Log Tail Pointer                    = %#RX64\n", PprLogTailPtr.u64);
    3605         pHlp->pfnPrintf(pHlp, "    Pointer                                 = %#x\n",  PprLogTailPtr.n.off);
     3609        pHlp->pfnPrintf(pHlp, "  PPR Log Tail Pointer                    = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
     3610                        PprLogTailPtr.n.off);
    36063611    }
    36073612    /* Guest Virtual-APIC Log Head Pointer. */
    36083613    {
    36093614        GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
    3610         pHlp->pfnPrintf(pHlp, "  Guest Virtual-APIC Log Head Pointer     = %#RX64\n", GALogHeadPtr.u64);
    3611         pHlp->pfnPrintf(pHlp, "    Pointer                                 = %#x\n",  GALogHeadPtr.n.u12GALogPtr);
     3615        pHlp->pfnPrintf(pHlp, "  Guest Virtual-APIC Log Head Pointer     = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
     3616                        GALogHeadPtr.n.u12GALogPtr);
    36123617    }
    36133618    /* Guest Virtual-APIC Log Tail Pointer. */
    36143619    {
    36153620        GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
    3616         pHlp->pfnPrintf(pHlp, "  Guest Virtual-APIC Log Tail Pointer     = %#RX64\n", GALogTailPtr.u64);
    3617         pHlp->pfnPrintf(pHlp, "    Pointer                                 = %#x\n",  GALogTailPtr.n.u12GALogPtr);
     3621        pHlp->pfnPrintf(pHlp, "  Guest Virtual-APIC Log Tail Pointer     = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
     3622                        GALogTailPtr.n.u12GALogPtr);
    36183623    }
    36193624    /* PPR Log B Head Pointer. */
    36203625    {
    36213626        PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
    3622         pHlp->pfnPrintf(pHlp, "  PPR Log B Head Pointer                  = %#RX64\n", PprLogBHeadPtr.u64);
    3623         pHlp->pfnPrintf(pHlp, "    Pointer                                 = %#x\n",  PprLogBHeadPtr.n.off);
     3627        pHlp->pfnPrintf(pHlp, "  PPR Log B Head Pointer                  = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
     3628                        PprLogBHeadPtr.n.off);
    36243629    }
    36253630    /* PPR Log B Tail Pointer. */
    36263631    {
    36273632        PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
    3628         pHlp->pfnPrintf(pHlp, "  PPR Log B Tail Pointer                  = %#RX64\n", PprLogBTailPtr.u64);
    3629         pHlp->pfnPrintf(pHlp, "    Pointer                                 = %#x\n",  PprLogBTailPtr.n.off);
     3633        pHlp->pfnPrintf(pHlp, "  PPR Log B Tail Pointer                  = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
     3634                        PprLogBTailPtr.n.off);
    36303635    }
    36313636    /* Event Log B Head Pointer. */
    36323637    {
    36333638        EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
    3634         pHlp->pfnPrintf(pHlp, "  Event Log B Head Pointer                = %#RX64\n", EvtLogBHeadPtr.u64);
    3635         pHlp->pfnPrintf(pHlp, "    Pointer                                 = %#x\n",  EvtLogBHeadPtr.n.off);
     3639        pHlp->pfnPrintf(pHlp, "  Event Log B Head Pointer                = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
     3640                        EvtLogBHeadPtr.n.off);
    36363641    }
    36373642    /* Event Log B Tail Pointer. */
    36383643    {
    36393644        EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
    3640         pHlp->pfnPrintf(pHlp, "  Event Log B Tail Pointer                = %#RX64\n", EvtLogBTailPtr.u64);
    3641         pHlp->pfnPrintf(pHlp, "    Pointer                                 = %#x\n",  EvtLogBTailPtr.n.off);
     3645        pHlp->pfnPrintf(pHlp, "  Event Log B Tail Pointer                = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
     3646                        EvtLogBTailPtr.n.off);
    36423647    }
    36433648    /* PPR Log Auto Response Register. */
    … …  
    38603865    PDMPciDevSetVendorId(pPciDev,          IOMMU_PCI_VENDOR_ID);       /* AMD */
    38613866    PDMPciDevSetDeviceId(pPciDev,          IOMMU_PCI_DEVICE_ID);       /* VirtualBox IOMMU device */
    3862     PDMPciDevSetCommand(pPciDev,           VBOX_PCI_COMMAND_MASTER);   /* Enable bus master (as we write to main memory). */
    3863     PDMPciDevSetStatus(pPciDev,            VBOX_PCI_STATUS_CAP_LIST);  /* Status - CapList supported */
     3867    PDMPciDevSetCommand(pPciDev,           VBOX_PCI_COMMAND_MASTER);   /* Enable bus master (as we write to main memory) */
     3868    PDMPciDevSetStatus(pPciDev,            VBOX_PCI_STATUS_CAP_LIST);  /* Capability list supported */
    38643869    PDMPciDevSetRevisionId(pPciDev,        IOMMU_PCI_REVISION_ID);     /* VirtualBox specific device implementation revision */
    38653870    PDMPciDevSetClassBase(pPciDev,         VBOX_PCI_CLASS_SYSTEM);     /* System Base Peripheral */
    38663871    PDMPciDevSetClassSub(pPciDev,          VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
    3867     PDMPciDevSetClassProg(pPciDev,         0x00);                      /* IOMMU Programming interface */
    3868     PDMPciDevSetHeaderType(pPciDev,        0x00);                      /* Single function, type 0. */
     3872    PDMPciDevSetClassProg(pPciDev,         0x0);                       /* IOMMU Programming interface */
     3873    PDMPciDevSetHeaderType(pPciDev,        0x0);                       /* Single function, type 0 */
    38693874    PDMPciDevSetSubSystemId(pPciDev,       IOMMU_PCI_DEVICE_ID);       /* AMD */
    38703875    PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID);       /* VirtualBox IOMMU device */
    3871     PDMPciDevSetCapabilityList(pPciDev,    IOMMU_PCI_OFF_CAP_HDR);     /* Offset into capability registers. */
    3872     PDMPciDevSetInterruptPin(pPciDev,      0x01);                      /* INTA#. */
    3873     PDMPciDevSetInterruptLine(pPciDev,     0x00);                      /* For software compatibility; no effect on hardware. */
     3876    PDMPciDevSetCapabilityList(pPciDev,    IOMMU_PCI_OFF_CAP_HDR);     /* Offset into capability registers */
     3877    PDMPciDevSetInterruptPin(pPciDev,      0x1);                       /* INTA#. */
     3878    PDMPciDevSetInterruptLine(pPciDev,     0x0);                       /* For software compatibility; no effect on hardware */
    38743879
    38753880    /* Capability Header. */
    … …  
    38863891                      | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT,   0x1));   /* RO - Misc. Information Register support */
    38873892
    3888     /* Base Address Low Register. */
    3889     PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0);   /* RW - Base address (Lo) and enable bit. */
    3890 
    3891     /* Base Address High Register. */
     3893    /* Base Address Register. */
     3894    PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0);   /* RW - Base address (Lo) and enable bit */
    38923895    PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0);   /* RW - Base address (Hi) */
    38933896
    38943897    /* IOMMU Range Register. */
    3895     PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0);          /* RW - Range register (implemented as RO by us). */
     3898    PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0);          /* RW - Range register (implemented as RO by us) */
    38963899
    38973900    /* Misc. Information Register. */
    … …  
    39183921#if 0
    39193922    /* MSI Address Lo. */
    3920     PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0);         /* RW - MSI message address (Lo). */
     3923    PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0);         /* RW - MSI message address (Lo) */
    39213924    /* MSI Address Hi. */
    3922     PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0);         /* RW - MSI message address (Hi). */
     3925    PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0);         /* RW - MSI message address (Hi) */
    39233926    /* MSI Data. */
    3924     PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0);            /* RW - MSI data. */
     3927    PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0);            /* RW - MSI data */
    39253928#endif
    39263929
    … …  
    40134016    AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
    40144017    pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
    4015     pThis->ExtFeat.n.u2GstAddrTranslateSize  = 0;   /* Requires GstTranslateSup. */
    4016     pThis->ExtFeat.n.u2GstCr3RootTblLevel    = 0;   /* Requires GstTranslateSup. */
     4018    pThis->ExtFeat.n.u2GstAddrTranslateSize  = 0;   /* Requires GstTranslateSup */
     4019    pThis->ExtFeat.n.u2GstCr3RootTblLevel    = 0;   /* Requires GstTranslateSup */
    40174020    pThis->ExtFeat.n.u2SmiFilterSup          = 0;
    40184021    pThis->ExtFeat.n.u3SmiFilterCount        = 0;
    … …  
    40204023    pThis->ExtFeat.n.u2DualPprLogSup         = 0;
    40214024    pThis->ExtFeat.n.u2DualEvtLogSup         = 0;
    4022     pThis->ExtFeat.n.u5MaxPasidSup           = 0;   /* Requires GstTranslateSup. */
     4025    pThis->ExtFeat.n.u5MaxPasidSup           = 0;   /* Requires GstTranslateSup */
    40234026    pThis->ExtFeat.n.u1UserSupervisorSup     = 0;
    40244027    AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
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