VirtualBox

Changeset 89620 in vbox


Ignore:
Timestamp:
Jun 11, 2021 8:51:10 AM (4 years ago)
Author:
vboxsync
Message:

Intel IOMMU: bugref:9967 Allow PDMIoApicSetEoi operation to be queued to ring-3 if I/O APIC isn't available in R0.
This key change is taking the PDM lock such that it doesn't fail (VINF_SUCCESS instead of VINF_IOM_R3_MMIO_WRITE for rcBusy, which wouldn't have worked anyway when called via APICHvSetEoi for instance).
Also cleaned up the prototype of PDMIoApicSendMsi a bit (use PVMCC instead of PPDMDEVINS).

Location:
trunk
Files:
9 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/pdmapi.h

    r89600 r89620  
    5454VMM_INT_DECL(bool)      PDMHasApic(PVM pVM);
    5555VMM_INT_DECL(int)       PDMIoApicSetIrq(PVM pVM, PCIBDF uBusDevFn, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc);
    56 VMM_INT_DECL(VBOXSTRICTRC) PDMIoApicBroadcastEoi(PVM pVM, uint8_t uVector);
    57 VMM_INT_DECL(void)      PDMIoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc);
     56VMM_INT_DECL(void)      PDMIoApicBroadcastEoi(PVMCC pVM, uint8_t uVector);
     57VMM_INT_DECL(void)      PDMIoApicSendMsi(PVMCC pVM, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc);
    5858VMM_INT_DECL(int)       PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys);
    5959VMM_INT_DECL(bool)      PDMVmmDevHeapIsEnabled(PVM pVM);

  • trunk/include/VBox/vmm/pdmdev.h

    r89200 r89620  
    18691869     * Set the EOI for an interrupt vector.
    18701870     *
    1871      * @returns Strict VBox status code - only the following informational status codes:
    1872      * @retval  VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.
    1873      * @retval  VINF_SUCCESS
    1874      *
    18751871     * @param   pDevIns         Device instance of the I/O APIC.
    18761872     * @param   u8Vector        The vector.
    … …  
    18791875     *          Actually, as per 2018-07-21 this isn't true (bird).
    18801876     */
    1881     DECLCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
     1877    DECLCALLBACKMEMBER(void, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
    18821878
    18831879    /** Just a safety precaution. */
    … …  
    18881884
    18891885/** Current PDMAPICREG version number. */
    1890 #define PDM_IOAPICREG_VERSION                   PDM_VERSION_MAKE(0xfff2, 7, 0)
     1886#define PDM_IOAPICREG_VERSION                   PDM_VERSION_MAKE(0xfff2, 8, 0)
    18911887
    18921888

  • trunk/src/VBox/Devices/PC/DevIoApic.cpp

    r89098 r89620  
    313313    /** Number of IOMMU denied or failed MSIs. */
    314314    STAMCOUNTER             StatIommuDiscardedMsi;
    315     /** Number of returns to ring-3 due to EOI broadcast lock contention. */
    316     STAMCOUNTER             StatEoiContention;
    317315    /** Number of returns to ring-3 due to Set RTE lock contention. */
    318316    STAMCOUNTER             StatSetRteContention;
    … …  
    845843 * @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
    846844 */
    847 static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
     845static DECLCALLBACK(void) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
    848846{
    849847    PIOAPIC   pThis   = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
    850848    PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
     849
     850    LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
    851851    STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
    852     LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
    853852
    854853    bool fRemoteIrrCleared = false;
    855     VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
    856     if (rc == VINF_SUCCESS)
    857     {
    858         for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
     854    int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
     855    AssertRC(rc);
     856
     857    for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
     858    {
     859        uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
     860        if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
    859861        {
    860             uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
    861             if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
    862             {
    863862#ifdef DEBUG_ramshankar
    864                 /* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
    865                 Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
     863            /* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
     864            Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
    866865#endif
    867                 pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
    868                 fRemoteIrrCleared = true;
    869                 STAM_COUNTER_INC(&pThis->StatEoiReceived);
    870                 Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
    871 
    872                 /*
    873                  * Signal the next pending interrupt for this RTE.
    874                  */
    875                 uint32_t const uPinMask = UINT32_C(1) << idxRte;
    876                 if (pThis->uIrr & uPinMask)
    877                     ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
    878             }
     866            pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
     867            fRemoteIrrCleared = true;
     868            STAM_COUNTER_INC(&pThis->StatEoiReceived);
     869            Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
     870
     871            /*
     872             * Signal the next pending interrupt for this RTE.
     873             */
     874            uint32_t const uPinMask = UINT32_C(1) << idxRte;
     875            if (pThis->uIrr & uPinMask)
     876                ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
    879877        }
    880 
    881         IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
     878    }
     879
     880    IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
     881
    882882#ifndef VBOX_WITH_IOMMU_AMD
    883         AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
     883    AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
    884884#endif
    885     }
    886     else
    887         STAM_COUNTER_INC(&pThis->StatEoiContention);
    888 
    889     return rc;
    890885}
    891886
    … …  
    11191114        case IOAPIC_DIRECT_OFF_EOI:
    11201115            if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
    1121                 rc = ioapicSetEoi(pDevIns, uValue);
     1116                ioapicSetEoi(pDevIns, uValue);
    11221117            else
    11231118                Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
    … …  
    16681663    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedMsi,  STAMTYPE_COUNTER, "Iommu/DiscardedMsi",  STAMUNIT_OCCURENCES, "Number of MSIs discarded by the IOMMU.");
    16691664
    1670     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention,    STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
    16711665    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
    16721666

  • trunk/src/VBox/VMM/VMMAll/APICAll.cpp

    r88670 r89620  
    12331233 * @param   pVCpu                   The cross context virtual CPU structure.
    12341234 * @param   uEoi                    The EOI value.
    1235  * @param   rcBusy                  The busy return code when the write cannot
    1236  *                                  be completed successfully in this context.
    12371235 * @param   fForceX2ApicBehaviour   Pretend the APIC is in x2APIC mode during
    12381236 *                                  this write.
    12391237 */
    1240 static VBOXSTRICTRC apicSetEoi(PVMCPUCC pVCpu, uint32_t uEoi, int rcBusy, bool fForceX2ApicBehaviour)
     1238static VBOXSTRICTRC apicSetEoi(PVMCPUCC pVCpu, uint32_t uEoi, bool fForceX2ApicBehaviour)
    12411239{
    12421240    VMCPU_ASSERT_EMT(pVCpu);
    … …  
    12661264        if (fLevelTriggered)
    12671265        {
    1268             VBOXSTRICTRC rc = PDMIoApicBroadcastEoi(pVCpu->CTX_SUFF(pVM), uVector);
    1269             if (rc == VINF_SUCCESS)
    1270             { /* likely */ }
    1271             else
    1272                 return rcBusy;
     1266            PDMIoApicBroadcastEoi(pVCpu->CTX_SUFF(pVM), uVector);
    12731267
    12741268            /*
    … …  
    17891783        case XAPIC_OFF_EOI:
    17901784        {
    1791             rcStrict = apicSetEoi(pVCpu, uValue, VINF_IOM_R3_MMIO_WRITE, false /* fForceX2ApicBehaviour */);
     1785            rcStrict = apicSetEoi(pVCpu, uValue, false /* fForceX2ApicBehaviour */);
    17921786            break;
    17931787        }
    … …  
    21352129            case MSR_IA32_X2APIC_EOI:
    21362130            {
    2137                 rcStrict = apicSetEoi(pVCpu, u32Value, VINF_CPUM_R3_MSR_WRITE, false /* fForceX2ApicBehaviour */);
     2131                rcStrict = apicSetEoi(pVCpu, u32Value, false /* fForceX2ApicBehaviour */);
    21382132                break;
    21392133            }
    … …  
    35033497    Assert(pVCpu);
    35043498    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
    3505     return apicSetEoi(pVCpu, uEoi, VINF_CPUM_R3_MSR_WRITE, true /* fForceX2ApicBehaviour */);
     3499    return apicSetEoi(pVCpu, uEoi, true /* fForceX2ApicBehaviour */);
    35063500}
    35073501

  • trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

    r89602 r89620  
    191191
    192192/**
    193  * Broadcasts an EOI to the I/O APICs.
    194  *
    195  * @returns Strict VBox status code - only the following informational status codes:
    196  * @retval  VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.
    197  * @retval  VINF_SUCCESS
    198  *
    199  * @param   pVM             The cross context VM structure.
    200  * @param   uVector         The interrupt vector corresponding to the EOI.
    201  */
    202 VMM_INT_DECL(VBOXSTRICTRC) PDMIoApicBroadcastEoi(PVM pVM, uint8_t uVector)
    203 {
    204     /* At present, we support only a maximum of one I/O APIC per-VM. If we ever implement having
    205        multiple I/O APICs per-VM, we'll have to broadcast this EOI to all of the I/O APICs. */
    206     if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
    207     {
    208         Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetEoi));
    209         return pVM->pdm.s.IoApic.CTX_SUFF(pfnSetEoi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uVector);
    210     }
    211 
    212     /* We shouldn't return failure if no I/O APIC is present. */
    213     return VINF_SUCCESS;
     193 * Broadcasts an EOI to the I/O APIC(s).
     194 *
     195 * @param   pVM         The cross context VM structure.
     196 * @param   uVector     The interrupt vector corresponding to the EOI.
     197 */
     198VMM_INT_DECL(void) PDMIoApicBroadcastEoi(PVMCC pVM, uint8_t uVector)
     199{
     200    /*
     201     * At present, we support only a maximum of one I/O APIC per-VM. If we ever implement having
     202     * multiple I/O APICs per-VM, we'll have to broadcast this EOI to all of the I/O APICs.
     203     */
     204    PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
     205#ifdef IN_RING0
     206    if (pIoApic->pDevInsR0)
     207    {
     208        Assert(pIoApic->pfnSetEoiR0);
     209        pIoApic->pfnSetEoiR0(pIoApic->pDevInsR0, uVector);
     210    }
     211    else if (pIoApic->pDevInsR3)
     212    {
     213        /* Queue for ring-3 execution. */
     214        PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
     215        if (pTask)
     216        {
     217            pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_EOI;
     218            pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
     219            pTask->u.IoApicSetEoi.uVector = uVector;
     220            PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
     221        }
     222        else
     223            AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
     224    }
     225#else
     226    if (pIoApic->pDevInsR3)
     227    {
     228        Assert(pIoApic->pfnSetEoiR3);
     229        pIoApic->pfnSetEoiR3(pIoApic->pDevInsR3, uVector);
     230    }
     231#endif
    214232}
    215233
    … …  
    218236 * Send a MSI to an I/O APIC.
    219237 *
    220  * @param   pDevIns     The PCI device instance.
     238 * @param   pVM         The cross context VM structure.
    221239 * @param   uBusDevFn   The bus:device:function of the device initiating the MSI.
    222  *                      Cannot be NIL_PCIBDF.
    223240 * @param   pMsi        The MSI to send.
    224241 * @param   uTagSrc     The IRQ tag and source tracer ID.
    225242 */
    226 VMM_INT_DECL(void) PDMIoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
    227 {
     243VMM_INT_DECL(void) PDMIoApicSendMsi(PVMCC pVM, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
     244{
     245    PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
    228246#ifdef IN_RING0
    229     PGVM pGVM = pDevIns->Internal.s.pGVM;
    230     PCPDMIOAPIC pIoApic = &pGVM->pdm.s.IoApic;
    231247    if (pIoApic->pDevInsR0)
    232248        pIoApic->pfnSendMsiR0(pIoApic->pDevInsR0, uBusDevFn, pMsi, uTagSrc);
    … …  
    234250    {
    235251        /* Queue for ring-3 execution. */
    236         PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
     252        PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
    237253        if (pTask)
    238254        {
    239255            pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SEND_MSI;
    240             pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
     256            pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
    241257            pTask->u.IoApicSendMsi.uBusDevFn = uBusDevFn;
    242258            pTask->u.IoApicSendMsi.Msi       = *pMsi;
    243259            pTask->u.IoApicSendMsi.uTagSrc   = uTagSrc;
    244 
    245             PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
     260            PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
    246261        }
    247262        else
    … …  
    249264    }
    250265#else
    251     PVM pVM = pDevIns->Internal.s.pVMR3;
    252     PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
    253266    if (pIoApic->pDevInsR3)
    254267    {

  • trunk/src/VBox/VMM/VMMR0/PDMR0DevHlp.cpp

    r89600 r89620  
    16331633    Log4(("pdmR0PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi=(Addr:%#RX64 Data:%#RX32) uTagSrc=%#x\n", uBusDevFn, pMsi->Addr.u64,
    16341634          pMsi->Data.u32, uTagSrc));
    1635     PDMIoApicSendMsi(pDevIns, uBusDevFn, pMsi, uTagSrc);
     1635    PDMIoApicSendMsi(pDevIns->Internal.s.pGVM, uBusDevFn, pMsi, uTagSrc);
    16361636}
    16371637
    … …  
    17151715{
    17161716    PDMDEV_ASSERT_DEVINS(pDevIns);
    1717     PDMIoApicSendMsi(pDevIns, NIL_PCIBDF, pMsi, uTagSrc);
     1717    PDMIoApicSendMsi(pDevIns->Internal.s.pGVM, NIL_PCIBDF, pMsi, uTagSrc);
    17181718}
    17191719

  • trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp

    r89602 r89620  
    53715371            if (pPciDev)
    53725372            {
    5373                 size_t const    idxBus = pPciDev->Int.s.idxPdmBus;
     5373                size_t const idxBus = pPciDev->Int.s.idxPdmBus;
    53745374                AssertBreak(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses));
    5375                 PPDMPCIBUS      pBus   = &pVM->pdm.s.aPciBuses[idxBus];
     5375                PPDMPCIBUS   pBus   = &pVM->pdm.s.aPciBuses[idxBus];
    53765376
    53775377                pdmLock(pVM);
    … …  
    53945394        case PDMDEVHLPTASKOP_IOAPIC_SEND_MSI:
    53955395        {
    5396             Assert(pTask->pDevInsR3);
    5397             PDMIoApicSendMsi(pTask->pDevInsR3, pTask->u.IoApicSendMsi.uBusDevFn, &pTask->u.IoApicSendMsi.Msi,
    5398                              pTask->u.IoApicSendMsi.uTagSrc);
     5396            PDMIoApicSendMsi(pVM, pTask->u.IoApicSendMsi.uBusDevFn, &pTask->u.IoApicSendMsi.Msi, pTask->u.IoApicSendMsi.uTagSrc);
     5397            break;
     5398        }
     5399
     5400        case PDMDEVHLPTASKOP_IOAPIC_SET_EOI:
     5401        {
     5402            PDMIoApicBroadcastEoi(pVM, pTask->u.IoApicSetEoi.uVector);
    53995403            break;
    54005404        }

  • trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp

    r89600 r89620  
    215215    Log4(("pdmR3PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi (Addr=%#RX64 Data=%#x) uTagSrc=%#x\n", uBusDevFn,
    216216          pMsi->Addr.u64, pMsi->Data.u32, uTagSrc));
    217     PDMIoApicSendMsi(pDevIns, uBusDevFn, pMsi, uTagSrc);
     217    PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, uBusDevFn, pMsi, uTagSrc);
    218218}
    219219
    … …  
    303303    PDMDEV_ASSERT_DEVINS(pDevIns);
    304304    LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
    305     PDMIoApicSendMsi(pDevIns, NIL_PCIBDF, pMsi, uTagSrc);
     305    PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, NIL_PCIBDF, pMsi, uTagSrc);
    306306}
    307307

  • trunk/src/VBox/VMM/include/PDMInternal.h

    r89600 r89620  
    799799    DECLR3CALLBACKMEMBER(void,      pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
    800800    /** @copydoc PDMIOAPICREG::pfnSetEoi */
    801     DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
     801    DECLR3CALLBACKMEMBER(void,      pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
    802802
    803803    /** Pointer to the I/O  APIC device instance - R0. */
    … …  
    808808    DECLR0CALLBACKMEMBER(void,      pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
    809809    /** @copydoc PDMIOAPICREG::pfnSetEoi */
    810     DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
     810    DECLR0CALLBACKMEMBER(void,      pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
    811811
    812812    /** Pointer to the I/O APIC device instance - RC Ptr. */
    … …  
    817817    DECLRCCALLBACKMEMBER(void,      pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
    818818     /** @copydoc PDMIOAPICREG::pfnSendMsi */
    819     DECLRCCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
     819    DECLRCCALLBACKMEMBER(void,      pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
    820820} PDMIOAPIC;
    821821/** Pointer to a PDM IOAPIC instance. */
    … …  
    12151215    /** IoApicSendMsi */
    12161216    PDMDEVHLPTASKOP_IOAPIC_SEND_MSI,
     1217    /** IoApicBroadcastEoi */
     1218    PDMDEVHLPTASKOP_IOAPIC_SET_EOI,
    12171219    /** The usual 32-bit hack. */
    12181220    PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
    … …  
    12781280            uint32_t                uTagSrc;
    12791281        } IoApicSendMsi;
     1282
     1283        /**
     1284         * PDMDEVHLPTASKOP_IOAPIC_SET_EOI
     1285         */
     1286        struct PDMDEVHLPTASKIOAPICSETEOI
     1287        {
     1288            /** The vector corresponding to the EOI. */
     1289            uint8_t                 uVector;
     1290        } IoApicSetEoi;
    12801291
    12811292        /** Expanding the structure. */
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