|
|
|
@10110
|
16 years |
vboxsync |
More TPR updates
|
|
|
|
@10108
|
16 years |
vboxsync |
More CR8 updates
|
|
|
|
@10097
|
16 years |
vboxsync |
Derive CPL from cs, not ss.
|
|
|
|
@10095
|
16 years |
vboxsync |
logging change
|
|
|
|
@10066
|
16 years |
vboxsync |
Paranoid assertion
|
|
|
|
@10064
|
16 years |
vboxsync |
Missing log group
|
|
|
|
@10019
|
16 years |
vboxsync |
Updated for accepted shadow page modes.
|
|
|
|
@10018
|
16 years |
vboxsync |
Wrong assertion + logging updates
|
|
|
|
@10015
|
16 years |
vboxsync |
Don't forget to sync back MSR_K8_KERNEL_GS_BASE.
|
|
|
|
@10014
|
16 years |
vboxsync |
Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow …
|
|
|
|
@10011
|
16 years |
vboxsync |
Compile fix
|
|
|
|
@10010
|
16 years |
vboxsync |
Updates for 64 bits mode (invlpg - amd-v)
|
|
|
|
@9998
|
16 years |
vboxsync |
Logging update
|
|
|
|
@9988
|
16 years |
vboxsync |
Unconditionally update the sysenter msrs.
|
|
|
|
@9964
|
16 years |
vboxsync |
Paranoid assertion
|
|
|
|
@9915
|
16 years |
vboxsync |
fixed build breaks
|
|
|
|
@9897
|
16 years |
vboxsync |
Updates for executing 64 bits guest code with AMD-V.
|
|
|
|
@9896
|
16 years |
vboxsync |
Fixed SVMInvlpgA for 64 bits guest pointers and a potential issue with …
|
|
|
|
@9854
|
16 years |
vboxsync |
Sigh.
|
|
|
|
@9853
|
16 years |
vboxsync |
kernel gs base can be changed behind our back (swapgs), so always …
|
|
|
|
@9821
|
16 years |
vboxsync |
Compile fix
|
|
|
|
@9817
|
16 years |
vboxsync |
fs & gs base cleanup
|
|
|
|
@9815
|
16 years |
vboxsync |
Removed unnecessary guest msr saving.
|
|
|
|
@9814
|
16 years |
vboxsync |
FS & GS base msr fixes
|
|
|
|
@9805
|
16 years |
vboxsync |
Backed out previous changeset
|
|
|
|
@9804
|
16 years |
vboxsync |
FS & GS syncing
|
|
|
|
@9802
|
16 years |
vboxsync |
CPUMIsGuestIn64BitCodeEx update
|
|
|
|
@9720
|
16 years |
vboxsync |
Emulate rdmsr & wrmsr.
Note that Intel mentions a (slightly different) …
|
|
|
|
@9719
|
16 years |
vboxsync |
Accidental commit
|
|
|
|
@9718
|
16 years |
vboxsync |
Single instruction emulation for rd/wrmsr
|
|
|
|
@9708
|
16 years |
vboxsync |
Use RIP everywhere
|
|
|
|
@9686
|
16 years |
vboxsync |
Logging updates
|
|
|
|
@9669
|
16 years |
vboxsync |
warnings
|
|
|
|
@9660
|
16 years |
vboxsync |
Correction
|
|
|
|
@9659
|
16 years |
vboxsync |
SELMGetCpuModeFromSelector is a better name.
|
|
|
|
@9658
|
16 years |
vboxsync |
Renamed SELMIsSelector32Bit to SELMGetSelectorType.
|
|
|
|
@9593
|
16 years |
vboxsync |
Comments
|
|
|
|
@9592
|
16 years |
vboxsync |
Bug fixes
|
|
|
|
@9535
|
17 years |
vboxsync |
Log guest state in case of failure.
|
|
|
|
@9533
|
17 years |
vboxsync |
Dump state in case of VMX_EXIT_ERR_INVALID_GUEST_STATE.
|
|
|
|
@9484
|
17 years |
vboxsync |
Save & restore CSTAR, STAR, SFMASK & KERNEL_GSBASE MSRs (VT-x)
|
|
|
|
@9475
|
17 years |
vboxsync |
Added VMXR0StartVM64.
Sync the FS_BASE & GS_BASE MSRs.
|
|
|
|
@9457
|
17 years |
vboxsync |
Reapplied fixed 31707.
|
|
|
|
@9453
|
17 years |
vboxsync |
Backed out 31707
|
|
|
|
@9452
|
17 years |
vboxsync |
Preparing for 64 bits vmlaunch/vmresume.
|
|
|
|
@9421
|
17 years |
vboxsync |
64 bits hidden selector base.
|
|
|
|
@9414
|
17 years |
vboxsync |
macro
|
|
|
|
@9413
|
17 years |
vboxsync |
Compile fixes
|
|
|
|
@9412
|
17 years |
vboxsync |
use macros to access base, limit of a descriptor and offset of an IDT entry
|
|
|
|
@9411
|
17 years |
vboxsync |
Use a union for esp & rsp, so they are in-sync.
|
|
|
|
@9409
|
17 years |
vboxsync |
Probably caused the testbox failures.
|
|
|
|
@9407
|
17 years |
vboxsync |
HWACCM updates.
|
|
|
|
@9385
|
17 years |
vboxsync |
Backed out some of the changes. Broke VT-x
|
|
|
|
@9384
|
17 years |
vboxsync |
Compile fix
|
|
|
|
@9383
|
17 years |
vboxsync |
VT-x/AMD-V updates for 64 bits guests
|
|
|
|
@9212
|
17 years |
vboxsync |
Major changes for sizeof(RTGCPTR) == uint64_t.
Introduced RCPTRTYPE …
|
|
|
|
@9188
|
17 years |
vboxsync |
Same IF fix for halt instructions in VT-x.
|
|
|
|
@9184
|
17 years |
vboxsync |
If CF=0 HLT should never resume.
|
|
|
|
@9161
|
17 years |
vboxsync |
Have to save and restore MSR_K8_FS_BASE as well in the …
|
|
|
|
@9151
|
17 years |
vboxsync |
Statistics
|
|
|
|
@9125
|
17 years |
vboxsync |
AMD-V: setup PAT guest register for nested paging
|
|
|
|
@9122
|
17 years |
vboxsync |
Logging update
|
|
|
|
@9120
|
17 years |
vboxsync |
Updates
|
|
|
|
@9116
|
17 years |
vboxsync |
Added stat counter for physical page invalidation.
|
|
|
|
@9115
|
17 years |
vboxsync |
HWACCM: Invalidate pages changed by PGMHandlerPhysicalPageTempOff. …
|
|
|
|
@9110
|
17 years |
vboxsync |
Minor update
|
|
|
|
@9092
|
17 years |
vboxsync |
We need a real shadow paging backend for PGMHandlerPhysicalPageTempOff …
|
|
|
|
@9082
|
17 years |
vboxsync |
More statistics
|
|
|
|
@9075
|
17 years |
vboxsync |
Fixed wrong call to TRPMResetTrap
|
|
|
|
@9074
|
17 years |
vboxsync |
Log normal page faults in nested paging mode too (DEBUG only).
|
|
|
|
@9073
|
17 years |
vboxsync |
Updated logging
|
|
|
|
@9064
|
17 years |
vboxsync |
Properly deal with CR3 changes in nested paging mode.
|
|
|
|
@9046
|
17 years |
vboxsync |
Experimental workaround for the non-working debuggers and panicing …
|
|
|
|
@9038
|
17 years |
vboxsync |
Sync back the debug registers too (fixed gdb/dbx weirdness on solaris).
|
|
|
|
@9033
|
17 years |
vboxsync |
Statistics for SVM_EXIT_NPF
|
|
|
|
@9029
|
17 years |
vboxsync |
Removed assertion
|
|
|
|
@9026
|
17 years |
vboxsync |
More updates for nested paging. (setting up the paging mode)
|
|
|
|
@9021
|
17 years |
vboxsync |
Nested paging updates. Extra paging mode added to prevent illegal …
|
|
|
|
@9008
|
17 years |
vboxsync |
Changes for proper flushing of the TLB for physical registration changes.
|
|
|
|
@9001
|
17 years |
vboxsync |
Enabled the PGMMODE_PROTECTED (Guest) & PGMMODE_AMD64 (shadow) …
|
|
|
|
@8977
|
17 years |
vboxsync |
export
|
|
|
|
@8965
|
17 years |
vboxsync |
Nested paging updates
|
|
|
|
@8961
|
17 years |
vboxsync |
Fixed amd64 debug builds. Added some TODOs.
|
|
|
|
@8953
|
17 years |
vboxsync |
Ring-0 assertions are now always printed to the debug log.
Introduced …
|
|
|
|
@8952
|
17 years |
vboxsync |
Nested paging updates
|
|
|
|
@8948
|
17 years |
vboxsync |
Nested paging updates
|
|
|
|
@8945
|
17 years |
vboxsync |
Updated comment
|
|
|
|
@8944
|
17 years |
vboxsync |
Fixed problem with erratum 170 cpus.
|
|
|
|
@8943
|
17 years |
vboxsync |
AMD-V: flush TLB when the flush count for the cpu has changed
AMD-V: …
|
|
|
|
@8941
|
17 years |
vboxsync |
Intercept task switches as well. (they can change CR3)
|
|
|
|
@8914
|
17 years |
vboxsync |
Moved cpu id check around for tlb flushing.
|
|
|
|
@8901
|
17 years |
vboxsync |
Always enable caching
|
|
|
|
@8900
|
17 years |
vboxsync |
Some updates
|
|
|
|
@8881
|
17 years |
vboxsync |
Wrong assertion
|
|
|
|
@8880
|
17 years |
vboxsync |
More logging
|
|
|
|
@8879
|
17 years |
vboxsync |
Init idCpu
|
|
|
|
@8878
|
17 years |
vboxsync |
Don't automatically flush the TLB when we remain on the same cpu (on …
|
|
|
|
@8876
|
17 years |
vboxsync |
ASID based TLB flushing
|
|
|
|
@8873
|
17 years |
vboxsync |
Fetch the SVM features too and write them to the release log
|
|
|
|
@8871
|
17 years |
vboxsync |
Updated assertion
|
|
|
|
