|
|
|
@10886
|
17 years |
vboxsync |
Fixes for syncing back sysenter MSRs.
|
|
|
|
@10858
|
17 years |
vboxsync |
We can't rely on #NM handling in kernel mode, so do what we did before …
|
|
|
|
@10849
|
17 years |
vboxsync |
32 bits build fix
|
|
|
|
@10844
|
17 years |
vboxsync |
VMMR0: Fixed bogus pSession argument passed to vmmR0EntryExWorker when …
|
|
|
|
@10843
|
17 years |
vboxsync |
intnet: Implemented activation on power on & resume, deactivation on …
|
|
|
|
@10835
|
17 years |
vboxsync |
Obsolete comment removed
|
|
|
|
@10833
|
17 years |
vboxsync |
Backed out 33617. Doesn't solve anything.
|
|
|
|
@10832
|
17 years |
vboxsync |
TPR shadow changes.
|
|
|
|
@10828
|
17 years |
vboxsync |
Update
|
|
|
|
@10817
|
17 years |
vboxsync |
Started with EPT support.
|
|
|
|
@10806
|
17 years |
vboxsync |
intnet: Push the session down to all the INTNETR0* apis.
|
|
|
|
@10805
|
17 years |
vboxsync |
VMM+SUPDrv: Changed the VMMR0EntryEx interface to also take the …
|
|
|
|
@10746
|
17 years |
vboxsync |
Added pSession argument to all the intnet request packets.
|
|
|
|
@10724
|
17 years |
vboxsync |
Bumped the SUPDRV_IOC_VERSION major as the changes to the fast path on …
|
|
|
|
@10721
|
17 years |
vboxsync |
Missing update for last error handling.
|
|
|
|
@10716
|
17 years |
vboxsync |
TPR fix for VT-x
|
|
|
|
@10687
|
17 years |
vboxsync |
Save the FPU control word and MXCSR on entry and restore them …
|
|
|
|
@10683
|
17 years |
vboxsync |
Backed out 33399; must save the host context on entry due to long …
|
|
|
|
@10682
|
17 years |
vboxsync |
Saving of the host state is done correctly already for VT-x. (not …
|
|
|
|
@10673
|
17 years |
vboxsync |
Comment added.
|
|
|
|
@10672
|
17 years |
vboxsync |
Added a comment about the fact that we trash our own FPU state. Could …
|
|
|
|
@10667
|
17 years |
vboxsync |
Sync back TPR if necessary.
|
|
|
|
@10663
|
17 years |
vboxsync |
Created tstIntNet-1 for checking that capturing an interface works on …
|
|
|
|
@10661
|
17 years |
vboxsync |
Reduce the number of world switches caused by cr8 writes by checking …
|
|
|
|
@10655
|
17 years |
vboxsync |
Guest MSR_K6_EFER_FFXSR value is not relevant. Always manually …
|
|
|
|
@10647
|
17 years |
vboxsync |
Manual saving of XMM registers.
Use new FPU/MMX/XMM state saving for …
|
|
|
|
@10630
|
17 years |
vboxsync |
Newer functions for handling fpu save/restore in ring 0.
|
|
|
|
@10609
|
17 years |
vboxsync |
Check for unexpected rescheduling.
|
|
|
|
@10607
|
17 years |
vboxsync |
Guest state loading and host state saving *must* be done after TPR …
|
|
|
|
@10572
|
17 years |
vboxsync |
Use NIL_RTR0MEMOBJ and ASMMemZeroPage.
|
|
|
|
@10566
|
17 years |
vboxsync |
Comment
|
|
|
|
@10542
|
17 years |
vboxsync |
Go directly to the halted state when encountering a hlt instruction …
|
|
|
|
@10537
|
17 years |
vboxsync |
Updated HWACCMDumpRegs
|
|
|
|
@10509
|
17 years |
vboxsync |
And again
|
|
|
|
@10508
|
17 years |
vboxsync |
Stupid compiler
|
|
|
|
@10506
|
17 years |
vboxsync |
Assertion
|
|
|
|
@10505
|
17 years |
vboxsync |
Easier to grep for
|
|
|
|
@10504
|
17 years |
vboxsync |
Don't violate my own rules…
|
|
|
|
@10503
|
17 years |
vboxsync |
More logging
|
|
|
|
@10502
|
17 years |
vboxsync |
Take precautions for being rescheduled to a different cpu due to long …
|
|
|
|
@10500
|
17 years |
vboxsync |
Clarified comment
|
|
|
|
@10499
|
17 years |
vboxsync |
Another paranoid assertion.
|
|
|
|
@10498
|
17 years |
vboxsync |
Added warning
|
|
|
|
@10497
|
17 years |
vboxsync |
Another edge case where we need to flush the TLB.
|
|
|
|
@10491
|
17 years |
vboxsync |
Logging
|
|
|
|
@10489
|
17 years |
vboxsync |
AMD-V: Always flush the TLB the first time a cpu is used.
|
|
|
|
@10480
|
17 years |
vboxsync |
Must monitor CR8 writes. (for now)
|
|
|
|
@10473
|
17 years |
vboxsync |
MMIO instruction emulation for OR, BT and XOR added.
|
|
|
|
@10471
|
17 years |
vboxsync |
warning
|
|
|
|
@10466
|
17 years |
vboxsync |
Write back cached TPR
|
|
|
|
@10465
|
17 years |
vboxsync |
Cleaned up
|
|
|
|
@10464
|
17 years |
vboxsync |
More assertions
|
|
|
|
@10463
|
17 years |
vboxsync |
Use the TPR threshold feature.
|
|
|
|
@10458
|
17 years |
vboxsync |
TPR & interrupt dispatch updates.
|
|
|
|
@10450
|
17 years |
vboxsync |
Added VMMGetSvnRev() (exported) and changed VMMR0Init and VMMGCInit …
|
|
|
|
@10360
|
17 years |
vboxsync |
Removed the same assertion as before in the AMD-V code.
|
|
|
|
@10356
|
17 years |
vboxsync |
Safety precaution
|
|
|
|
@10355
|
17 years |
vboxsync |
TPR updates
|
|
|
|
@10354
|
17 years |
vboxsync |
Extra assertion
|
|
|
|
@10353
|
17 years |
vboxsync |
TPR caching for VT-x. Removed the CR8 register from CPUMCTX.
|
|
|
|
@10331
|
17 years |
vboxsync |
Removed the assertion completely.
|
|
|
|
@10330
|
17 years |
vboxsync |
Wrong assertion. Due to ring 3 far jumps the assertion condition can …
|
|
|
|
@10301
|
17 years |
vboxsync |
Wrong place for the assertion
|
|
|
|
@10299
|
17 years |
vboxsync |
Force a TLB flush on a mode switch too.
|
|
|
|
@10297
|
17 years |
vboxsync |
More assertions.
|
|
|
|
@10269
|
17 years |
vboxsync |
Logging updates
|
|
|
|
@10206
|
17 years |
vboxsync |
Fixed regression introduced by TPR caching. (never execute code that …
|
|
|
|
@10202
|
17 years |
vboxsync |
removed VBOX_WITH_PDM_LOCK
|
|
|
|
@10110
|
17 years |
vboxsync |
More TPR updates
|
|
|
|
@10108
|
17 years |
vboxsync |
More CR8 updates
|
|
|
|
@10097
|
17 years |
vboxsync |
Derive CPL from cs, not ss.
|
|
|
|
@10095
|
17 years |
vboxsync |
logging change
|
|
|
|
@10066
|
17 years |
vboxsync |
Paranoid assertion
|
|
|
|
@10064
|
17 years |
vboxsync |
Missing log group
|
|
|
|
@10019
|
17 years |
vboxsync |
Updated for accepted shadow page modes.
|
|
|
|
@10018
|
17 years |
vboxsync |
Wrong assertion + logging updates
|
|
|
|
@10015
|
17 years |
vboxsync |
Don't forget to sync back MSR_K8_KERNEL_GS_BASE.
|
|
|
|
@10014
|
17 years |
vboxsync |
Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow …
|
|
|
|
@10011
|
17 years |
vboxsync |
Compile fix
|
|
|
|
@10010
|
17 years |
vboxsync |
Updates for 64 bits mode (invlpg - amd-v)
|
|
|
|
@9998
|
17 years |
vboxsync |
Logging update
|
|
|
|
@9988
|
17 years |
vboxsync |
Unconditionally update the sysenter msrs.
|
|
|
|
@9964
|
17 years |
vboxsync |
Paranoid assertion
|
|
|
|
@9915
|
17 years |
vboxsync |
fixed build breaks
|
|
|
|
@9897
|
17 years |
vboxsync |
Updates for executing 64 bits guest code with AMD-V.
|
|
|
|
@9896
|
17 years |
vboxsync |
Fixed SVMInvlpgA for 64 bits guest pointers and a potential issue with …
|
|
|
|
@9854
|
17 years |
vboxsync |
Sigh.
|
|
|
|
@9853
|
17 years |
vboxsync |
kernel gs base can be changed behind our back (swapgs), so always …
|
|
|
|
@9821
|
17 years |
vboxsync |
Compile fix
|
|
|
|
@9817
|
17 years |
vboxsync |
fs & gs base cleanup
|
|
|
|
@9815
|
17 years |
vboxsync |
Removed unnecessary guest msr saving.
|
|
|
|
@9814
|
17 years |
vboxsync |
FS & GS base msr fixes
|
|
|
|
@9805
|
17 years |
vboxsync |
Backed out previous changeset
|
|
|
|
@9804
|
17 years |
vboxsync |
FS & GS syncing
|
|
|
|
@9802
|
17 years |
vboxsync |
CPUMIsGuestIn64BitCodeEx update
|
|
|
|
@9720
|
17 years |
vboxsync |
Emulate rdmsr & wrmsr.
Note that Intel mentions a (slightly different) …
|
|
|
|
@9719
|
17 years |
vboxsync |
Accidental commit
|
|
|
|
@9718
|
17 years |
vboxsync |
Single instruction emulation for rd/wrmsr
|
|
|
|
@9708
|
17 years |
vboxsync |
Use RIP everywhere
|
|
|
|
@9686
|
17 years |
vboxsync |
Logging updates
|
|
|
|
