Changeset 17586 in vbox for trunk

Timestamp:

Mar 9, 2009 3:28:25 PM (16 years ago)

Author:

vboxsync

Message:

Removed all dead non-VBOX_WITH_PGMPOOL_PAGING_ONLY code.

Location:

trunk/src/VBox/VMM

Files:

• PGM.cpp (modified) (9 diffs)
• PGMBth.h (modified) (2 diffs)
• PGMGst.h (modified) (6 diffs)
• PGMInternal.h (modified) (23 diffs)
• PGMMap.cpp (modified) (8 diffs)
• PGMPool.cpp (modified) (6 diffs)
• PGMShw.h (modified) (5 diffs)
• VMMAll/PGMAll.cpp (modified) (28 diffs)
• VMMAll/PGMAllBth.h (modified) (42 diffs)
• VMMAll/PGMAllGst.h (modified) (3 diffs)
• VMMAll/PGMAllMap.cpp (modified) (25 diffs)
• VMMAll/PGMAllPool.cpp (modified) (61 diffs)
• VMMAll/PGMAllShw.h (modified) (1 diff)
• VMMSwitcher.cpp (modified) (1 diff)
• testcase/tstVMStructGC.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/PGM.cpp

@@ -1177 +1177 @@
     pVM->pgm.s.enmHostMode      = SUPPAGINGMODE_INVALID;
     pVM->pgm.s.GCPhysCR3        = NIL_RTGCPHYS;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
-#endif
     pVM->pgm.s.fA20Enabled      = true;
     pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
@@ -1298 +1295 @@
         rc = pgmR3PoolInit(pVM);
     }
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     if (RT_SUCCESS(rc))
         rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
-#endif
+
     if (RT_SUCCESS(rc))
     {
@@ -1473 +1469 @@
 
     /*
-     * Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
-     * We allocate pages for all three posibilities in order to simplify mappings and
-     * avoid resource failure during mode switches. So, we need to cover all levels of the
-     * of the first 4GB down to PD level.
-     * As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
-     */
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    pVM->pgm.s.pShw32BitPdR3    = (PX86PD)MMR3PageAllocLow(pVM);
-# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    pVM->pgm.s.pShw32BitPdR0    = (uintptr_t)pVM->pgm.s.pShw32BitPdR3;
-# endif
-    pVM->pgm.s.apShwPaePDsR3[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
-    pVM->pgm.s.apShwPaePDsR3[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
-    AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1]);
-    pVM->pgm.s.apShwPaePDsR3[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
-    AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2]);
-    pVM->pgm.s.apShwPaePDsR3[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
-    AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3]);
-# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    pVM->pgm.s.apShwPaePDsR0[0] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[0];
-    pVM->pgm.s.apShwPaePDsR0[1] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1];
-    pVM->pgm.s.apShwPaePDsR0[2] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2];
-    pVM->pgm.s.apShwPaePDsR0[3] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3];
-# endif
-    pVM->pgm.s.pShwPaePdptR3 = (PX86PDPT)MMR3PageAllocLow(pVM);
-# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
-# endif
-    pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
-# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    pVM->pgm.s.pShwNestedRootR0 = (uintptr_t)pVM->pgm.s.pShwNestedRootR3;
-# endif
-#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
-
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    if (    !pVM->pgm.s.pShw32BitPdR3
-        ||  !pVM->pgm.s.apShwPaePDsR3[0]
-        ||  !pVM->pgm.s.apShwPaePDsR3[1]
-        ||  !pVM->pgm.s.apShwPaePDsR3[2]
-        ||  !pVM->pgm.s.apShwPaePDsR3[3]
-        ||  !pVM->pgm.s.pShwPaePdptR3
-        ||  !pVM->pgm.s.pShwNestedRootR3)
-    {
-        AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
-        return VERR_NO_PAGE_MEMORY;
-    }
-#endif
-
-    /* get physical addresses. */
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    pVM->pgm.s.HCPhysShw32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pShw32BitPdR3);
-    Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhysShw32BitPD) == pVM->pgm.s.pShw32BitPdR3);
-    pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[0]);
-    pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[1]);
-    pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[2]);
-    pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[3]);
-    pVM->pgm.s.HCPhysShwPaePdpt = MMPage2Phys(pVM, pVM->pgm.s.pShwPaePdptR3);
-    pVM->pgm.s.HCPhysShwNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
-#endif
-
-    /*
-     * Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
-     */
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    ASMMemZero32(pVM->pgm.s.pShw32BitPdR3, PAGE_SIZE);
-    ASMMemZero32(pVM->pgm.s.pShwPaePdptR3, PAGE_SIZE);
-    ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
-
-    for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
-    {
-        ASMMemZero32(pVM->pgm.s.apShwPaePDsR3[i], PAGE_SIZE);
-        pVM->pgm.s.pShwPaePdptR3->a[i].u = X86_PDPE_P | PGM_PLXFLAGS_PERMANENT | pVM->pgm.s.aHCPhysPaePDs[i];
-        /* The flags will be corrected when entering and leaving long mode. */
-    }
-#endif
-
-    /*
      * Initialize paging workers and mode from current host mode
      * and the guest running in real mode.
@@ -1582 +1501 @@
     }
     rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    if (RT_SUCCESS(rc))
-        rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
-#endif
     if (RT_SUCCESS(rc))
     {
         LogFlow(("pgmR3InitPaging: returns successfully\n"));
 #if HC_ARCH_BITS == 64
-# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp\n",
-                pVM->pgm.s.HCPhysShw32BitPD,
-                pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
-                pVM->pgm.s.HCPhysShwPaePdpt));
-# endif
         LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
                 pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
@@ -1891 +1800 @@
     int     rc;
 
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    /*
-     * Reserve space for mapping the paging pages into guest context.
-     */
-    rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3) + 1 + 2 + 2), "Paging", &GCPtr);
-    AssertRCReturn(rc, rc);
-    pVM->pgm.s.pShw32BitPdRC = GCPtr;
-    MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
-#endif
-
     /*
      * Reserve space for the dynamic mappings.
@@ -1933 +1832 @@
 {
     int rc;
-
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    /*
-     * Map the paging pages into the guest context.
-     */
-    RTGCPTR GCPtr = pVM->pgm.s.pShw32BitPdRC;
-    AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
-
-    rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShw32BitPD, PAGE_SIZE, 0);
-    AssertRCReturn(rc, rc);
-    pVM->pgm.s.pShw32BitPdRC = GCPtr;
-    GCPtr += PAGE_SIZE;
-    GCPtr += PAGE_SIZE; /* reserved page */
-
-    for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
-    {
-        rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
-        AssertRCReturn(rc, rc);
-        pVM->pgm.s.apShwPaePDsRC[i] = GCPtr;
-        GCPtr += PAGE_SIZE;
-    }
-    /* A bit of paranoia is justified. */
-    AssertRelease(pVM->pgm.s.apShwPaePDsRC[0] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[1]);
-    AssertRelease(pVM->pgm.s.apShwPaePDsRC[1] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[2]);
-    AssertRelease(pVM->pgm.s.apShwPaePDsRC[2] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[3]);
-    GCPtr += PAGE_SIZE; /* reserved page */
-
-    rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShwPaePdpt, PAGE_SIZE, 0);
-    AssertRCReturn(rc, rc);
-    pVM->pgm.s.pShwPaePdptRC = GCPtr;
-    GCPtr += PAGE_SIZE;
-    GCPtr += PAGE_SIZE; /* reserved page */
-#endif
 
     /*
@@ -2027 +1893 @@
     pVM->pgm.s.GCPtrCR3Mapping += offDelta;
     /** @todo move this into shadow and guest specific relocation functions. */
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    AssertMsg(pVM->pgm.s.pShw32BitPdR3, ("Init order, no relocation before paging is initialized!\n"));
-    pVM->pgm.s.pShw32BitPdRC += offDelta;
-#endif
     pVM->pgm.s.pGst32BitPdRC += offDelta;
     for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC); i++)
     {
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        AssertCompile(RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC));
-        pVM->pgm.s.apShwPaePDsRC[i] += offDelta;
-#endif
         pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
     }
     pVM->pgm.s.pGstPaePdptRC += offDelta;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    pVM->pgm.s.pShwPaePdptRC += offDelta;
-#endif
-
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
+
     pVM->pgm.s.pShwPageCR3RC += offDelta;
-#endif
 
     pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
@@ -3116 +2969 @@
     pVM->pgm.s.pfnR3GstModifyPage           = pModeData->pfnR3GstModifyPage;
     pVM->pgm.s.pfnR3GstGetPDE               = pModeData->pfnR3GstGetPDE;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    pVM->pgm.s.pfnR3GstMonitorCR3           = pModeData->pfnR3GstMonitorCR3;
-    pVM->pgm.s.pfnR3GstUnmonitorCR3         = pModeData->pfnR3GstUnmonitorCR3;
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    pVM->pgm.s.pfnR3GstWriteHandlerCR3      = pModeData->pfnR3GstWriteHandlerCR3;
-    pVM->pgm.s.pszR3GstWriteHandlerCR3      = pModeData->pszR3GstWriteHandlerCR3;
-    pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3   = pModeData->pfnR3GstPAEWriteHandlerCR3;
-    pVM->pgm.s.pszR3GstPAEWriteHandlerCR3   = pModeData->pszR3GstPAEWriteHandlerCR3;
-#endif
     pVM->pgm.s.pfnRCGstGetPage              = pModeData->pfnRCGstGetPage;
     pVM->pgm.s.pfnRCGstModifyPage           = pModeData->pfnRCGstModifyPage;
     pVM->pgm.s.pfnRCGstGetPDE               = pModeData->pfnRCGstGetPDE;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    pVM->pgm.s.pfnRCGstMonitorCR3           = pModeData->pfnRCGstMonitorCR3;
-    pVM->pgm.s.pfnRCGstUnmonitorCR3         = pModeData->pfnRCGstUnmonitorCR3;
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    pVM->pgm.s.pfnRCGstWriteHandlerCR3      = pModeData->pfnRCGstWriteHandlerCR3;
-    pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3   = pModeData->pfnRCGstPAEWriteHandlerCR3;
-#endif
     pVM->pgm.s.pfnR0GstGetPage              = pModeData->pfnR0GstGetPage;
     pVM->pgm.s.pfnR0GstModifyPage           = pModeData->pfnR0GstModifyPage;
     pVM->pgm.s.pfnR0GstGetPDE               = pModeData->pfnR0GstGetPDE;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    pVM->pgm.s.pfnR0GstMonitorCR3           = pModeData->pfnR0GstMonitorCR3;
-    pVM->pgm.s.pfnR0GstUnmonitorCR3         = pModeData->pfnR0GstUnmonitorCR3;
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    pVM->pgm.s.pfnR0GstWriteHandlerCR3      = pModeData->pfnR0GstWriteHandlerCR3;
-    pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3   = pModeData->pfnR0GstPAEWriteHandlerCR3;
-#endif
 
     /* both */
@@ -3486 +3313 @@
         }
     }
-
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    /** @todo This is a bug!
-     *
-     * We must flush the PGM pool cache if the guest mode changes; we don't always
-     * switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
-     * the shadow page tables.
-     *
-     * That only applies when switching between paging and non-paging modes.
-     */
-   /** @todo A20 setting */
-    if (   pVM->pgm.s.CTX_SUFF(pPool)
-        && !HWACCMIsNestedPagingActive(pVM)
-        && PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
-    {
-        Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
-        pgmPoolFlushAll(pVM);
-    }
-#endif
 
     /*

trunk/src/VBox/VMM/PGMBth.h

@@ -130 +130 @@
 PGM_BTH_DECL(int, Enter)(PVM pVM, RTGCPHYS GCPhysCR3)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     /* Here we deal with allocation of the root shadow page table for real and protected mode during mode switches;
      * Other modes rely on MapCR3/UnmapCR3 to setup the shadow root page tables. 
      */
-# if  (   (   PGM_SHW_TYPE == PGM_TYPE_32BIT \
-           || PGM_SHW_TYPE == PGM_TYPE_PAE    \
-           || PGM_SHW_TYPE == PGM_TYPE_AMD64) \
-       && (   PGM_GST_TYPE == PGM_TYPE_REAL   \
-           || PGM_GST_TYPE == PGM_TYPE_PROT))
+#if  (   (   PGM_SHW_TYPE == PGM_TYPE_32BIT \
+          || PGM_SHW_TYPE == PGM_TYPE_PAE    \
+          || PGM_SHW_TYPE == PGM_TYPE_AMD64) \
+      && (   PGM_GST_TYPE == PGM_TYPE_REAL   \
+          || PGM_GST_TYPE == PGM_TYPE_PROT))
 
     Assert(!HWACCMIsNestedPagingActive(pVM));
@@ -188 +187 @@
     /* Apply all hypervisor mappings to the new CR3. */
     return pgmMapActivateCR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
-# endif
-#else
-    /* nothing special to do here - InitData does the job. */
 #endif
     return VINF_SUCCESS;

trunk/src/VBox/VMM/PGMGst.h

@@ -31 +31 @@
 PGM_GST_DECL(int, Exit)(PVM pVM);
 
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-static DECLCALLBACK(int) pgmR3Gst32BitWriteHandlerCR3(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
-static DECLCALLBACK(int) pgmR3GstPAEWriteHandlerCR3(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
-#endif
-
 /* all */
 PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
 PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
 PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPDE);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
-PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
-#endif
 __END_DECLS
 
@@ -66 +57 @@
     pModeData->pfnR3GstGetPage            = PGM_GST_NAME(GetPage);
     pModeData->pfnR3GstModifyPage         = PGM_GST_NAME(ModifyPage);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    pModeData->pfnR3GstMonitorCR3         = PGM_GST_NAME(MonitorCR3);
-    pModeData->pfnR3GstUnmonitorCR3       = PGM_GST_NAME(UnmonitorCR3);
-#endif
-
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-# if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE
-    pModeData->pfnR3GstWriteHandlerCR3    = PGM_GST_NAME(WriteHandlerCR3);
-    pModeData->pszR3GstWriteHandlerCR3    = "Guest CR3 Write access handler";
-    pModeData->pfnR3GstPAEWriteHandlerCR3 = PGM_GST_NAME(WriteHandlerCR3);
-    pModeData->pszR3GstPAEWriteHandlerCR3 = "Guest CR3 Write access handler (PAE)";
-# else
-    pModeData->pfnR3GstWriteHandlerCR3    = NULL;
-    pModeData->pszR3GstWriteHandlerCR3    = NULL;
-    pModeData->pfnR3GstPAEWriteHandlerCR3 = NULL;
-    pModeData->pszR3GstPAEWriteHandlerCR3 = NULL;
-# endif
-#endif
 
     if (fResolveGCAndR0)
@@ -97 +70 @@
         rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_GST_NAME_RC_STR(GetPDE),           &pModeData->pfnRCGstGetPDE);
         AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(GetPDE), rc), rc);
-# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_GST_NAME_RC_STR(MonitorCR3),       &pModeData->pfnRCGstMonitorCR3);
-        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(MonitorCR3), rc), rc);
-        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_GST_NAME_RC_STR(UnmonitorCR3),     &pModeData->pfnRCGstUnmonitorCR3);
-        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(UnmonitorCR3), rc), rc);
-# endif
-# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-#  if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE
-        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_GST_NAME_RC_STR(WriteHandlerCR3),  &pModeData->pfnRCGstWriteHandlerCR3);
-        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(WriteHandlerCR3), rc), rc);
-        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_GST_NAME_RC_STR(WriteHandlerCR3),  &pModeData->pfnRCGstPAEWriteHandlerCR3);
-        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(WriteHandlerCR3), rc), rc);
-#  endif
-# endif
 #endif /* Not AMD64 shadow paging. */
 
@@ -120 +79 @@
         rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_GST_NAME_R0_STR(GetPDE),           &pModeData->pfnR0GstGetPDE);
         AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(GetPDE), rc), rc);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_GST_NAME_R0_STR(MonitorCR3),       &pModeData->pfnR0GstMonitorCR3);
-        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(MonitorCR3), rc), rc);
-        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_GST_NAME_R0_STR(UnmonitorCR3),     &pModeData->pfnR0GstUnmonitorCR3);
-        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(UnmonitorCR3), rc), rc);
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-# if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE
-        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_GST_NAME_R0_STR(WriteHandlerCR3),  &pModeData->pfnR0GstWriteHandlerCR3);
-        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(WriteHandlerCR3), rc), rc);
-        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_GST_NAME_R0_STR(WriteHandlerCR3),  &pModeData->pfnR0GstPAEWriteHandlerCR3);
-        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(WriteHandlerCR3), rc), rc);
-# endif
-#endif
     }
 
@@ -152 +97 @@
      * Map and monitor CR3
      */
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     int rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
-#else
-    int rc = PGM_BTH_NAME(MapCR3)(pVM, GCPhysCR3);
-    if (RT_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
-        rc = PGM_GST_NAME(MonitorCR3)(pVM, GCPhysCR3);
-#endif
     return rc;
 }
@@ -187 +126 @@
     int rc;
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     rc = PGM_BTH_PFN(UnmapCR3, pVM)(pVM);
-#else
-    rc = PGM_GST_NAME(UnmonitorCR3)(pVM);
-    if (RT_SUCCESS(rc))
-        rc = PGM_BTH_NAME(UnmapCR3)(pVM);
-#endif
     return rc;
 }
 
 
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-
-#if PGM_GST_TYPE == PGM_TYPE_32BIT
-/**
- * Physical write access for the Guest CR3 in 32-bit mode.
- *
- * @returns VINF_SUCCESS if the handler have carried out the operation.
- * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
- * @param   pVM             VM Handle.
- * @param   GCPhys          The physical address the guest is writing to.
- * @param   pvPhys          The HC mapping of that address.
- * @param   pvBuf           What the guest is reading/writing.
- * @param   cbBuf           How much it's reading/writing.
- * @param   enmAccessType   The access type.
- * @param   pvUser          User argument.
- */
-static DECLCALLBACK(int) pgmR3Gst32BitWriteHandlerCR3(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
-{
-    AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
-    Assert(enmAccessType == PGMACCESSTYPE_WRITE);
-    Log2(("pgmR3Gst32BitWriteHandlerCR3: ff=%#x GCPhys=%RGp pvPhys=%p cbBuf=%d pvBuf={%.*Rhxs}\n", pVM->fForcedActions, GCPhys, pvPhys, cbBuf, cbBuf, pvBuf));
-
-    /*
-     * Do the write operation.
-     */
-    memcpy(pvPhys, pvBuf, cbBuf);
-    if (    !pVM->pgm.s.fMappingsFixed
-        &&  !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
-    {
-        /*
-         * Check for conflicts.
-         */
-        const RTGCPTR   offPD = GCPhys & PAGE_OFFSET_MASK;
-        const unsigned  iPD1  = offPD / sizeof(X86PDE);
-        const unsigned  iPD2  = (unsigned)(offPD + cbBuf - 1) / sizeof(X86PDE);
-        Assert(iPD1 - iPD2 <= 1);
-        if (    (   pVM->pgm.s.pGst32BitPdR3->a[iPD1].n.u1Present
-                 && pgmGetMapping(pVM, iPD1 << X86_PD_SHIFT) )
-            ||  (   iPD1 != iPD2
-                 && pVM->pgm.s.pGst32BitPdR3->a[iPD2].n.u1Present
-                 && pgmGetMapping(pVM, iPD2 << X86_PD_SHIFT) )
-           )
-        {
-            Log(("pgmR3Gst32BitWriteHandlerCR3: detected conflict. iPD1=%#x iPD2=%#x GCPhys=%RGp\n", iPD1, iPD2, GCPhys));
-            STAM_COUNTER_INC(&pVM->pgm.s.StatR3GuestPDWriteConflict);
-            VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
-        }
-    }
-
-    STAM_COUNTER_INC(&pVM->pgm.s.StatR3GuestPDWrite);
-    return VINF_SUCCESS;
-}
-#endif /* 32BIT */
-
-#if PGM_GST_TYPE == PGM_TYPE_PAE
-
-/**
- * Physical write access handler for the Guest CR3 in PAE mode.
- *
- * @returns VINF_SUCCESS if the handler have carried out the operation.
- * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
- * @param   pVM             VM Handle.
- * @param   GCPhys          The physical address the guest is writing to.
- * @param   pvPhys          The HC mapping of that address.
- * @param   pvBuf           What the guest is reading/writing.
- * @param   cbBuf           How much it's reading/writing.
- * @param   enmAccessType   The access type.
- * @param   pvUser          User argument.
- */
-static DECLCALLBACK(int) pgmR3GstPAEWriteHandlerCR3(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
-{
-    AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
-    Assert(enmAccessType == PGMACCESSTYPE_WRITE);
-    Log2(("pgmR3GstPAEWriteHandlerCR3: ff=%#x GCPhys=%RGp pvPhys=%p cbBuf=%d pvBuf={%.*Rhxs}\n", pVM->fForcedActions, GCPhys, pvPhys, cbBuf, cbBuf, pvBuf));
-
-    /*
-     * Do the write operation.
-     */
-    memcpy(pvPhys, pvBuf, cbBuf);
-    if (    !pVM->pgm.s.fMappingsFixed
-        &&  !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
-    {
-        /*
-         * Check if any of the PDs have changed.
-         * We'll simply check all of them instead of figuring out which one/two to check.
-         */
-        for (unsigned i = 0; i < 4; i++)
-        {
-            if (    pVM->pgm.s.pGstPaePdptR3->a[i].n.u1Present
-                &&  (pVM->pgm.s.pGstPaePdptR3->a[i].u & X86_PDPE_PG_MASK) != pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
-            {
-                Log(("pgmR3GstPAEWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%RGp\n",
-                     i, pVM->pgm.s.pGstPaePdptR3->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
-                /*
-                 * The PD has changed.
-                 * We will schedule a monitoring update for the next TLB Flush,
-                 * InvalidatePage or SyncCR3.
-                 *
-                 * This isn't perfect, because a lazy page sync might be dealing with an half
-                 * updated PDPE. However, we assume that the guest OS is disabling interrupts
-                 * and being extremely careful (cmpxchg8b) when updating a PDPE where it's
-                 * executing.
-                 */
-                pVM->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
-            }
-        }
-    }
-    /*
-     * Flag a updating of the monitor at the next crossroad so we don't monitor the
-     * wrong pages for soo long that they can be reused as code pages and freak out
-     * the recompiler or something.
-     */
-    else
-        pVM->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
-
-
-    STAM_COUNTER_INC(&pVM->pgm.s.StatR3GuestPDWrite);
-    return VINF_SUCCESS;
-}
-
-#endif /* PAE */
-#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */

trunk/src/VBox/VMM/PGMInternal.h

@@ -53 +53 @@
  * @{
  */
-
-/*
- * Enable to use the PGM pool for all levels in the paging chain in all paging modes.
- */
-#define VBOX_WITH_PGMPOOL_PAGING_ONLY
 
 /**
@@ -1460 +1455 @@
 /** The first normal index. */
 #define PGMPOOL_IDX_FIRST_SPECIAL       1
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 /** Page directory (32-bit root). */
 #define PGMPOOL_IDX_PD                  1
@@ -1471 +1465 @@
 /** The first normal index. */
 #define PGMPOOL_IDX_FIRST               5
-#else
-/** Page directory (32-bit root). */
-#define PGMPOOL_IDX_PD                  1
-/** The extended PAE page directory (2048 entries, works as root currently). */
-#define PGMPOOL_IDX_PAE_PD              2
-/** PAE Page Directory Table 0. */
-#define PGMPOOL_IDX_PAE_PD_0            3
-/** PAE Page Directory Table 1. */
-#define PGMPOOL_IDX_PAE_PD_1            4
-/** PAE Page Directory Table 2. */
-#define PGMPOOL_IDX_PAE_PD_2            5
-/** PAE Page Directory Table 3. */
-#define PGMPOOL_IDX_PAE_PD_3            6
-/** Page Directory Pointer Table (PAE root, not currently used). */
-#define PGMPOOL_IDX_PDPT                7
-/** AMD64 CR3 level index.*/
-#define PGMPOOL_IDX_AMD64_CR3           8
-/** Nested paging root.*/
-#define PGMPOOL_IDX_NESTED_ROOT         9
-/** The first normal index. */
-#define PGMPOOL_IDX_FIRST               10
-#endif
 /** The last valid index. (inclusive, 14 bits) */
 #define PGMPOOL_IDX_LAST                0x3fff
@@ -1606 +1578 @@
     PGMPOOLKIND_EPT_PT_FOR_PHYS,
 
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    /** Shw: Root 32-bit page directory. */
-    PGMPOOLKIND_ROOT_32BIT_PD,
-    /** Shw: Root PAE page directory */
-    PGMPOOLKIND_ROOT_PAE_PD,
-    /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
-    PGMPOOLKIND_ROOT_PDPT,
-#endif
     /** Shw: Root Nested paging table. */
     PGMPOOLKIND_ROOT_NESTED,
@@ -1686 +1650 @@
      * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
     bool volatile       fReusedFlushPending;
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
     bool                fLocked;
-#else
-    /** Used to indicate that the guest is mapping the page is also used as a CR3.
-     * In these cases the access handler acts differently and will check
-     * for mapping conflicts like the normal CR3 handler.
-     * @todo When we change the CR3 shadowing to use pool pages, this flag can be
-     *       replaced by a list of pages which share access handler.
-     */
-    bool                fCR3Mix;
-#endif
 } PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
 
@@ -2162 +2116 @@
     DECLR3CALLBACKMEMBER(int,       pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
     DECLR3CALLBACKMEMBER(int,       pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    DECLR3CALLBACKMEMBER(int,       pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
-    DECLR3CALLBACKMEMBER(int,       pfnR3GstUnmonitorCR3,(PVM pVM));
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    R3PTRTYPE(PFNPGMR3PHYSHANDLER)  pfnR3GstWriteHandlerCR3;
-    R3PTRTYPE(const char *)         pszR3GstWriteHandlerCR3;
-    R3PTRTYPE(PFNPGMR3PHYSHANDLER)  pfnR3GstPAEWriteHandlerCR3;
-    R3PTRTYPE(const char *)         pszR3GstPAEWriteHandlerCR3;
-#endif
     DECLRCCALLBACKMEMBER(int,       pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
     DECLRCCALLBACKMEMBER(int,       pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
     DECLRCCALLBACKMEMBER(int,       pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    DECLRCCALLBACKMEMBER(int,       pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
-    DECLRCCALLBACKMEMBER(int,       pfnRCGstUnmonitorCR3,(PVM pVM));
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    RCPTRTYPE(PFNPGMRCPHYSHANDLER)  pfnRCGstWriteHandlerCR3;
-    RCPTRTYPE(PFNPGMRCPHYSHANDLER)  pfnRCGstPAEWriteHandlerCR3;
-#endif
     DECLR0CALLBACKMEMBER(int,       pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
     DECLR0CALLBACKMEMBER(int,       pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
     DECLR0CALLBACKMEMBER(int,       pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    DECLR0CALLBACKMEMBER(int,       pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
-    DECLR0CALLBACKMEMBER(int,       pfnR0GstUnmonitorCR3,(PVM pVM));
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    R0PTRTYPE(PFNPGMRCPHYSHANDLER)  pfnR0GstWriteHandlerCR3;
-    R0PTRTYPE(PFNPGMRCPHYSHANDLER)  pfnR0GstPAEWriteHandlerCR3;
-#endif
     /** @} */
 
@@ -2293 +2221 @@
     uint32_t                        u32Alignment;
 #endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    /** The physical address of the currently monitored guest CR3 page.
-     * When this value is NIL_RTGCPHYS no page is being monitored. */
-    RTGCPHYS                        GCPhysGstCR3Monitored;
-#endif
     /** @name 32-bit Guest Paging.
      * @{ */
@@ -2350 +2273 @@
     /** @} */
 
-# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    /** @name Shadow paging
-     * @{ */
-    /** The root page table - R3 Ptr. */
-    R3PTRTYPE(void *)               pShwRootR3;
-#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    /** The root page table - R0 Ptr. */
-    R0PTRTYPE(void *)               pShwRootR0;
-#  endif
-    /** The root page table - RC Ptr. */
-    RCPTRTYPE(void *)               pShwRootRC;
-#  if HC_ARCH_BITS == 64
-    uint32_t                        u32Padding1; /**< alignment padding. */
-#  endif
-    /** The Physical Address (HC) of the current active shadow CR3. */
-    RTHCPHYS                        HCPhysShwCR3;
-# endif
     /** Pointer to the page of the current active CR3 - R3 Ptr. */
     R3PTRTYPE(PPGMPOOLPAGE)         pShwPageCR3R3;
@@ -2381 +2287 @@
 # endif
     /** @} */
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    /** @name 32-bit Shadow Paging
-     * @{ */
-    /** The 32-Bit PD - R3 Ptr. */
-    R3PTRTYPE(PX86PD)               pShw32BitPdR3;
-    /** The 32-Bit PD - R0 Ptr. */
-    R0PTRTYPE(PX86PD)               pShw32BitPdR0;
-    /** The 32-Bit PD - RC Ptr. */
-    RCPTRTYPE(PX86PD)               pShw32BitPdRC;
-# if HC_ARCH_BITS == 64
-    uint32_t                        u32Padding10; /**< alignment padding. */
-# endif
-    /** The Physical Address (HC) of the 32-Bit PD. */
-    RTHCPHYS                        HCPhysShw32BitPD;
-    /** @} */
-
-    /** @name PAE Shadow Paging
-     * @{ */
-    /** The four PDs for the low 4GB - R3 Ptr.
-     * Even though these are 4 pointers, what they point at is a single table.
-     * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
-    R3PTRTYPE(PX86PDPAE)            apShwPaePDsR3[4];
-# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    /** The four PDs for the low 4GB - R0 Ptr.
-     * Same kind of mapping as apHCPaePDs. */
-    R0PTRTYPE(PX86PDPAE)            apShwPaePDsR0[4];
-# endif
-    /** The four PDs for the low 4GB - RC Ptr.
-     * Same kind of mapping as apHCPaePDs. */
-    RCPTRTYPE(PX86PDPAE)            apShwPaePDsRC[4];
-    /** The Physical Address (HC) of the four PDs for the low 4GB.
-     * These are *NOT* 4 contiguous pages. */
-    RTHCPHYS                        aHCPhysPaePDs[4];
-    /** The Physical Address (HC) of the PAE PDPT. */
-    RTHCPHYS                        HCPhysShwPaePdpt;
-    /** The PAE PDPT - R3 Ptr. */
-    R3PTRTYPE(PX86PDPT)             pShwPaePdptR3;
-    /** The PAE PDPT - R0 Ptr. */
-    R0PTRTYPE(PX86PDPT)             pShwPaePdptR0;
-    /** The PAE PDPT - RC Ptr. */
-    RCPTRTYPE(PX86PDPT)             pShwPaePdptRC;
-    /** @} */
-# if HC_ARCH_BITS == 64
-    RTRCPTR                         alignment5; /**< structure size alignment. */
-# endif
-    /** @name Nested Shadow Paging
-     * @{ */
-    /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
-    RTR3PTR                         pShwNestedRootR3;
-# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
-    RTR0PTR                         pShwNestedRootR0;
-# endif
-    /** The Physical Address (HC) of the nested paging root. */
-    RTHCPHYS                        HCPhysShwNestedRoot;
-    /** @}  */
-#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
 
     /** @name Function pointers for Shadow paging.
@@ -2463 +2312 @@
     DECLR3CALLBACKMEMBER(int,       pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
     DECLR3CALLBACKMEMBER(int,       pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    DECLR3CALLBACKMEMBER(int,       pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
-    DECLR3CALLBACKMEMBER(int,       pfnR3GstUnmonitorCR3,(PVM pVM));
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    R3PTRTYPE(PFNPGMR3PHYSHANDLER)  pfnR3GstWriteHandlerCR3;
-    R3PTRTYPE(const char *)         pszR3GstWriteHandlerCR3;
-    R3PTRTYPE(PFNPGMR3PHYSHANDLER)  pfnR3GstPAEWriteHandlerCR3;
-    R3PTRTYPE(const char *)         pszR3GstPAEWriteHandlerCR3;
-#endif
     DECLRCCALLBACKMEMBER(int,       pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
     DECLRCCALLBACKMEMBER(int,       pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
     DECLRCCALLBACKMEMBER(int,       pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    DECLRCCALLBACKMEMBER(int,       pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
-    DECLRCCALLBACKMEMBER(int,       pfnRCGstUnmonitorCR3,(PVM pVM));
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    RCPTRTYPE(PFNPGMRCPHYSHANDLER)  pfnRCGstWriteHandlerCR3;
-    RCPTRTYPE(PFNPGMRCPHYSHANDLER)  pfnRCGstPAEWriteHandlerCR3;
-#endif
 #if HC_ARCH_BITS == 64
     RTRCPTR                         alignment3; /**< structure size alignment. */
@@ -2491 +2322 @@
     DECLR0CALLBACKMEMBER(int,       pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
     DECLR0CALLBACKMEMBER(int,       pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    DECLR0CALLBACKMEMBER(int,       pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
-    DECLR0CALLBACKMEMBER(int,       pfnR0GstUnmonitorCR3,(PVM pVM));
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    R0PTRTYPE(PFNPGMRCPHYSHANDLER)  pfnR0GstWriteHandlerCR3;
-    R0PTRTYPE(PFNPGMRCPHYSHANDLER)  pfnR0GstPAEWriteHandlerCR3;
-#endif
     /** @} */
 
@@ -3072 +2895 @@
 int             pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
 #endif
-#if !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY) && (defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0))
-void           *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
-#endif
 int             pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
 PPGMPOOLPAGE    pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
@@ -3101 +2921 @@
 #endif
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 void            pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE);
 void            pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
 int             pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
-#endif
 int             pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
 int             pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
@@ -3532 +3350 @@
         return pv;
     }
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
-#else
-    return pgmPoolMapPageFallback(pPGM, pPage);
-#endif
 }
 
@@ -4212 +4026 @@
 DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
-#else
-# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
-    PX86PD          pShwPd;
-    Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
-    int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
-    AssertRCReturn(rc, NULL);
-    return pShwPd;
-# else
-    return pPGM->CTX_SUFF(pShw32BitPd);
-# endif
-#endif
 }
 
@@ -4275 +4077 @@
 DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
-#else
-# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
-    PX86PDPT pShwPdpt;
-    Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
-    int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
-    AssertRCReturn(rc, 0);
-    return pShwPdpt;
-# else
-    return pPGM->CTX_SUFF(pShwPaePdpt);
-# endif
-#endif
 }
 
@@ -4300 +4090 @@
 DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     const unsigned  iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
     PX86PDPT        pPdpt = pgmShwGetPaePDPTPtr(pPGM);
@@ -4312 +4101 @@
 
     return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
-#else
-    const unsigned  iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
-# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
-    PX86PDPAE       pPD;
-    int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
-    AssertRCReturn(rc, 0);
-    return pPD;
-# else
-    PX86PDPAE       pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
-    Assert(pPD);
-    return pPD;
-# endif
-#endif
 }
 
@@ -4337 +4113 @@
 DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     const unsigned  iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
 
@@ -4348 +4123 @@
 
     return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
-#else
-    AssertFailed();
-    return NULL;
-#endif
 }
 
@@ -4402 +4173 @@
 DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
-#else
-# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
-    PX86PML4 pShwPml4;
-    Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
-    int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
-    AssertRCReturn(rc, 0);
-    return pShwPml4;
-# else
-    Assert(pPGM->CTX_SUFF(pShwRoot));
-    return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
-# endif
-#endif
 }
 
@@ -4735 +4493 @@
 #endif /* PGMPOOL_WITH_CACHE */
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
-
 /**
  * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
@@ -4781 +4537 @@
 }
 
-#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
-
 /**
  * Tells if mappings are to be put into the shadow page table or not

trunk/src/VBox/VMM/PGMMap.cpp

@@ -621 +621 @@
     }
 
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    /*
-     * Turn off CR3 updating monitoring.
-     */
-    int rc2 = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
-    AssertRC(rc2);
-#endif
-
     /*
      * Mark the mappings as fixed and return.
@@ -686 +678 @@
     pVM->pgm.s.GCPtrMappingFixed = 0;
     pVM->pgm.s.cbMappingFixed    = 0;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
-
-    /*
-     * Re-enable the CR3 monitoring.
-     *
-     * Paranoia: We flush the page pool before doing that because Windows
-     * is using the CR3 page both as a PD and a PT, e.g. the pool may
-     * be monitoring it.
-     */
-# ifdef PGMPOOL_WITH_MONITORING
-    pgmPoolFlushAll(pVM);
-# endif
-    /* Remap CR3 as we have just flushed the CR3 shadow PML4 in case we're in long mode. */
-    int rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
-    AssertRCSuccess(rc);
-
-    rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
-    AssertRCSuccess(rc);
-#endif
     return VINF_SUCCESS;
 }
@@ -928 +900 @@
     unsigned i = pMap->cPTs;
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     pgmMapClearShadowPDEs(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pMap, iOldPDE);
-#endif
 
     iOldPDE += i;
@@ -941 +911 @@
          */
         pVM->pgm.s.pInterPD->a[iOldPDE].u        = 0;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        pVM->pgm.s.pShw32BitPdR3->a[iOldPDE].u   = 0;
-#endif
         /*
          * PAE.
@@ -950 +917 @@
         unsigned iPDE = iOldPDE * 2 % 512;
         pVM->pgm.s.apInterPaePDs[iPD]->a[iPDE].u = 0;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        pVM->pgm.s.apShwPaePDsR3[iPD]->a[iPDE].u = 0;
-#endif
         iPDE++;
         AssertFatal(iPDE < 512);
         pVM->pgm.s.apInterPaePDs[iPD]->a[iPDE].u = 0;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        pVM->pgm.s.apShwPaePDsR3[iPD]->a[iPDE].u = 0;
-
-        /* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode) */
-        pVM->pgm.s.pShwPaePdptR3->a[iPD].u &= ~PGM_PLXFLAGS_MAPPING;
-#endif
     }
 }
@@ -978 +936 @@
     Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s) || PGMGetGuestMode(pVM) <= PGMMODE_PAE_NX);
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     pgmMapSetShadowPDEs(pVM, pMap, iNewPDE);
-#endif
 
     /*
@@ -994 +950 @@
          * 32-bit.
          */
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        Assert(!pPGM->pShw32BitPdR3->a[iNewPDE].n.u1Present || pgmMapAreMappingsEnabled(&pVM->pgm.s));
-        if (    pgmMapAreMappingsEnabled(&pVM->pgm.s)
-            &&  pPGM->pShw32BitPdR3->a[iNewPDE].n.u1Present)
-        {
-            Assert(!(pPGM->pShw32BitPdR3->a[iNewPDE].u & PGM_PDFLAGS_MAPPING));
-            pgmPoolFree(pVM, pPGM->pShw32BitPdR3->a[iNewPDE].u & X86_PDE_PG_MASK, PGMPOOL_IDX_PD, iNewPDE);
-        }
-#endif
         X86PDE Pde;
         /* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags */
         Pde.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT;
         pPGM->pInterPD->a[iNewPDE]        = Pde;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
-            pPGM->pShw32BitPdR3->a[iNewPDE]   = Pde;
-#endif
         /*
          * PAE.
@@ -1016 +959 @@
         const unsigned iPD = iNewPDE / 256;
         unsigned iPDE = iNewPDE * 2 % 512;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        Assert(!pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present || pgmMapAreMappingsEnabled(&pVM->pgm.s));
-        if (   pgmMapAreMappingsEnabled(&pVM->pgm.s)
-            && pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present)
-        {
-            Assert(!(pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & PGM_PDFLAGS_MAPPING));
-            pgmPoolFree(pVM, pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2);
-        }
-#endif
         X86PDEPAE PdePae0;
         PdePae0.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0;
         pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae0;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
-            pPGM->apShwPaePDsR3[iPD]->a[iPDE] = PdePae0;
-#endif
         iPDE++;
         AssertFatal(iPDE < 512);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        Assert(!pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present || pgmMapAreMappingsEnabled(&pVM->pgm.s));
-        if (   pgmMapAreMappingsEnabled(&pVM->pgm.s)
-            && pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present)
-        {
-            Assert(!(pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & PGM_PDFLAGS_MAPPING));
-            pgmPoolFree(pVM, pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2 + 1);
-        }
-#endif
         X86PDEPAE PdePae1;
         PdePae1.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1;
         pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae1;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
-        {
-            pPGM->apShwPaePDsR3[iPD]->a[iPDE] = PdePae1;
-
-            /* Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode) */
-            pPGM->pShwPaePdptR3->a[iPD].u |= PGM_PLXFLAGS_MAPPING;
-        }
-#endif
     }
 }

trunk/src/VBox/VMM/PGMPool.cpp

@@ -255 +255 @@
     pPool->aPages[PGMPOOL_IDX_PD].Core.Key  = NIL_RTHCPHYS;
     pPool->aPages[PGMPOOL_IDX_PD].GCPhys    = NIL_RTGCPHYS;
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     pPool->aPages[PGMPOOL_IDX_PD].pvPageR3  = 0;
     pPool->aPages[PGMPOOL_IDX_PD].enmKind   = PGMPOOLKIND_32BIT_PD;
-#else
-    pPool->aPages[PGMPOOL_IDX_PD].pvPageR3  = pVM->pgm.s.pShw32BitPdR3;
-    pPool->aPages[PGMPOOL_IDX_PD].enmKind   = PGMPOOLKIND_ROOT_32BIT_PD;
-#endif
     pPool->aPages[PGMPOOL_IDX_PD].idx       = PGMPOOL_IDX_PD;
-
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    /* The Shadow PAE PDs. This is actually 4 pages! (32 bits guest paging)  */
-    pPool->aPages[PGMPOOL_IDX_PAE_PD].Core.Key  = NIL_RTHCPHYS;
-    pPool->aPages[PGMPOOL_IDX_PAE_PD].GCPhys    = NIL_RTGCPHYS;
-    pPool->aPages[PGMPOOL_IDX_PAE_PD].pvPageR3  = pVM->pgm.s.apShwPaePDsR3[0];
-    pPool->aPages[PGMPOOL_IDX_PAE_PD].enmKind   = PGMPOOLKIND_ROOT_PAE_PD;
-    pPool->aPages[PGMPOOL_IDX_PAE_PD].idx       = PGMPOOL_IDX_PAE_PD;
-
-    /* The Shadow PAE PDs for PAE guest mode. */
-    for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
-    {
-        pPool->aPages[PGMPOOL_IDX_PAE_PD_0 + i].Core.Key  = NIL_RTHCPHYS;
-        pPool->aPages[PGMPOOL_IDX_PAE_PD_0 + i].GCPhys    = NIL_RTGCPHYS;
-        pPool->aPages[PGMPOOL_IDX_PAE_PD_0 + i].pvPageR3  = pVM->pgm.s.apShwPaePDsR3[i];
-        pPool->aPages[PGMPOOL_IDX_PAE_PD_0 + i].enmKind   = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
-        pPool->aPages[PGMPOOL_IDX_PAE_PD_0 + i].idx       = PGMPOOL_IDX_PAE_PD_0 + i;
-    }
-#endif
 
     /* The Shadow PDPT. */
     pPool->aPages[PGMPOOL_IDX_PDPT].Core.Key  = NIL_RTHCPHYS;
     pPool->aPages[PGMPOOL_IDX_PDPT].GCPhys    = NIL_RTGCPHYS;
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     pPool->aPages[PGMPOOL_IDX_PDPT].pvPageR3  = 0;
     pPool->aPages[PGMPOOL_IDX_PDPT].enmKind   = PGMPOOLKIND_PAE_PDPT;
-#else
-    pPool->aPages[PGMPOOL_IDX_PDPT].pvPageR3  = pVM->pgm.s.pShwPaePdptR3;
-    pPool->aPages[PGMPOOL_IDX_PDPT].enmKind   = PGMPOOLKIND_ROOT_PDPT;
-#endif
     pPool->aPages[PGMPOOL_IDX_PDPT].idx       = PGMPOOL_IDX_PDPT;
 
@@ -298 +269 @@
     pPool->aPages[PGMPOOL_IDX_AMD64_CR3].Core.Key  = NIL_RTHCPHYS;
     pPool->aPages[PGMPOOL_IDX_AMD64_CR3].GCPhys    = NIL_RTGCPHYS;
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     pPool->aPages[PGMPOOL_IDX_AMD64_CR3].pvPageR3  = 0;
-#else
-    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].pvPageR3  = pVM->pgm.s.pShwPaePdptR3;  /* not used - isn't it wrong as well? */
-#endif
     pPool->aPages[PGMPOOL_IDX_AMD64_CR3].enmKind   = PGMPOOLKIND_64BIT_PML4;
     pPool->aPages[PGMPOOL_IDX_AMD64_CR3].idx       = PGMPOOL_IDX_AMD64_CR3;
@@ -309 +276 @@
     pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].Core.Key  = NIL_RTHCPHYS;
     pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].GCPhys    = NIL_RTGCPHYS;
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].pvPageR3  = 0;
-#else
-    pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].pvPageR3  = pVM->pgm.s.pShwNestedRootR3;
-#endif
     pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].enmKind   = PGMPOOLKIND_ROOT_NESTED;
     pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].idx       = PGMPOOL_IDX_NESTED_ROOT;
@@ -335 +298 @@
         pPool->aPages[iPage].iAgeNext       = NIL_PGMPOOL_IDX;
         pPool->aPages[iPage].iAgePrev       = NIL_PGMPOOL_IDX;
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        Assert(VALID_PTR(pPool->aPages[iPage].pvPageR3));
 #endif
         Assert(pPool->aPages[iPage].idx == iPage);
@@ -475 +435 @@
         PPGMPOOLPAGE pPage = &pPool->aPages[i];
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         /* Allocate all pages in low (below 4 GB) memory as 32 bits guests need a page table root in low memory. */
         pPage->pvPageR3 = MMR3PageAllocLow(pVM);
-#else
-        pPage->pvPageR3 = MMR3PageAlloc(pVM);
-#endif
         if (!pPage->pvPageR3)
         {
@@ -590 +546 @@
     }
     else if (    (   pPage->cModifications < 96 /* it's cheaper here. */
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                   || pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
-#else
-                  || pPage->fCR3Mix
-#endif
                   )
              &&  cbBuf <= 4)

trunk/src/VBox/VMM/PGMShw.h

@@ -110 +110 @@
 #  define SHW_PDPE_PG_MASK      X86_PDPE_PG_MASK
 #  define SHW_TOTAL_PD_ENTRIES  (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 #  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_PDPT
-#  else
-#  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_PAE_PD
-#  endif
-
 # endif
 #endif
@@ -184 +179 @@
 PGM_SHW_DECL(int, Enter)(PVM pVM)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
-# if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
+#if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
     RTGCPHYS     GCPhysCR3 = RT_BIT_64(63);
     PPGMPOOLPAGE pNewShwPageCR3;
@@ -207 +201 @@
 
     Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVM->pgm.s.pShwPageCR3R3, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key));
-# endif
-#else
-# if PGM_SHW_TYPE == PGM_TYPE_NESTED
-#   ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    pVM->pgm.s.pShwRootR0 = (R0PTRTYPE(void *))pVM->pgm.s.pShwNestedRootR0;
-#   else
-    pVM->pgm.s.pShwRootR3 = (R3PTRTYPE(void *))pVM->pgm.s.pShwNestedRootR3;
-#   endif
-    pVM->pgm.s.HCPhysShwCR3 = pVM->pgm.s.HCPhysShwNestedRoot;
-
-    CPUMSetHyperCR3(pVM, PGMGetHyperCR3(pVM));
-# endif
 #endif
-
     return VINF_SUCCESS;
 }
@@ -247 +228 @@
 PGM_SHW_DECL(int, Exit)(PVM pVM)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
-# if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
+#if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
     if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
     {
@@ -265 +245 @@
         pVM->pgm.s.iShwUserTable = 0;
     }
-# endif
-# else
-# if PGM_SHW_TYPE == PGM_TYPE_NESTED
-    Assert(HWACCMIsNestedPagingActive(pVM));
-    pVM->pgm.s.pShwRootR3 = 0;
-#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    pVM->pgm.s.pShwRootR0 = 0;
-#  endif
-    pVM->pgm.s.HCPhysShwCR3 = 0;
-
     Log(("Leave nested shadow paging mode\n"));
-# endif
 #endif
     return VINF_SUCCESS;

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -71 +71 @@
 DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
 DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGM pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
-#endif
 
 /*
@@ -738 +736 @@
         pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
         Assert(!pVM->pgm.s.fMappingsFixed);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
-        rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
-#endif
     }
 
@@ -868 +862 @@
         return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
 
+    Assert(pPdpe->u & X86_PDPE_PG_MASK);
     pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
     AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
@@ -874 +869 @@
     return VINF_SUCCESS;
 }
-
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 
 /**
@@ -904 +897 @@
         PGMPOOLKIND enmKind;
 
-# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+# if defined(IN_RC)
         /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
         PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
@@ -952 +945 @@
             Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
             VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
-# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+# if defined(IN_RC)
             PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
 # endif
@@ -963 +956 @@
                  | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
 
-# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+# if defined(IN_RC)
         /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
          * non-present PDPT will continue to cause page faults.
@@ -1010 +1003 @@
 }
 
-#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
 #ifndef IN_RC
 
@@ -1035 +1027 @@
     PX86PML4E      pPml4e        = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
     bool           fNestedPaging = HWACCMIsNestedPagingActive(pVM);
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     bool           fPaging      = !!(CPUMGetGuestCR0(pVM) & X86_CR0_PG);
-#endif
     PPGMPOOLPAGE   pShwPage;
     int            rc;
@@ -1045 +1035 @@
         &&  !(pPml4e->u & X86_PML4E_PG_MASK))
     {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         RTGCPTR64   GCPml4;
         PGMPOOLKIND enmKind;
@@ -1067 +1056 @@
         /* Create a reference back to the PDPT by using the index in its shadow page. */
         rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
-#else
-        if (!fNestedPaging)
-        {
-            Assert(pGstPml4e && pGstPdpe);
-            Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
-
-            rc = pgmPoolAlloc(pVM, pGstPml4e->u & X86_PML4E_PG_MASK,
-                              PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
-        }
-        else
-        {
-            /* AMD-V nested paging. (Intel EPT never comes here) */
-            RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
-            rc = pgmPoolAlloc(pVM, GCPml4 + RT_BIT_64(63) /* hack: make the address unique */,
-                              PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
-        }
-#endif
         if (rc == VERR_PGM_POOL_FLUSHED)
         {
@@ -1110 +1082 @@
         &&  !(pPdpe->u & X86_PDPE_PG_MASK))
     {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         RTGCPTR64   GCPdPt;
         PGMPOOLKIND enmKind;
@@ -1130 +1101 @@
         /* Create a reference back to the PDPT by using the index in its shadow page. */
         rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
-#else
-        if (!fNestedPaging)
-        {
-            Assert(pGstPml4e && pGstPdpe);
-            Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
-            /* Create a reference back to the PDPT by using the index in its shadow page. */
-            rc = pgmPoolAlloc(pVM, pGstPdpe->u & X86_PDPE_PG_MASK, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD, pShwPage->idx, iPdPt, &pShwPage);
-        }
-        else
-        {
-            /* AMD-V nested paging. (Intel EPT never comes here) */
-            RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
-
-            rc = pgmPoolAlloc(pVM, GCPdPt + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
-        }
-#endif
         if (rc == VERR_PGM_POOL_FLUSHED)
         {
@@ -1228 +1183 @@
     Assert(HWACCMIsNestedPagingActive(pVM));
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
-#else
-# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
-    rc = PGM_HCPHYS_2_PTR(pVM, pPGM->HCPhysShwNestedRoot, &pPml4);
-    AssertRCReturn(rc, rc);
-# else
-    pPml4 = (PEPTPML4)pPGM->CTX_SUFF(pShwNestedRoot);
-# endif
-#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
     Assert(pPml4);
 
@@ -1248 +1194 @@
         RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
-#else
-        rc = pgmPoolAlloc(pVM, GCPml4 + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
-#endif
         if (rc == VERR_PGM_POOL_FLUSHED)
         {
@@ -1286 +1228 @@
         RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
-#else
-        rc = pgmPoolAlloc(pVM, GCPdPt + RT_BIT_64(62) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
-#endif
         if (rc == VERR_PGM_POOL_FLUSHED)
         {
@@ -1431 +1369 @@
 VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
-#else
-    PGMMODE enmShadowMode = pVM->pgm.s.enmShadowMode;
-    switch (enmShadowMode)
-    {
-        case PGMMODE_32_BIT:
-            return pVM->pgm.s.HCPhysShw32BitPD;
-
-        case PGMMODE_PAE:
-        case PGMMODE_PAE_NX:
-            return pVM->pgm.s.HCPhysShwPaePdpt;
-
-        case PGMMODE_AMD64:
-        case PGMMODE_AMD64_NX:
-            return pVM->pgm.s.HCPhysShwCR3;
-
-        case PGMMODE_EPT:
-            return pVM->pgm.s.HCPhysShwNestedRoot;
-
-        case PGMMODE_NESTED:
-            return PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
-
-        default:
-            AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
-            return ~0;
-    }
-#endif
 }
 
@@ -1470 +1381 @@
 VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
-#else
-    switch (enmShadowMode)
-    {
-        case PGMMODE_32_BIT:
-            return pVM->pgm.s.HCPhysShw32BitPD;
-
-        case PGMMODE_PAE:
-        case PGMMODE_PAE_NX:
-            return pVM->pgm.s.HCPhysShwPaePdpt;
-
-        case PGMMODE_AMD64:
-        case PGMMODE_AMD64_NX:
-            return pVM->pgm.s.HCPhysShwCR3;
-
-        default:
-            AssertMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
-            return ~0;
-    }
-#endif
 }
 
@@ -1502 +1393 @@
 VMMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
-#else
-    return pVM->pgm.s.HCPhysShw32BitPD;
-#endif
 }
 
@@ -1518 +1405 @@
 VMMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
-#else
-    return pVM->pgm.s.HCPhysShwPaePdpt;
-#endif
 }
 
@@ -1534 +1417 @@
 VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     return pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
-#else
-    return pVM->pgm.s.HCPhysShwCR3;
-#endif
 }
 
@@ -1694 +1573 @@
             {
                 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-                rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
-#endif
             }
         }
@@ -1723 +1599 @@
             pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
             Assert(!pVM->pgm.s.fMappingsFixed);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-            rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, GCPhysCR3);
-#endif
         }
         if (fGlobal)
@@ -1868 +1741 @@
         }
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         if (pVM->pgm.s.GCPhysCR3 != GCPhysCR3)
         {
@@ -1874 +1746 @@
             rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
         }
-#else
-        pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
-        rc = PGM_BTH_PFN(MapCR3, pVM)(pVM, GCPhysCR3);
-#endif
 #ifdef IN_RING3
         if (rc == VINF_PGM_SYNC_CR3)
@@ -1914 +1782 @@
             pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
             Assert(!pVM->pgm.s.fMappingsFixed);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-            Assert(pVM->pgm.s.GCPhysCR3 == pVM->pgm.s.GCPhysGstCR3Monitored);
-            rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
-#endif
         }
     }
@@ -2263 +2127 @@
      */
     register unsigned iPage = pVM->pgm.s.iDynPageMapLast;
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     unsigned i;
     for (i=0;i<(MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT);i++)
@@ -2273 +2136 @@
     }
     AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
-#  else
-    pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
-#  endif
 
     pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -82 +82 @@
 PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
 {
-# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY) && defined(VBOX_STRICT)
+# if defined(IN_RC) && defined(VBOX_STRICT)
     PGMDynCheckLocks(pVM);
 # endif
@@ -115 +115 @@
 #    if PGM_GST_TYPE == PGM_TYPE_PAE
     unsigned        iPDSrc;
-#     ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     X86PDPE         PdpeSrc;
     PGSTPD          pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
-#     else
-    PGSTPD          pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, NULL);
-#     endif
 
 #    elif PGM_GST_TYPE == PGM_TYPE_AMD64
@@ -159 +155 @@
     const unsigned  iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK;   /* pPDDst index, not used with the pool. */
 
-#   ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     PX86PDPAE       pPDDst;
 #    if PGM_GST_TYPE != PGM_TYPE_PAE
@@ -174 +169 @@
     }
     Assert(pPDDst);
-
-#   else
-    PX86PDPAE       pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, pvFault);
-
-    /* Did we mark the PDPT as not present in SyncCR3? */
-    unsigned        iPdpt  = (pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
-    PX86PDPT        pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
-    if (!pPdptDst->a[iPdpt].n.u1Present)
-        pPdptDst->a[iPdpt].n.u1Present = 1;
-#   endif
 
 #  elif PGM_SHW_TYPE == PGM_TYPE_AMD64
@@ -943 +928 @@
     PX86PDE         pPdeDst   = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
 
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     /* Fetch the pgm pool shadow descriptor. */
     PPGMPOOLPAGE    pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
     Assert(pShwPde);
-#  endif
 
 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
@@ -961 +944 @@
     }
 
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     const unsigned  iPDDst  = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
     PPGMPOOLPAGE    pShwPde;
@@ -973 +955 @@
     pPDDst             = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
     PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
-#  else
-    const unsigned  iPDDst    = (GCPtrPage >> SHW_PD_SHIFT) /*& SHW_PD_MASK - pool index only atm! */;
-    PX86PDEPAE      pPdeDst   = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
-#  endif
 
 # else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
     /* PML4 */
-#  ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    AssertReturn(pVM->pgm.s.pShwRootR3, VERR_INTERNAL_ERROR);
-#  endif
-
     const unsigned  iPml4     = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
     const unsigned  iPdpt     = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
@@ -1165 +1139 @@
     }
 # endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
-
-# if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
-    /*
-     * Update the shadow PDPE and free all the shadow PD entries if the PDPE is marked not present.
-     * Note: This shouldn't actually be necessary as we monitor the PDPT page for changes.
-     */
-    if (!pPDSrc)
-    {
-        /* Guest PDPE not present */
-        PX86PDPAE  pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, GCPtrPage);
-        PPGMPOOL   pPool  = pVM->pgm.s.CTX_SUFF(pPool);
-
-        Assert(!PdpeSrc.n.u1Present);
-        LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpt));
-
-        /* for each page directory entry */
-        for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
-        {
-            if (   pPDDst->a[iPD].n.u1Present
-                && !(pPDDst->a[iPD].u & PGM_PDFLAGS_MAPPING))
-            {
-                pgmPoolFree(pVM, pPDDst->a[iPD].u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
-                pPDDst->a[iPD].u = 0;
-            }
-        }
-        if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
-            pPdptDst->a[iPdpt].n.u1Present = 0;
-        PGM_INVL_GUEST_TLBS();
-    }
-    AssertMsg(pVM->pgm.s.fMappingsFixed || (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt], ("%RGp vs %RGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt]));
-# endif
 
 
@@ -1221 +1164 @@
             LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
                      GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
-# if PGM_GST_TYPE == PGM_TYPE_AMD64 || defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
             pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
-# else
-            pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
-# endif
             pPdeDst->u = 0;
             STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
@@ -1237 +1176 @@
             LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
                      GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
-# if PGM_GST_TYPE == PGM_TYPE_AMD64 || defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
             pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
-# else
-            pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
-# endif
             pPdeDst->u = 0;
             STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
@@ -1285 +1220 @@
                 LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
                          GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
-# if PGM_GST_TYPE == PGM_TYPE_AMD64 || defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
                 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
-# else
-                pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
-# endif
                 pPdeDst->u = 0;
                 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
@@ -1331 +1262 @@
             LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
                      GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
-# if PGM_GST_TYPE == PGM_TYPE_AMD64 || defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
             pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
-# else
-            pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
-# endif
             pPdeDst->u = 0;
             STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
@@ -1348 +1275 @@
         if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
         {
-# if PGM_GST_TYPE == PGM_TYPE_AMD64 || defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
             pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
-# else
-            pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
-# endif
             pPdeDst->u = 0;
             STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
@@ -1683 +1606 @@
     PX86PDE         pPdeDst  = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
 
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     /* Fetch the pgm pool shadow descriptor. */
     PPGMPOOLPAGE    pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
     Assert(pShwPde);
-#  endif
 
 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
-
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     const unsigned  iPDDst  = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
     PPGMPOOLPAGE    pShwPde;
@@ -1703 +1622 @@
     pPDDst             = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
     PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
-#  else
-    const unsigned  iPDDst   = (GCPtrPage >> SHW_PD_SHIFT) /*& SHW_PD_MASK - only pool index atm! */;
-    const unsigned  iPdpt    = (GCPtrPage >> X86_PDPT_SHIFT);
-    PX86PDPT        pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
-    PX86PDEPAE      pPdeDst  = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
-    AssertReturn(pPdeDst, VERR_INTERNAL_ERROR);
-#  endif
+
 # elif PGM_SHW_TYPE == PGM_TYPE_AMD64
     const unsigned  iPDDst   = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
@@ -1963 +1876 @@
      */
     PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
-# if PGM_GST_TYPE == PGM_TYPE_AMD64 || defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
     pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
-# else
-    pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
-# endif
 
     pPdeDst->u = 0;
@@ -2441 +2350 @@
     PSHWPDE         pPdeDst  = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
 
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     /* Fetch the pgm pool shadow descriptor. */
     PPGMPOOLPAGE    pShwPde  = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
     Assert(pShwPde);
-#  endif
 
 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     const unsigned  iPDDst  = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
     PPGMPOOLPAGE    pShwPde;
@@ -2461 +2367 @@
     pPDDst  = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
     pPdeDst = &pPDDst->a[iPDDst];
-#  else
-    const unsigned  iPDDst   = (GCPtrPage >> SHW_PD_SHIFT) /*& SHW_PD_MASK - only pool index atm! */;
-    const unsigned  iPdpt    = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpt);
-    PX86PDPT        pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
-    PSHWPDE         pPdeDst  = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
-#  endif
+
 # elif PGM_SHW_TYPE == PGM_TYPE_AMD64
     const unsigned  iPdpt    = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
@@ -2521 +2422 @@
     Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
 
-# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+# if defined(IN_RC)
     /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
     PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
@@ -2550 +2451 @@
             GCPhys |= (iPDDst & 1) * (PAGE_SIZE / 2);
 # endif
-# if PGM_GST_TYPE == PGM_TYPE_AMD64 || defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
             rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx,      iPDDst, &pShwPage);
-# else
-            rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
-# endif
         }
         else
@@ -2563 +2460 @@
             GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
 # endif
-# if PGM_GST_TYPE == PGM_TYPE_AMD64 || defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
             rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx,      iPDDst, &pShwPage);
-# else
-            rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
-# endif
         }
         if (rc == VINF_SUCCESS)
@@ -2592 +2485 @@
             }
             *pPdeDst = PdeDst;
-# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+# if defined(IN_RC)
             PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
 # endif
@@ -2600 +2493 @@
         {
             VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
-# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+# if defined(IN_RC)
             PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
 # endif
@@ -2633 +2526 @@
                          | (PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
                 *pPdeDst = PdeDst;
-# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+# if defined(IN_RC)
                 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
 # endif
@@ -2739 +2632 @@
             }
             *pPdeDst = PdeDst;
-# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+# if defined(IN_RC)
             PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
 # endif
@@ -2891 +2784 @@
     PSHWPDE         pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
 
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     /* Fetch the pgm pool shadow descriptor. */
     PPGMPOOLPAGE    pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
     Assert(pShwPde);
-#  endif
 
 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     const unsigned  iPDDst  = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
     PPGMPOOLPAGE    pShwPde;
@@ -2911 +2801 @@
     pPDDst  = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
     pPdeDst = &pPDDst->a[iPDDst];
-#  else
-    const unsigned  iPDDst  = (GCPtrPage >> SHW_PD_SHIFT) /*& SHW_PD_MASK - only pool index atm!*/;
-    PX86PDEPAE      pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
-#  endif
 
 # elif PGM_SHW_TYPE == PGM_TYPE_AMD64
@@ -2970 +2856 @@
     /* Virtual address = physical address */
     GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
-# if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_EPT || defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
     rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
-# else
-    rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
-# endif
 
     if (    rc == VINF_SUCCESS
@@ -3032 +2914 @@
 #  elif PGM_GST_TYPE == PGM_TYPE_PAE
     unsigned        iPDSrc;
-#   ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     X86PDPE         PdpeSrc;
     PGSTPD          pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
-#   else
-    PGSTPD          pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
-#   endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
     if (!pPDSrc)
         return VINF_SUCCESS; /* not present */
@@ -3066 +2944 @@
         const X86PDE    PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         const unsigned  iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
         PX86PDPAE       pPDDst;
@@ -3084 +2961 @@
         Assert(pPDDst);
         PdeDst = pPDDst->a[iPDDst];
-#  else
-        const X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
-#  endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
 
 # elif PGM_SHW_TYPE == PGM_TYPE_AMD64
@@ -3177 +3051 @@
 #  elif PGM_GST_TYPE == PGM_TYPE_PAE
     unsigned        iPDSrc;
-#   ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     X86PDPE         PdpeSrc;
     PGSTPD          pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
-#   else
-    PGSTPD          pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
-#   endif
 
     if (pPDSrc)
@@ -3213 +3083 @@
 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
     PX86PDEPAE      pPdeDst;
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     const unsigned  iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
     PX86PDPAE       pPDDst;
@@ -3230 +3099 @@
     Assert(pPDDst);
     pPdeDst = &pPDDst->a[iPDDst];
-#  else
-    pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
-#  endif
+
 # elif PGM_SHW_TYPE == PGM_TYPE_AMD64
     const unsigned  iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
@@ -3409 +3276 @@
 #else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
 
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 #  ifdef PGM_WITHOUT_MAPPINGS
     Assert(pVM->pgm.s.fMappingsFixed);
@@ -3427 +3293 @@
 #  endif
     return VINF_SUCCESS;
-# else
-    /*
-     * PAE and 32-bit legacy mode (shadow).
-     * (Guest PAE, 32-bit legacy, protected and real modes.)
-     */
-    Assert(fGlobal || (cr4 & X86_CR4_PGE));
-    MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Global) : &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3NotGlobal));
-
-# if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE
-    bool const fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
-
-    /*
-     * Get page directory addresses.
-     */
-#  if PGM_SHW_TYPE == PGM_TYPE_32BIT
-    PX86PDE     pPDEDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, 0);
-#  else /* PGM_SHW_TYPE == PGM_TYPE_PAE */
-#   if PGM_GST_TYPE == PGM_TYPE_32BIT
-    PX86PDEPAE  pPDEDst = NULL;
-#   endif
-#  endif
-
-#  if PGM_GST_TYPE == PGM_TYPE_32BIT
-    PGSTPD      pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
-    Assert(pPDSrc);
-#   if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
-    Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == (RTR3PTR)pPDSrc);
-#   endif
-#  endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
-
-    /*
-     * Iterate the the CR3 page.
-     */
-    PPGMMAPPING pMapping;
-    unsigned    iPdNoMapping;
-    const bool  fRawR0Enabled = EMIsRawRing0Enabled(pVM);
-    PPGMPOOL    pPool         = pVM->pgm.s.CTX_SUFF(pPool);
-
-    /* Only check mappings if they are supposed to be put into the shadow page table. */
-    if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
-    {
-        pMapping      = pVM->pgm.s.CTX_SUFF(pMappings);
-        iPdNoMapping  = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
-    }
-    else
-    {
-        pMapping      = 0;
-        iPdNoMapping  = ~0U;
-    }
-
-#  if PGM_GST_TYPE == PGM_TYPE_PAE
-    for (uint64_t iPdpt = 0; iPdpt < GST_PDPE_ENTRIES; iPdpt++)
-    {
-        unsigned        iPDSrc;
-        X86PDPE         PdpeSrc;
-        PGSTPD          pPDSrc    = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT, &iPDSrc, &PdpeSrc);
-        PX86PDEPAE      pPDEDst   = pgmShwGetPaePDEPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT);
-        PX86PDPT        pPdptDst  = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
-
-        if (pPDSrc == NULL)
-        {
-            /* PDPE not present */
-            if (pPdptDst->a[iPdpt].n.u1Present)
-            {
-                LogFlow(("SyncCR3: guest PDPE %lld not present; clear shw pdpe\n", iPdpt));
-                /* for each page directory entry */
-                for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
-                {
-                    if (   pPDEDst[iPD].n.u1Present
-                        && !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
-                    {
-                        pgmPoolFree(pVM, pPDEDst[iPD].u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
-                        pPDEDst[iPD].u = 0;
-                    }
-                }
-            }
-            if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
-                pPdptDst->a[iPdpt].n.u1Present = 0;
-            continue;
-        }
-#  else  /* PGM_GST_TYPE != PGM_TYPE_PAE */
-    {
-#  endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
-        for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
-        {
-#  if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
-            if ((iPD & 255) == 0) /* Start of new PD. */
-                pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)iPD << GST_PD_SHIFT);
-#  endif
-#  if PGM_SHW_TYPE == PGM_TYPE_32BIT
-            Assert(pgmShwGet32BitPDEPtr(&pVM->pgm.s, (uint32_t)iPD << SHW_PD_SHIFT) == pPDEDst);
-#  elif PGM_SHW_TYPE == PGM_TYPE_PAE
-#   if defined(VBOX_STRICT) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* Unfortuantely not reliable with PGMR0DynMap and multiple VMs. */
-            RTGCPTR GCPtrStrict = (uint32_t)iPD << GST_PD_SHIFT;
-#    if PGM_GST_TYPE == PGM_TYPE_PAE
-            GCPtrStrict |= iPdpt << X86_PDPT_SHIFT;
-#    endif
-            AssertMsg(pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrStrict) == pPDEDst, ("%p vs %p (%RGv)\n", pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrStrict), pPDEDst, GCPtrStrict));
-#   endif /* VBOX_STRICT */
-#  endif
-            GSTPDE PdeSrc = pPDSrc->a[iPD];
-            if (    PdeSrc.n.u1Present
-                &&  (PdeSrc.n.u1User || fRawR0Enabled))
-            {
-#  if    (   PGM_GST_TYPE == PGM_TYPE_32BIT \
-          || PGM_GST_TYPE == PGM_TYPE_PAE) \
-      && !defined(PGM_WITHOUT_MAPPINGS)
-
-                /*
-                 * Check for conflicts with GC mappings.
-                 */
-#   if PGM_GST_TYPE == PGM_TYPE_PAE
-                if (iPD + iPdpt * X86_PG_PAE_ENTRIES == iPdNoMapping)
-#   else
-                if (iPD == iPdNoMapping)
-#   endif
-                {
-                    if (pVM->pgm.s.fMappingsFixed)
-                    {
-                        /* It's fixed, just skip the mapping. */
-                        const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
-                        Assert(PGM_GST_TYPE == PGM_TYPE_32BIT || (iPD + cPTs - 1) / X86_PG_PAE_ENTRIES == iPD / X86_PG_PAE_ENTRIES);
-                        iPD += cPTs - 1;
-#   if PGM_SHW_TYPE != PGM_GST_TYPE /* SHW==PAE && GST==32BIT */
-                        pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)(iPD + 1) << GST_PD_SHIFT);
-#   else
-                        pPDEDst += cPTs;
-#   endif
-                        pMapping = pMapping->CTX_SUFF(pNext);
-                        iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
-                        continue;
-                    }
-#   ifdef IN_RING3
-#    if PGM_GST_TYPE == PGM_TYPE_32BIT
-                    int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
-#    elif PGM_GST_TYPE == PGM_TYPE_PAE
-                    int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
-#    endif
-                    if (RT_FAILURE(rc))
-                        return rc;
-
-                    /*
-                     * Update iPdNoMapping and pMapping.
-                     */
-                    pMapping = pVM->pgm.s.pMappingsR3;
-                    while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
-                        pMapping = pMapping->pNextR3;
-                    iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
-#   else  /* !IN_RING3 */
-                    LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
-                    return VINF_PGM_SYNC_CR3;
-#   endif /* !IN_RING3 */
-                }
-#  else  /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) || PGM_WITHOUT_MAPPINGS */
-                Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
-#  endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) || PGM_WITHOUT_MAPPINGS */
-
-                /*
-                 * Sync page directory entry.
-                 *
-                 * The current approach is to allocated the page table but to set
-                 * the entry to not-present and postpone the page table synching till
-                 * it's actually used.
-                 */
-#   if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
-                for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
-#   elif PGM_GST_TYPE == PGM_TYPE_PAE
-                const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
-#   else
-                const unsigned iPdShw = iPD; NOREF(iPdShw);
-#   endif
-                {
-                    SHWPDE PdeDst = *pPDEDst;
-                    if (PdeDst.n.u1Present)
-                    {
-                        PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
-                        RTGCPHYS     GCPhys;
-                        if (    !PdeSrc.b.u1Size
-                            ||  !fBigPagesSupported)
-                        {
-                            GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
-#   if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
-                            /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
-                            GCPhys |= i * (PAGE_SIZE / 2);
-#   endif
-                        }
-                        else
-                        {
-                            GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
-#   if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
-                            /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
-                            GCPhys |= i * X86_PAGE_2M_SIZE;
-#   endif
-                        }
-
-                        if (    pShwPage->GCPhys == GCPhys
-                            &&  pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
-                            &&  (   pShwPage->fCached
-                                || (   !fGlobal
-                                    && (   false
-#   ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
-                                        || (   (PdeSrc.u & (X86_PDE4M_PS | X86_PDE4M_G)) == (X86_PDE4M_PS | X86_PDE4M_G)
-                                            && (cr4 & (X86_CR4_PGE | X86_CR4_PSE)) == (X86_CR4_PGE | X86_CR4_PSE)) /* global 2/4MB page. */
-                                        || (  !pShwPage->fSeenNonGlobal
-                                            && (cr4 & X86_CR4_PGE))
-#   endif
-                                        )
-                                    )
-                                )
-                            &&  (   (PdeSrc.u & (X86_PDE_US | X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US | X86_PDE_RW))
-                                || (   fBigPagesSupported
-                                    &&     ((PdeSrc.u & (X86_PDE_US | X86_PDE4M_PS | X86_PDE4M_D)) | PGM_PDFLAGS_TRACK_DIRTY)
-                                        ==  ((PdeDst.u & (X86_PDE_US | X86_PDE_RW | PGM_PDFLAGS_TRACK_DIRTY)) | X86_PDE4M_PS))
-                                )
-                        )
-                        {
-#   ifdef VBOX_WITH_STATISTICS
-                            if (   !fGlobal
-                                && (PdeSrc.u & (X86_PDE4M_PS | X86_PDE4M_G)) == (X86_PDE4M_PS | X86_PDE4M_G)
-                                && (cr4 & (X86_CR4_PGE | X86_CR4_PSE)) == (X86_CR4_PGE | X86_CR4_PSE))
-                                MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPD));
-                            else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
-                                MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPT));
-                            else
-                                MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstCacheHit));
-#   endif /* VBOX_WITH_STATISTICS */
-    /** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
-    * The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
-    //#  ifdef PGMPOOL_WITH_CACHE
-    //                        pgmPoolCacheUsed(pPool, pShwPage);
-    //#  endif
-                        }
-                        else
-                        {
-                            pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
-                            pPDEDst->u = 0;
-                            MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreed));
-                        }
-                    }
-                    else
-                        MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstNotPresent));
-
-                    /* advance */
-                    pPDEDst++;
-                } /* foreach 2MB PAE PDE in 4MB guest PDE */
-            }
-#  if PGM_GST_TYPE == PGM_TYPE_PAE
-            else if (iPD + iPdpt * X86_PG_PAE_ENTRIES != iPdNoMapping)
-#  else
-            else if (iPD != iPdNoMapping)
-#  endif
-            {
-                /*
-                 * Check if there is any page directory to mark not present here.
-                 */
-#   if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
-                for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
-#   elif PGM_GST_TYPE == PGM_TYPE_PAE
-                const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES;
-#   else
-                const unsigned iPdShw = iPD;
-#   endif
-                {
-                    if (pPDEDst->n.u1Present)
-                    {
-                        pgmPoolFree(pVM, pPDEDst->u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdShw);
-                        pPDEDst->u = 0;
-                        MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreedSrcNP));
-                    }
-                    pPDEDst++;
-                }
-            }
-            else
-            {
-#  if    (   PGM_GST_TYPE == PGM_TYPE_32BIT \
-          || PGM_GST_TYPE == PGM_TYPE_PAE)  \
-      && !defined(PGM_WITHOUT_MAPPINGS)
-
-                const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
-
-                Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
-                if (pVM->pgm.s.fMappingsFixed)
-                {
-                    /* It's fixed, just skip the mapping. */
-                    pMapping = pMapping->CTX_SUFF(pNext);
-                    iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
-                }
-                else
-                {
-                    /*
-                     * Check for conflicts for subsequent pagetables
-                     * and advance to the next mapping.
-                     */
-                    iPdNoMapping = ~0U;
-                    unsigned iPT = cPTs;
-                    while (iPT-- > 1)
-                    {
-                        if (    pPDSrc->a[iPD + iPT].n.u1Present
-                            &&  (pPDSrc->a[iPD + iPT].n.u1User || fRawR0Enabled))
-                        {
-#   ifdef IN_RING3
-#    if PGM_GST_TYPE == PGM_TYPE_32BIT
-                            int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
-#    elif PGM_GST_TYPE == PGM_TYPE_PAE
-                            int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
-#    endif
-                            if (RT_FAILURE(rc))
-                                return rc;
-
-                            /*
-                             * Update iPdNoMapping and pMapping.
-                             */
-                            pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
-                            while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
-                                pMapping = pMapping->CTX_SUFF(pNext);
-                            iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
-                            break;
-#   else
-                            LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
-                            return VINF_PGM_SYNC_CR3;
-#   endif
-                        }
-                    }
-                    if (iPdNoMapping == ~0U && pMapping)
-                    {
-                        pMapping = pMapping->CTX_SUFF(pNext);
-                        if (pMapping)
-                            iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
-                    }
-                }
-
-                /* advance. */
-                Assert(PGM_GST_TYPE == PGM_TYPE_32BIT || (iPD + cPTs - 1) / X86_PG_PAE_ENTRIES == iPD / X86_PG_PAE_ENTRIES);
-                iPD += cPTs - 1;
-#   if PGM_SHW_TYPE != PGM_GST_TYPE /* SHW==PAE && GST==32BIT */
-                pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)(iPD + 1) << GST_PD_SHIFT);
-#   else
-                pPDEDst += cPTs;
-#   endif
-#   if PGM_GST_TYPE != PGM_SHW_TYPE
-                AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
-#   endif
-#  else  /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) || PGM_WITHOUT_MAPPINGS */
-                Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
-#  endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) || PGM_WITHOUT_MAPPINGS */
-            }
-
-        } /* for iPD */
-    } /* for each PDPTE (PAE) */
-    return VINF_SUCCESS;
-
-# else /* guest real and protected mode */
-    return VINF_SUCCESS;
-# endif
-#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
 #endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
 }
@@ -4694 +4205 @@
             pVM->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
 #  endif
-#  ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-            if (!HWACCMIsNestedPagingActive(pVM))
-            {
-                /*
-                 * Update the shadow root page as well since that's not fixed.
-                 */
-                /** @todo Move this into PGMAllBth.h. */
-                PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
-                if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
-                {
-                    /* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
-                    /** @todo Coordinate this better with the pool. */
-                    if (pVM->pgm.s.CTX_SUFF(pShwPageCR3)->enmKind != PGMPOOLKIND_FREE)
-                        pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->GCPhys >> PAGE_SHIFT);
-                    pVM->pgm.s.pShwPageCR3R3 = 0;
-                    pVM->pgm.s.pShwPageCR3R0 = 0;
-                    pVM->pgm.s.pShwRootR3    = 0;
-#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-                    pVM->pgm.s.pShwRootR0    = 0;
-#  endif
-                    pVM->pgm.s.HCPhysShwCR3  = 0;
-                }
-
-                Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
-                rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.CTX_SUFF(pShwPageCR3));
-                if (rc == VERR_PGM_POOL_FLUSHED)
-                {
-                    Log(("MapCR3: PGM pool flushed -> signal sync cr3\n"));
-                    Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
-                    return VINF_PGM_SYNC_CR3;
-                }
-                AssertRCReturn(rc, rc);
-#  ifdef IN_RING0
-                pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
-#  else
-                pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
-#  endif
-                pVM->pgm.s.pShwRootR3    = (R3PTRTYPE(void *))pVM->pgm.s.CTX_SUFF(pShwPageCR3)->pvPageR3;
-                Assert(pVM->pgm.s.pShwRootR3);
-#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-                pVM->pgm.s.pShwRootR0    = (R0PTRTYPE(void *))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwPageCR3));
-#  endif
-                pVM->pgm.s.HCPhysShwCR3  = pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
-                rc = VINF_SUCCESS; /* clear it - pgmPoolAlloc returns hints. */
-            }
-#  endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
 # endif
         }
@@ -4752 +4217 @@
 #endif
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     /* Update shadow paging info for guest modes with paging (32, pae, 64). */
 # if  (   (   PGM_SHW_TYPE == PGM_TYPE_32BIT \
@@ -4838 +4302 @@
 
 # endif
-#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
 
     return rc;
@@ -4884 +4347 @@
     pVM->pgm.s.pGstAmd64Pml4R0 = 0;
 # endif
-# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    if (!HWACCMIsNestedPagingActive(pVM))
-    {
-        pVM->pgm.s.pShwRootR3 = 0;
-#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-        pVM->pgm.s.pShwRootR0 = 0;
-#  endif
-        pVM->pgm.s.HCPhysShwCR3 = 0;
-        if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
-        {
-            PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
-            pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->GCPhys >> PAGE_SHIFT);
-            pVM->pgm.s.pShwPageCR3R3 = 0;
-            pVM->pgm.s.pShwPageCR3R0 = 0;
-        }
-    }
-# endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
 
 #else /* prot/real mode stub */
@@ -4906 +4352 @@
 #endif
 
-#if defined(VBOX_WITH_PGMPOOL_PAGING_ONLY) && !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
+#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
     /* Update shadow paging info. */
 # if  (   (   PGM_SHW_TYPE == PGM_TYPE_32BIT  \
@@ -4939 +4385 @@
     }
 # endif
-#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY && !IN_RC*/
+#endif /* !IN_RC*/
 
     return rc;

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -28 +28 @@
 PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
 PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPDE);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
-PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
-#endif
 PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-# ifndef IN_RING3
-PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
-#  if PGM_GST_TYPE == PGM_TYPE_PAE \
-  || PGM_GST_TYPE == PGM_TYPE_AMD64
-PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
-#  endif
-# endif
-#endif
 __END_DECLS
 
@@ -311 +298 @@
 #endif
 }
-
-
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-
-#undef LOG_GROUP
-#define LOG_GROUP LOG_GROUP_PGM_POOL
-
-/**
- * Registers physical page monitors for the necessary paging
- * structures to detect conflicts with our guest mappings.
- *
- * This is always called after mapping CR3.
- * This is never called with fixed mappings.
- *
- * @returns VBox status, no specials.
- * @param   pVM             VM handle.
- * @param   GCPhysCR3       The physical address in the CR3 register.
- */
-PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
-{
-    Assert(!pVM->pgm.s.fMappingsFixed);
-    int rc = VINF_SUCCESS;
-
-    /*
-     * Register/Modify write phys handler for guest's CR3 if it changed.
-     */
-#if PGM_GST_TYPE == PGM_TYPE_32BIT
-
-    if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
-    {
-# ifndef PGMPOOL_WITH_MIXED_PT_CR3
-        const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
-        if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
-            rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
-        else
-            rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
-                                              pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
-                                              pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
-                                              pVM->pgm.s.pfnRCGstWriteHandlerCR3, 0,
-                                              pVM->pgm.s.pszR3GstWriteHandlerCR3);
-# else  /* PGMPOOL_WITH_MIXED_PT_CR3 */
-        rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool),
-                                         pVM->pgm.s.enmShadowMode == PGMMODE_PAE
-                                      || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
-                                      ? PGMPOOL_IDX_PAE_PD
-                                      : PGMPOOL_IDX_PD,
-                                      GCPhysCR3);
-# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
-        if (RT_FAILURE(rc))
-        {
-            AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
-                             rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
-            return rc;
-        }
-        pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
-    }
-
-#elif PGM_GST_TYPE == PGM_TYPE_PAE
-    /* Monitor the PDPT page */
-    /*
-     * Register/Modify write phys handler for guest's CR3 if it changed.
-     */
-# ifndef PGMPOOL_WITH_MIXED_PT_CR3
-    AssertFailed();
-# endif
-    if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
-    {
-        rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
-        if (RT_FAILURE(rc))
-        {
-            AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
-                             rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
-            return rc;
-        }
-        pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
-    }
-
-    /*
-     * Do the 4 PDs.
-     */
-    PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
-    for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
-    {
-        if (pGuestPDPT->a[i].n.u1Present)
-        {
-            RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
-            if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
-            {
-                Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
-
-                rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
-            }
-
-            if (RT_FAILURE(rc))
-            {
-                AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
-                                 rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
-                return rc;
-            }
-            pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
-        }
-        else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
-        {
-            rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
-            AssertRC(rc);
-            pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
-        }
-    }
-
-#else
-    /* prot/real/amd64 mode stub */
-
-#endif
-    return rc;
-}
-
-/**
- * Deregisters any physical page monitors installed by MonitorCR3.
- *
- * @returns VBox status code, no specials.
- * @param   pVM         The VM handle.
- */
-PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
-{
-    int rc = VINF_SUCCESS;
-
-    /*
-     * Deregister the access handlers.
-     *
-     * PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
-     * before we enter GC again.
-     */
-#if PGM_GST_TYPE == PGM_TYPE_32BIT
-    if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
-    {
-# ifndef PGMPOOL_WITH_MIXED_PT_CR3
-        rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
-        AssertRCReturn(rc, rc);
-# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
-        rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool),
-                                           pVM->pgm.s.enmShadowMode == PGMMODE_PAE
-                                        || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
-                                        ? PGMPOOL_IDX_PAE_PD
-                                        : PGMPOOL_IDX_PD);
-        AssertRCReturn(rc, rc);
-# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
-        pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
-    }
-
-#elif PGM_GST_TYPE == PGM_TYPE_PAE
-    /* The PDPT page */
-# ifndef PGMPOOL_WITH_MIXED_PT_CR3
-    AssertFailed();
-# endif
-
-    if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
-    {
-        rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PDPT);
-        AssertRC(rc);
-    }
-
-    /* The 4 PDs. */
-    for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
-    {
-        if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
-        {
-            Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
-            int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
-            AssertRC(rc2);
-            if (RT_FAILURE(rc2))
-                rc = rc2;
-            pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
-        }
-    }
-#else
-    /* prot/real/amd64 mode stub */
-#endif
-    return rc;
-
-}
-
-#undef LOG_GROUP
-#define LOG_GROUP LOG_GROUP_PGM
-
-#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
 
 
@@ -704 +506 @@
 }
 
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-
-#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
-
-/**
- * Write access handler for the Guest CR3 page in 32-bit mode.
- *
- * This will try interpret the instruction, if failure fail back to the recompiler.
- * Check if the changed PDEs are marked present and conflicts with our
- * mappings. If conflict, we'll switch to the host context and resolve it there
- *
- * @returns VBox status code (appropritate for trap handling and GC return).
- * @param   pVM         VM Handle.
- * @param   uErrorCode  CPU Error code.
- * @param   pRegFrame   Trap register frame.
- * @param   pvFault     The fault address (cr2).
- * @param   GCPhysFault The GC physical address corresponding to pvFault.
- * @param   pvUser      User argument.
- */
-PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
-{
-    AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
-
-    /*
-     * Try interpret the instruction.
-     */
-    uint32_t cb;
-    int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
-    if (RT_SUCCESS(rc) && cb)
-    {
-        /*
-         * Check if the modified PDEs are present and mappings.
-         */
-        const RTGCPTR   offPD = GCPhysFault & PAGE_OFFSET_MASK;
-        const unsigned  iPD1  = offPD / sizeof(X86PDE);
-        const unsigned  iPD2  = (offPD + cb - 1) / sizeof(X86PDE);
-
-        Assert(cb > 0 && cb <= 8);
-        Assert(iPD1 < X86_PG_ENTRIES);
-        Assert(iPD2 < X86_PG_ENTRIES);
-
-#ifdef DEBUG
-        Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%x\n", iPD1, iPD1 << X86_PD_SHIFT));
-        if (iPD1 != iPD2)
-            Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%x\n", iPD2, iPD2 << X86_PD_SHIFT));
-#endif
-
-        if (!pVM->pgm.s.fMappingsFixed)
-        {
-            PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
-            if (    (   pPDSrc->a[iPD1].n.u1Present
-                     && pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
-                ||  (   iPD1 != iPD2
-                     && pPDSrc->a[iPD2].n.u1Present
-                     && pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
-               )
-            {
-                STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteConflict);
-                VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
-                if (rc == VINF_SUCCESS)
-                    rc = VINF_PGM_SYNC_CR3;
-                Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
-                return rc;
-            }
-        }
-
-        STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
-    }
-    else
-    {
-        Assert(RT_FAILURE(rc));
-        if (rc == VERR_EM_INTERPRETER)
-            rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
-        Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
-        STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
-    }
-    return rc;
-}
-
-#endif /* PGM_TYPE_32BIT && !IN_RING3 */
-#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
-
-/**
- * Write access handler for the Guest CR3 page in PAE mode.
- *
- * This will try interpret the instruction, if failure fail back to the recompiler.
- * Check if the changed PDEs are marked present and conflicts with our
- * mappings. If conflict, we'll switch to the host context and resolve it there
- *
- * @returns VBox status code (appropritate for trap handling and GC return).
- * @param   pVM         VM Handle.
- * @param   uErrorCode  CPU Error code.
- * @param   pRegFrame   Trap register frame.
- * @param   pvFault     The fault address (cr2).
- * @param   GCPhysFault The GC physical address corresponding to pvFault.
- * @param   pvUser      User argument.
- */
-PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
-{
-    AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
-
-    /*
-     * Try interpret the instruction.
-     */
-    uint32_t cb;
-    int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
-    if (RT_SUCCESS(rc) && cb)
-    {
-        /*
-         * Check if any of the PDs have changed.
-         * We'll simply check all of them instead of figuring out which one/two to check.
-         */
-        PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
-        for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
-        {
-            if (    pGuestPDPT->a[i].n.u1Present
-                &&      (pGuestPDPT->a[i].u & X86_PDPE_PG_MASK)
-                    !=  pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
-            {
-                /*
-                 * The PDPE has changed.
-                 * We will schedule a monitoring update for the next TLB Flush,
-                 * InvalidatePage or SyncCR3.
-                 *
-                 * This isn't perfect, because a lazy page sync might be dealing with an half
-                 * updated PDPE. However, we assume that the guest OS is disabling interrupts
-                 * and being extremely careful (cmpxchg8b) when updating a PDPE where it's
-                 * executing.
-                 */
-                pVM->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
-                Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%RGp\n",
-                     i, pGuestPDPT->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
-            }
-        }
-
-        STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
-    }
-    else
-    {
-        Assert(RT_FAILURE(rc));
-        STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
-        if (rc == VERR_EM_INTERPRETER)
-            rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
-    }
-    Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
-    return rc;
-}
-
-
-/**
- * Write access handler for the Guest PDs in PAE mode.
- *
- * This will try interpret the instruction, if failure fail back to the recompiler.
- * Check if the changed PDEs are marked present and conflicts with our
- * mappings. If conflict, we'll switch to the host context and resolve it there
- *
- * @returns VBox status code (appropritate for trap handling and GC return).
- * @param   pVM         VM Handle.
- * @param   uErrorCode  CPU Error code.
- * @param   pRegFrame   Trap register frame.
- * @param   pvFault     The fault address (cr2).
- * @param   GCPhysFault The GC physical address corresponding to pvFault.
- * @param   pvUser      User argument.
- */
-PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
-{
-    AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
-
-    /*
-     * Try interpret the instruction.
-     */
-    uint32_t cb;
-    int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
-    if (RT_SUCCESS(rc) && cb)
-    {
-        /*
-         * Figure out which of the 4 PDs this is.
-         */
-        RTGCPTR i;
-        PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
-        for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
-            if (pGuestPDPT->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
-            {
-                PX86PDPAE       pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
-                const RTGCPTR   offPD  = GCPhysFault & PAGE_OFFSET_MASK;
-                const unsigned  iPD1   = offPD / sizeof(X86PDEPAE);
-                const unsigned  iPD2   = (offPD + cb - 1) / sizeof(X86PDEPAE);
-
-                Assert(cb > 0 && cb <= 8);
-                Assert(iPD1 < X86_PG_PAE_ENTRIES);
-                Assert(iPD2 < X86_PG_PAE_ENTRIES);
-
-# ifdef LOG_ENABLED
-                Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%x)\n",
-                     i, iPD1, (i << X86_PDPT_SHIFT) | (iPD1 << X86_PD_PAE_SHIFT)));
-                if (iPD1 != iPD2)
-                    Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%x)\n",
-                         i, iPD2, (i << X86_PDPT_SHIFT) | (iPD2 << X86_PD_PAE_SHIFT)));
-# endif
-
-                if (!pVM->pgm.s.fMappingsFixed)
-                {
-                    if (    (   pPDSrc->a[iPD1].n.u1Present
-                             && pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) | (iPD1 << X86_PD_PAE_SHIFT))) )
-                        ||  (   iPD1 != iPD2
-                             && pPDSrc->a[iPD2].n.u1Present
-                             && pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) | (iPD2 << X86_PD_PAE_SHIFT))) )
-                       )
-                    {
-                        Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
-                        STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteConflict);
-                        VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
-                        return VINF_PGM_SYNC_CR3;
-                    }
-                }
-                break; /* ASSUMES no duplicate entries... */
-            }
-        Assert(i < 4);
-
-        STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
-    }
-    else
-    {
-        Assert(RT_FAILURE(rc));
-        if (rc == VERR_EM_INTERPRETER)
-            rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
-        else
-            Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
-        STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
-    }
-    return rc;
-}
-
-#endif /* PGM_TYPE_PAE && !IN_RING3 */
-
-#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */

trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp

@@ -224 +224 @@
         return;
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     if (!pVM->pgm.s.CTX_SUFF(pShwPageCR3))
         return;    /* too early */
-#endif
 
     PGMMODE enmShadowMode = PGMGetShadowMode(pVM);
@@ -272 +270 @@
                 Assert(pShwPdpt);
                 pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, (iPdPt << X86_PDPT_SHIFT));
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 if (!pShwPaePd)
                 {
@@ -299 +296 @@
                     }
                 }
-#endif
                 AssertFatal(pShwPaePd);
 
@@ -305 +301 @@
                 AssertFatal(pPoolPagePd);
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 if (!pgmPoolIsPageLocked(&pVM->pgm.s, pPoolPagePd))
                 {
@@ -328 +323 @@
                 }
 
-#else
-                if (pShwPaePd->a[iPDE].n.u1Present)
-                {
-                    Assert(!(pShwPaePd->a[iPDE].u & PGM_PDFLAGS_MAPPING));
-                    pgmPoolFree(pVM, pShwPaePd->a[iPDE].u & X86_PDE_PG_MASK, pPoolPagePd->idx, iNewPDE);
-                }
-#endif
                 X86PDEPAE PdePae0;
                 PdePae0.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0;
@@ -343 +331 @@
                 AssertFatal(iPDE < 512);
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 if (    pShwPaePd->a[iPDE].n.u1Present
                     &&  !(pShwPaePd->a[iPDE].u & PGM_PDFLAGS_MAPPING))
@@ -349 +336 @@
                     pgmPoolFree(pVM, pShwPaePd->a[iPDE].u & X86_PDE_PG_MASK, pPoolPagePd->idx, iPDE);
                 }
-#else
-                if (pShwPaePd->a[iPDE].n.u1Present)
-                {
-                    Assert(!(pShwPaePd->a[iPDE].u & PGM_PDFLAGS_MAPPING));
-                    pgmPoolFree(pVM, pShwPaePd->a[iPDE].u & X86_PDE_PG_MASK, pPoolPagePd->idx, iNewPDE);
-                }
-#endif
                 X86PDEPAE PdePae1;
                 PdePae1.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1;
@@ -387 +367 @@
         return;
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     Assert(pShwPageCR3);
 # ifdef IN_RC
@@ -400 +379 @@
         pCurrentShwPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
     }
-#endif
 
     unsigned i = pMap->cPTs;
@@ -414 +392 @@
             case PGMMODE_32_BIT:
             {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
-#else
-                PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVM->pgm.s);
-#endif
                 AssertFatal(pShw32BitPd);
 
@@ -434 +408 @@
                 const unsigned iPdpt = iOldPDE / 256;         /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
                 unsigned iPDE = iOldPDE * 2 % 512;
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 pShwPdpt  = (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
                 pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, pShwPdpt, (iPdpt << X86_PDPT_SHIFT));
@@ -444 +417 @@
                         break;
                 }
-#else
-                pShwPdpt  = pgmShwGetPaePDPTPtr(&pVM->pgm.s); 
-                pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, (iPdpt << X86_PDPT_SHIFT)); 
-#endif
                 AssertFatal(pShwPaePd);
 
@@ -461 +430 @@
                 pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPageByHCPhys(pVM, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
                 AssertFatal(pPoolPagePd);
@@ -470 +438 @@
                     pgmPoolUnlockPage(pVM->pgm.s.CTX_SUFF(pPool), pPoolPagePd);
                 }
-#endif
-
                 break;
             }
@@ -494 +460 @@
 void pgmMapCheckShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iPDE)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     Assert(pShwPageCR3);
-#endif
 
     unsigned i = pMap->cPTs;
@@ -510 +474 @@
             case PGMMODE_32_BIT:
             {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
-#else
-                PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVM->pgm.s);
-#endif
                 AssertFatal(pShw32BitPd);
 
@@ -530 +490 @@
                 const unsigned iPD = iPDE / 256;         /* iPDE * 2 / 512; iPDE is in 4 MB pages */
                 unsigned iPaePDE = iPDE * 2 % 512;
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 pPdpt     = (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
                 pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, pPdpt, (iPD << X86_PDPT_SHIFT));
-#else
-                pPdpt     = pgmShwGetPaePDPTPtr(&pVM->pgm.s); 
-                pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, (iPD << X86_PDPT_SHIFT)); 
-#endif
                 AssertFatal(pShwPaePd);
 
@@ -566 +521 @@
 VMMDECL(void) PGMMapCheck(PVM pVM)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     /*
      * Can skip this if mappings are disabled.
@@ -573 +527 @@
         return;
 
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
-#  endif
 
     /*
@@ -586 +538 @@
         pgmMapCheckShadowPDEs(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pCur, iPDE);
     }
-#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
 }
 #endif /* defined(VBOX_STRICT) && !defined(IN_RING0) */
@@ -600 +551 @@
 int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     /*
      * Can skip this if mappings are disabled.
      */
     if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
-#else
-    /*
-     * Can skip this if mappings are safely fixed.
-     */
-    if (pVM->pgm.s.fMappingsFixed)
-#endif
         return VINF_SUCCESS;
 
@@ -616 +560 @@
     Log4(("PGMMapActivateAll fixed mappings=%d\n", pVM->pgm.s.fMappingsFixed));
 
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     Assert(pShwPageCR3 && pShwPageCR3 == pVM->pgm.s.CTX_SUFF(pShwPageCR3));
-# endif
 
     /*
@@ -642 +584 @@
 int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
 {
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     /*
      * Can skip this if mappings are disabled.
      */
     if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
-#else
-    /*
-     * Can skip this if mappings are safely fixed.
-     */
-    if (pVM->pgm.s.fMappingsFixed)
-#endif
         return VINF_SUCCESS;
 
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     Assert(pShwPageCR3);
-# endif
 
     /*
@@ -762 +695 @@
 }
 
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 /**
  * Checks and resolves (ring 3 only) guest conflicts with VMM GC mappings.
@@ -878 +810 @@
     return VINF_SUCCESS;
 }
-# endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
 
 #endif /* IN_RING0 */

trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

@@ -136 +136 @@
 # define PGMPOOL_UNLOCK_PTR(pVM, pPage)  do {} while (0)
 #endif
-
-#if !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY) && (defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0))
-/**
- * Maps a pool page into the current context.
- *
- * @returns Pointer to the mapping.
- * @param   pPGM    Pointer to the PGM instance data.
- * @param   pPage   The page to map.
- */
-void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage)
-{
-    /* general pages are take care of by the inlined part, it
-       only ends up here in case of failure. */
-    AssertReleaseReturn(pPage->idx < PGMPOOL_IDX_FIRST, NULL);
-
-/** @todo make sure HCPhys is valid for *all* indexes. */
-    /* special pages. */
-# ifdef IN_RC
-    switch (pPage->idx)
-    {
-        case PGMPOOL_IDX_PD:
-            return pPGM->pShw32BitPdRC;
-        case PGMPOOL_IDX_PAE_PD:
-        case PGMPOOL_IDX_PAE_PD_0:
-            return pPGM->apShwPaePDsRC[0];
-        case PGMPOOL_IDX_PAE_PD_1:
-            return pPGM->apShwPaePDsRC[1];
-        case PGMPOOL_IDX_PAE_PD_2:
-            return pPGM->apShwPaePDsRC[2];
-        case PGMPOOL_IDX_PAE_PD_3:
-            return pPGM->apShwPaePDsRC[3];
-        case PGMPOOL_IDX_PDPT:
-            return pPGM->pShwPaePdptRC;
-        default:
-            AssertReleaseMsgFailed(("Invalid index %d\n", pPage->idx));
-            return NULL;
-    }
-
-# else  /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
-    RTHCPHYS HCPhys;
-    switch (pPage->idx)
-    {
-        case PGMPOOL_IDX_PD:
-            HCPhys = pPGM->HCPhysShw32BitPD;
-            break;
-        case PGMPOOL_IDX_PAE_PD_0:
-            HCPhys = pPGM->aHCPhysPaePDs[0];
-            break;
-        case PGMPOOL_IDX_PAE_PD_1:
-            HCPhys = pPGM->aHCPhysPaePDs[1];
-            break;
-        case PGMPOOL_IDX_PAE_PD_2:
-            HCPhys = pPGM->aHCPhysPaePDs[2];
-            break;
-        case PGMPOOL_IDX_PAE_PD_3:
-            HCPhys = pPGM->aHCPhysPaePDs[3];
-            break;
-        case PGMPOOL_IDX_PDPT:
-            HCPhys = pPGM->HCPhysShwPaePdpt;
-            break;
-        case PGMPOOL_IDX_NESTED_ROOT:
-            HCPhys = pPGM->HCPhysShwNestedRoot;
-            break;
-        case PGMPOOL_IDX_PAE_PD:
-            AssertReleaseMsgFailed(("PGMPOOL_IDX_PAE_PD is not usable in VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 context\n"));
-            return NULL;
-        default:
-            AssertReleaseMsgFailed(("Invalid index %d\n", pPage->idx));
-            return NULL;
-    }
-    AssertMsg(HCPhys && HCPhys != NIL_RTHCPHYS && !(PAGE_OFFSET_MASK & HCPhys), ("%RHp\n", HCPhys));
-
-    void *pv;
-    pgmR0DynMapHCPageInlined(pPGM, HCPhys, &pv);
-    return pv;
-# endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
-}
-#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
 
 
@@ -388 +310 @@
             }
 
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
             case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
             case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
@@ -457 +378 @@
                 break;
             }
-# endif
-
 
             case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
@@ -508 +427 @@
             }
 
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
             case PGMPOOLKIND_32BIT_PD:
-#  else
-            case PGMPOOLKIND_ROOT_32BIT_PD:
-#  endif
             {
                 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
                 const unsigned iShw = off / sizeof(X86PTE);         // ASSUMING 32-bit guest paging!
 
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
-#  endif
 #  ifndef IN_RING0
                 if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
@@ -530 +443 @@
                 }
 #  endif /* !IN_RING0 */
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 #   ifndef IN_RING0
                 else
@@ -545 +457 @@
                     }
                 }
-#  endif
                 /* paranoia / a bit assumptive. */
                 if (   pCpu
@@ -564 +475 @@
                         }
 #  endif /* !IN_RING0 */
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 #   ifndef IN_RING0
                         else
@@ -579 +489 @@
                             }
                         }
-#  endif
                     }
                 }
@@ -596 +505 @@
                 break;
             }
-
-# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-            case PGMPOOLKIND_ROOT_PAE_PD:
-            {
-                unsigned iGst     = off / sizeof(X86PDE);           // ASSUMING 32-bit guest paging!
-                unsigned iShwPdpt = iGst / 256;
-                unsigned iShw     = (iGst % 256) * 2;
-                Assert(pPage->idx == PGMPOOL_IDX_PAE_PD);
-                PPGMPOOLPAGE pPage2 = pPage + 1 + iShwPdpt;
-                Assert(pPage2->idx == PGMPOOL_IDX_PAE_PD_0 + iShwPdpt);
-                uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage2);
-                for (unsigned i = 0; i < 2; i++, iShw++)
-                {
-                    if ((uShw.pPDPae->a[iShw].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
-                    {
-                        Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
-                        VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
-                        LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw));
-                    }
-                    /* paranoia / a bit assumptive. */
-                    else if (   pCpu
-                             && (off & 3)
-                             && (off & 3) + cbWrite > 4)
-                    {
-                        const unsigned iShw2 = iShw + 2;
-                        if (    iShw2 < RT_ELEMENTS(uShw.pPDPae->a) /** @todo was completely wrong, it's better now after #1865 but still wrong from cross PD. */
-                            &&  (uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
-                        {
-                            Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
-                            VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
-                            LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
-                        }
-                    }
-#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
-                    if (    uShw.pPDPae->a[iShw].n.u1Present
-                        &&  !VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
-                    {
-                        LogFlow(("pgmPoolMonitorChainChanging: iShwPdpt=%#x iShw=%#x: %RX64 -> freeing it!\n", iShwPdpt, iShw, uShw.pPDPae->a[iShw].u));
-# ifdef IN_RC           /* TLB load - we're pushing things a bit... */
-                        ASMProbeReadByte(pvAddress);
-# endif
-                        pgmPoolFree(pVM, uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK, pPage->idx, iShw + iShwPdpt * X86_PG_PAE_ENTRIES);
-                        uShw.pPDPae->a[iShw].u = 0;
-                    }
-#endif
-                }
-                break;
-            }
-#  endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
 
             case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
@@ -660 +520 @@
                 }
 #endif /* !IN_RING0 */
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 /*
                  * Causes trouble when the guest uses a PDE to refer to the whole page table level
@@ -675 +534 @@
                         pgmPoolFree(pVM,
                                     uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                                     pPage->idx,
                                     iShw);
-# else
-                                    /* Note: hardcoded PAE implementation dependency */
-                                    (pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD) ? PGMPOOL_IDX_PAE_PD : pPage->idx,
-                                    (pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD) ? iShw + (pPage->idx - PGMPOOL_IDX_PAE_PD_0) * X86_PG_PAE_ENTRIES : iShw);
-# endif
                         uShw.pPDPae->a[iShw].u = 0;
                     }
                 }
-#endif
                 /* paranoia / a bit assumptive. */
                 if (   pCpu
@@ -705 +557 @@
                     }
 #endif /* !IN_RING0 */
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 # ifndef IN_RING0
                     else
@@ -714 +565 @@
                         pgmPoolFree(pVM,
                                     uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                                     pPage->idx,
                                     iShw2);
-# else
-                                    /* Note: hardcoded PAE implementation dependency */
-                                    (pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD) ? PGMPOOL_IDX_PAE_PD : pPage->idx,
-                                    (pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD) ? iShw2 + (pPage->idx - PGMPOOL_IDX_PAE_PD_0) * X86_PG_PAE_ENTRIES : iShw2);
-# endif
                         uShw.pPDPae->a[iShw2].u = 0;
                     }
-#endif
                 }
                 break;
             }
 
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
             case PGMPOOLKIND_PAE_PDPT:
-#  else
-            case PGMPOOLKIND_ROOT_PDPT:
-#  endif
             {
                 /*
@@ -740 +580 @@
                  * - messing with the bits of pd pointers without changing the physical address
                  */
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 /* PDPT roots are not page aligned; 32 byte only! */
                 const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
-# else
-                const unsigned offPdpt = off;
-# endif
+
                 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
                 const unsigned iShw = offPdpt / sizeof(X86PDPE);
@@ -760 +597 @@
                     }
 # endif /* !IN_RING0 */
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 #  ifndef IN_RING0
                     else
@@ -773 +609 @@
                         uShw.pPDPT->a[iShw].u = 0;
                     }
-# endif
 
                     /* paranoia / a bit assumptive. */
@@ -793 +628 @@
                             }
 # endif /* !IN_RING0 */
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 #  ifndef IN_RING0
                             else
@@ -806 +640 @@
                                 uShw.pPDPT->a[iShw2].u = 0;
                             }
-# endif
                         }
                     }
@@ -856 +689 @@
                  * - messing with the bits of pd pointers without changing the physical address
                  */
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
-# endif
                 {
                     uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
@@ -891 +722 @@
                  * - messing with the bits of pd pointers without changing the physical address
                  */
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
-# endif
                 {
                     uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
@@ -1282 +1111 @@
     bool fReused = false;
     if (    (   pPage->cModifications < 48   /** @todo #define */ /** @todo need to check that it's not mapping EIP. */ /** @todo adjust this! */
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
              || pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
-#else
-             || pPage->fCR3Mix
-#endif
             )
         &&  !(fReused = pgmPoolMonitorIsReused(pVM, pPage, pRegFrame, &Cpu, pvFault))
@@ -1445 +1270 @@
      * Reject any attempts at flushing the currently active shadow CR3 mapping
      */
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     if (pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
-#else
-    if (PGMGetHyperCR3(pPool->CTX_SUFF(pVM)) == pPage->Core.Key)
-#endif
     {
         /* Refresh the cr3 mapping by putting it at the head of the age list. */
@@ -1490 +1311 @@
         case PGMPOOLKIND_EPT_PD_FOR_PHYS:
         case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
             return false;
-#else
-            return true;
-#endif
 
         /*
@@ -1564 +1381 @@
          * These cannot be flushed, and it's common to reuse the PDs as PTs.
          */
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        case PGMPOOLKIND_ROOT_32BIT_PD:
-        case PGMPOOLKIND_ROOT_PAE_PD:
-        case PGMPOOLKIND_ROOT_PDPT:
-#endif
         case PGMPOOLKIND_ROOT_NESTED:
             return false;
@@ -1770 +1582 @@
                 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
                 case PGMPOOLKIND_64BIT_PML4:
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 case PGMPOOLKIND_32BIT_PD:
                 case PGMPOOLKIND_PAE_PDPT:
-#else
-                case PGMPOOLKIND_ROOT_32BIT_PD:
-                case PGMPOOLKIND_ROOT_PAE_PD:
-                case PGMPOOLKIND_ROOT_PDPT:
-#endif
                 {
                     /* find the head */
@@ -1803 +1609 @@
                 case PGMPOOLKIND_PAE_PDPT_PHYS:
                 case PGMPOOLKIND_32BIT_PD_PHYS:
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
-#endif
                     break;
                 default:
@@ -1845 +1649 @@
         case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
         case PGMPOOLKIND_64BIT_PML4:
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
         case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
@@ -1852 +1655 @@
         case PGMPOOLKIND_32BIT_PD:
         case PGMPOOLKIND_PAE_PDPT:
-#else
-        case PGMPOOLKIND_ROOT_PDPT:
-#endif
             break;
 
@@ -1871 +1671 @@
             return VINF_SUCCESS;
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         case PGMPOOLKIND_32BIT_PD_PHYS:
         case PGMPOOLKIND_PAE_PDPT_PHYS:
@@ -1878 +1677 @@
             /* Nothing to monitor here. */
             return VINF_SUCCESS;
-#else
-        case PGMPOOLKIND_ROOT_32BIT_PD:
-        case PGMPOOLKIND_ROOT_PAE_PD:
-#endif
 #ifdef PGMPOOL_WITH_MIXED_PT_CR3
             break;
@@ -1952 +1747 @@
         case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
         case PGMPOOLKIND_64BIT_PML4:
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         case PGMPOOLKIND_32BIT_PD:
         case PGMPOOLKIND_PAE_PDPT:
@@ -1959 +1753 @@
         case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
         case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
-#else
-        case PGMPOOLKIND_ROOT_PDPT:
-#endif
             break;
 
@@ -1981 +1772 @@
             return VINF_SUCCESS;
 
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        case PGMPOOLKIND_ROOT_32BIT_PD:
-        case PGMPOOLKIND_ROOT_PAE_PD:
-#endif
 #ifdef PGMPOOL_WITH_MIXED_PT_CR3
             break;
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
 #endif
         default:
@@ -2007 +1791 @@
             PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
             pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-            pNewHead->fCR3Mix = pPage->fCR3Mix;
-#endif
             rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
                                                    pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
@@ -2047 +1828 @@
 }
 
-# if defined(PGMPOOL_WITH_MIXED_PT_CR3) && !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
-
-/**
- * Set or clear the fCR3Mix attribute in a chain of monitored pages.
- *
- * @param   pPool       The Pool.
- * @param   pPage       A page in the chain.
- * @param   fCR3Mix     The new fCR3Mix value.
- */
-static void pgmPoolMonitorChainChangeCR3Mix(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCR3Mix)
-{
-    /* current */
-    pPage->fCR3Mix = fCR3Mix;
-
-    /* before */
-    int16_t idx = pPage->iMonitoredPrev;
-    while (idx != NIL_PGMPOOL_IDX)
-    {
-        pPool->aPages[idx].fCR3Mix = fCR3Mix;
-        idx = pPool->aPages[idx].iMonitoredPrev;
-    }
-
-    /* after */
-    idx = pPage->iMonitoredNext;
-    while (idx != NIL_PGMPOOL_IDX)
-    {
-        pPool->aPages[idx].fCR3Mix = fCR3Mix;
-        idx = pPool->aPages[idx].iMonitoredNext;
-    }
-}
-
-
-/**
- * Installs or modifies monitoring of a CR3 page (special).
- *
- * We're pretending the CR3 page is shadowed by the pool so we can use the
- * generic mechanisms in detecting chained monitoring. (This also gives us a
- * tast of what code changes are required to really pool CR3 shadow pages.)
- *
- * @returns VBox status code.
- * @param   pPool       The pool.
- * @param   idxRoot     The CR3 (root) page index.
- * @param   GCPhysCR3   The (new) CR3 value.
- */
-int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3)
-{
-    Assert(idxRoot != NIL_PGMPOOL_IDX && idxRoot < PGMPOOL_IDX_FIRST);
-    PPGMPOOLPAGE pPage = &pPool->aPages[idxRoot];
-    LogFlow(("pgmPoolMonitorMonitorCR3: idxRoot=%d pPage=%p:{.GCPhys=%RGp, .fMonitored=%d} GCPhysCR3=%RGp\n",
-             idxRoot, pPage, pPage->GCPhys, pPage->fMonitored, GCPhysCR3));
-
-    /*
-     * The unlikely case where it already matches.
-     */
-    if (pPage->GCPhys == GCPhysCR3)
-    {
-        Assert(pPage->fMonitored);
-        return VINF_SUCCESS;
-    }
-
-    /*
-     * Flush the current monitoring and remove it from the hash.
-     */
-    int rc = VINF_SUCCESS;
-    if (pPage->fMonitored)
-    {
-        pgmPoolMonitorChainChangeCR3Mix(pPool, pPage, false);
-        rc = pgmPoolMonitorFlush(pPool, pPage);
-        if (rc == VERR_PGM_POOL_CLEARED)
-            rc = VINF_SUCCESS;
-        else
-            AssertFatalRC(rc);
-        pgmPoolHashRemove(pPool, pPage);
-    }
-
-    /*
-     * Monitor the page at the new location and insert it into the hash.
-     */
-    pPage->GCPhys = GCPhysCR3;
-    int rc2 = pgmPoolMonitorInsert(pPool, pPage);
-    if (rc2 != VERR_PGM_POOL_CLEARED)
-    {
-        AssertFatalRC(rc2);
-        if (rc2 != VINF_SUCCESS && rc == VINF_SUCCESS)
-            rc = rc2;
-    }
-    pgmPoolHashInsert(pPool, pPage);
-    pgmPoolMonitorChainChangeCR3Mix(pPool, pPage, true);
-    return rc;
-}
-
-
-/**
- * Removes the monitoring of a CR3 page (special).
- *
- * @returns VBox status code.
- * @param   pPool       The pool.
- * @param   idxRoot     The CR3 (root) page index.
- */
-int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot)
-{
-    Assert(idxRoot != NIL_PGMPOOL_IDX && idxRoot < PGMPOOL_IDX_FIRST);
-    PPGMPOOLPAGE pPage = &pPool->aPages[idxRoot];
-    LogFlow(("pgmPoolMonitorUnmonitorCR3: idxRoot=%d pPage=%p:{.GCPhys=%RGp, .fMonitored=%d}\n",
-             idxRoot, pPage, pPage->GCPhys, pPage->fMonitored));
-
-    if (!pPage->fMonitored)
-        return VINF_SUCCESS;
-
-    pgmPoolMonitorChainChangeCR3Mix(pPool, pPage, false);
-    int rc = pgmPoolMonitorFlush(pPool, pPage);
-    if (rc != VERR_PGM_POOL_CLEARED)
-        AssertFatalRC(rc);
-    else
-        rc = VINF_SUCCESS;
-    pgmPoolHashRemove(pPool, pPage);
-    Assert(!pPage->fMonitored);
-    pPage->GCPhys = NIL_RTGCPHYS;
-    return rc;
-}
-
-# endif /* PGMPOOL_WITH_MIXED_PT_CR3 && !VBOX_WITH_PGMPOOL_PAGING_ONLY*/
 
 /**
@@ -2713 +2372 @@
         case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
         case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         case PGMPOOLKIND_32BIT_PD:
         case PGMPOOLKIND_32BIT_PD_PHYS:
-#else
-        case PGMPOOLKIND_ROOT_32BIT_PD:
-#endif
             return 4;
 
@@ -2734 +2389 @@
         case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
         case PGMPOOLKIND_64BIT_PML4:
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        case PGMPOOLKIND_ROOT_PAE_PD:
-        case PGMPOOLKIND_ROOT_PDPT:
-#endif
         case PGMPOOLKIND_PAE_PDPT:
         case PGMPOOLKIND_ROOT_NESTED:
@@ -2770 +2421 @@
         case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
         case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         case PGMPOOLKIND_32BIT_PD:
-#else
-        case PGMPOOLKIND_ROOT_32BIT_PD:
-#endif
         case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
         case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
@@ -2789 +2436 @@
         case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
         case PGMPOOLKIND_64BIT_PML4:
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         case PGMPOOLKIND_PAE_PDPT:
-#else
-        case PGMPOOLKIND_ROOT_PAE_PD:
-        case PGMPOOLKIND_ROOT_PDPT:
-#endif
             return 8;
 
@@ -3201 +2843 @@
      */
     PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
-#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) && !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
-    if (pUserPage->enmKind == PGMPOOLKIND_ROOT_PAE_PD)
-    {
-        /* Must translate the fake 2048 entry PD to a 512 PD one since the R0 mapping is not linear. */
-        Assert(pUser->iUser == PGMPOOL_IDX_PAE_PD);
-        uint32_t iPdpt = iUserTable / X86_PG_PAE_ENTRIES;
-        iUserTable    %= X86_PG_PAE_ENTRIES;
-        pUserPage      = &pPool->aPages[PGMPOOL_IDX_PAE_PD_0 + iPdpt];
-        Assert(pUserPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD);
-    }
-#endif
     union
     {
@@ -3222 +2853 @@
 
     /* Safety precaution in case we change the paging for other modes too in the future. */
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
-#else
-    Assert(PGMGetHyperCR3(pPool->CTX_SUFF(pVM)) != pPage->Core.Key);
-#endif
 
 #ifdef VBOX_STRICT
@@ -3234 +2861 @@
     switch (pUserPage->enmKind)
     {
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         case PGMPOOLKIND_32BIT_PD:
             case PGMPOOLKIND_32BIT_PD_PHYS:
             Assert(iUserTable < X86_PG_ENTRIES);
             break;
-# else
-        case PGMPOOLKIND_ROOT_32BIT_PD:
-            Assert(iUserTable < X86_PG_ENTRIES);
-            Assert(!(u.pau32[iUserTable] & PGM_PDFLAGS_MAPPING));
-            break;
-# endif
-# if !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) && !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
-        case PGMPOOLKIND_ROOT_PAE_PD:
-            Assert(iUserTable < 2048 && pUser->iUser == PGMPOOL_IDX_PAE_PD);
-            AssertMsg(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING), ("%llx %d\n", u.pau64[iUserTable], iUserTable));
-            break;
-# endif
-# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         case PGMPOOLKIND_PAE_PDPT:
         case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
         case PGMPOOLKIND_PAE_PDPT_PHYS:
-# else
-        case PGMPOOLKIND_ROOT_PDPT:
-# endif
             Assert(iUserTable < 4);
             Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
@@ -3307 +2917 @@
     {
         /* 32-bit entries */
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         case PGMPOOLKIND_32BIT_PD:
             case PGMPOOLKIND_32BIT_PD_PHYS:
-#else
-        case PGMPOOLKIND_ROOT_32BIT_PD:
-#endif
             u.pau32[iUserTable] = 0;
             break;
@@ -3322 +2928 @@
         case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
         case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
-#if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+#if defined(IN_RC)
             /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
              * non-present PDPT will continue to cause page faults.
@@ -3336 +2942 @@
         case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
         case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
-#if !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) && !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
-        case PGMPOOLKIND_ROOT_PAE_PD:
-#endif
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         case PGMPOOLKIND_PAE_PDPT:
         case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
-#else
-        case PGMPOOLKIND_ROOT_PDPT:
-#endif
         case PGMPOOLKIND_ROOT_NESTED:
         case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
@@ -3848 +3447 @@
 
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 /**
  * Clear references to shadowed pages in a 32 bits page directory.
@@ -3872 +3470 @@
     }
 }
-#endif
 
 /**
@@ -3886 +3483 @@
     {
         if (    pShwPD->a[i].n.u1Present
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
             &&  !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
-#endif
            )
         {
@@ -3914 +3509 @@
     {
         if (    pShwPDPT->a[i].n.u1Present
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
             &&  !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
-#endif
            )
         {
@@ -4111 +3704 @@
             break;
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         case PGMPOOLKIND_32BIT_PD_PHYS:
         case PGMPOOLKIND_32BIT_PD:
@@ -4120 +3712 @@
         case PGMPOOLKIND_PAE_PDPT:
         case PGMPOOLKIND_PAE_PDPT_PHYS:
-#endif
         case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
         case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
@@ -4175 +3766 @@
      */
     Assert(NIL_PGMPOOL_IDX == 0);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    for (unsigned i = 1; i < PGMPOOL_IDX_FIRST; i++)
-    {
-        /*
-         * Get the page address.
-         */
-        PPGMPOOLPAGE pPage = &pPool->aPages[i];
-        union
-        {
-            uint64_t *pau64;
-            uint32_t *pau32;
-        } u;
-
-        /*
-         * Mark stuff not present.
-         */
-        switch (pPage->enmKind)
-        {
-            case PGMPOOLKIND_ROOT_32BIT_PD:
-                u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-                for (unsigned iPage = 0; iPage < X86_PG_ENTRIES; iPage++)
-                    if ((u.pau32[iPage] & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == X86_PDE_P)
-                        u.pau32[iPage] = 0;
-                break;
-
-            case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
-                u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-                for (unsigned iPage = 0; iPage < X86_PG_PAE_ENTRIES; iPage++)
-                    if ((u.pau64[iPage] & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == X86_PDE_P)
-                        u.pau64[iPage] = 0;
-                break;
-
-            case PGMPOOLKIND_ROOT_PDPT:
-                /* Not root of shadowed pages currently, ignore it. */
-                break;
-
-            case PGMPOOLKIND_ROOT_NESTED:
-                u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
-                ASMMemZero32(u.pau64, PAGE_SIZE);
-                break;
-        }
-    }
-#endif
 
     /*
@@ -4255 +3803 @@
     }
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     /* Unmap the old CR3 value before flushing everything. */
     int rc = PGM_BTH_PFN(UnmapCR3, pVM)(pVM);
@@ -4263 +3810 @@
     rc = PGM_SHW_PFN(Exit, pVM)(pVM);
     AssertRC(rc);
-#endif
 
     /*
@@ -4302 +3848 @@
         pPage->iAgePrev  = NIL_PGMPOOL_IDX;
 #endif
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
         pPage->fLocked   = false;
-#endif
     }
     pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
@@ -4409 +3953 @@
     }
 
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     /* Force a shadow mode reinit (necessary for nested paging and ept). */
     pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
@@ -4416 +3959 @@
     rc = PGMR3ChangeMode(pVM, PGMGetGuestMode(pVM));
     AssertRC(rc);
-#endif
 
     /*
@@ -4458 +4000 @@
      * Quietly reject any attempts at flushing the currently active shadow CR3 mapping
      */
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     if (pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
     {
@@ -4471 +4012 @@
                   || pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
                   ("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(pPool->CTX_SUFF(pVM)), pPage->Core.Key, pPage->enmKind));
-#else
-    if (PGMGetHyperCR3(pPool->CTX_SUFF(pVM)) == pPage->Core.Key)
-    {
-        AssertMsg(pPage->enmKind == PGMPOOLKIND_64BIT_PML4,
-                  ("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(pPool->CTX_SUFF(pVM)), pPage->Core.Key, pPage->enmKind));
-#endif
         Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
         return VINF_SUCCESS;
@@ -4585 +4120 @@
      */
     if (    pPool->cCurPages < pPool->cMaxPages
-#if defined(VBOX_WITH_PGMPOOL_PAGING_ONLY) && defined(IN_RC)
+#if defined(IN_RC)
         /* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
         &&  enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
@@ -4875 +4410 @@
     case PGMPOOLKIND_EPT_PT_FOR_PHYS:
         return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    case PGMPOOLKIND_ROOT_32BIT_PD:
-        return "PGMPOOLKIND_ROOT_32BIT_PD";
-    case PGMPOOLKIND_ROOT_PAE_PD:
-        return "PGMPOOLKIND_ROOT_PAE_PD";
-    case PGMPOOLKIND_ROOT_PDPT:
-        return "PGMPOOLKIND_ROOT_PDPT";
-#endif
     case PGMPOOLKIND_ROOT_NESTED:
         return "PGMPOOLKIND_ROOT_NESTED";

trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

@@ -110 +110 @@
 #  define SHW_PDPE_PG_MASK      X86_PDPE_PG_MASK
 #  define SHW_TOTAL_PD_ENTRIES  (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
-#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
 #  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_PDPT
-#  else
-#  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_PAE_PD
-#  endif
 
 # endif

trunk/src/VBox/VMM/VMMSwitcher.cpp

@@ -716 +716 @@
                     GCPtrGDT,
                     PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
                     /* @todo No need for three GetHyper calls; one and the same base is used */
-#endif
                     PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
                     SelCS, SelDS, SelCS64, SelTSS);

trunk/src/VBox/VMM/testcase/tstVMStructGC.cpp

@@ -416 +416 @@
     GEN_CHECK_OFF(PGM, GCPhysCR3);
     GEN_CHECK_OFF(PGM, GCPtrCR3Mapping);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    GEN_CHECK_OFF(PGM, GCPhysGstCR3Monitored);
-#endif
     GEN_CHECK_OFF(PGM, pGst32BitPdR3);
 #ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
@@ -436 +433 @@
     GEN_CHECK_OFF(PGM, aGCPhysGstPaePDs);
     GEN_CHECK_OFF(PGM, aGCPhysGstPaePDsMonitored);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    GEN_CHECK_OFF(PGM, pShw32BitPdR3);
-# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    GEN_CHECK_OFF(PGM, pShw32BitPdR0);
-# endif
-    GEN_CHECK_OFF(PGM, pShw32BitPdRC);
-    GEN_CHECK_OFF(PGM, HCPhysShw32BitPD);
-    GEN_CHECK_OFF(PGM, apShwPaePDsR3);
-# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    GEN_CHECK_OFF(PGM, apShwPaePDsR0);
-# endif
-    GEN_CHECK_OFF(PGM, apShwPaePDsRC);
-    GEN_CHECK_OFF(PGM, aHCPhysPaePDs);
-    GEN_CHECK_OFF(PGM, pShwPaePdptR3);
-    GEN_CHECK_OFF(PGM, pShwPaePdptR0);
-    GEN_CHECK_OFF(PGM, pShwPaePdptRC);
-    GEN_CHECK_OFF(PGM, HCPhysShwPaePdpt);
-#endif
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    GEN_CHECK_OFF(PGM, pShwRootR3);
-# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    GEN_CHECK_OFF(PGM, pShwRootR0);
-# endif
-    GEN_CHECK_OFF(PGM, HCPhysShwCR3);
-#endif
     GEN_CHECK_OFF(PGM, pShwPageCR3R3);
     GEN_CHECK_OFF(PGM, pShwPageCR3R0);
@@ -472 +444 @@
     GEN_CHECK_OFF(PGM, pfnR3GstRelocate);
     GEN_CHECK_OFF(PGM, pfnR3GstExit);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    GEN_CHECK_OFF(PGM, pfnR3GstMonitorCR3);
-    GEN_CHECK_OFF(PGM, pfnR3GstUnmonitorCR3);
-#endif
     GEN_CHECK_OFF(PGM, pfnR3BthMapCR3);
     GEN_CHECK_OFF(PGM, pfnR3BthUnmapCR3);
@@ -689 +657 @@
     GEN_CHECK_OFF(PGMPOOLPAGE, fCached);
     GEN_CHECK_OFF(PGMPOOLPAGE, fReusedFlushPending);
-#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-    GEN_CHECK_OFF(PGMPOOLPAGE, fCR3Mix);
-#endif
     GEN_CHECK_SIZE(PGMPOOL);
     GEN_CHECK_OFF(PGMPOOL, pVMR3);