- Timestamp:
- Dec 13, 2013 4:17:46 PM (11 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp
r49893 r49899 1079 1079 1080 1080 /** @callback_method_impl{FNCPUMRDMSR} */ 1081 static DECLCALLBACK(int) cpumMsrRd_(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1082 { 1083 *puValue = 0; 1081 static DECLCALLBACK(int) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1082 { 1083 /** @todo IA32_DEBUG_INTERFACE (no docs) */ 1084 *puValue = 0; 1085 return VINF_SUCCESS; 1086 } 1087 1088 1089 /** @callback_method_impl{FNCPUMWRMSR} */ 1090 static DECLCALLBACK(int) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 1091 { 1092 /** @todo IA32_DEBUG_INTERFACE (no docs) */ 1084 1093 return VINF_SUCCESS; 1085 1094 } … … 2171 2180 2172 2181 2182 /** @callback_method_impl{FNCPUMRDMSR} */ 2183 static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2184 { 2185 /** @todo intel power management. */ 2186 *puValue = pRange->uInitOrReadValue; 2187 return VINF_SUCCESS; 2188 } 2189 2190 2191 /** @callback_method_impl{FNCPUMRDMSR} */ 2192 static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2193 { 2194 /** @todo intel power management. */ 2195 *puValue = pRange->uInitOrReadValue; 2196 return VINF_SUCCESS; 2197 } 2198 2199 2200 /** @callback_method_impl{FNCPUMRDMSR} */ 2201 static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2202 { 2203 /** @todo intel power management. */ 2204 *puValue = pRange->uInitOrReadValue; 2205 return VINF_SUCCESS; 2206 } 2207 2208 2209 /** @callback_method_impl{FNCPUMRDMSR} */ 2210 static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2211 { 2212 /** @todo intel power management. */ 2213 *puValue = 0; 2214 return VINF_SUCCESS; 2215 } 2216 2217 2218 /** @callback_method_impl{FNCPUMWRMSR} */ 2219 static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2220 { 2221 /** @todo intel power management. */ 2222 return VINF_SUCCESS; 2223 } 2224 2225 2226 /** @callback_method_impl{FNCPUMRDMSR} */ 2227 static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2228 { 2229 /** @todo intel power management. */ 2230 *puValue = 0; 2231 return VINF_SUCCESS; 2232 } 2233 2234 2235 /** @callback_method_impl{FNCPUMWRMSR} */ 2236 static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2237 { 2238 /** @todo intel power management. */ 2239 return VINF_SUCCESS; 2240 } 2241 2242 2243 /** @callback_method_impl{FNCPUMRDMSR} */ 2244 static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2245 { 2246 /** @todo uncore msrs. */ 2247 *puValue = 0; 2248 return VINF_SUCCESS; 2249 } 2250 2251 2252 /** @callback_method_impl{FNCPUMWRMSR} */ 2253 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2254 { 2255 /** @todo uncore msrs. */ 2256 return VINF_SUCCESS; 2257 } 2258 2259 2260 /** @callback_method_impl{FNCPUMRDMSR} */ 2261 static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2262 { 2263 /** @todo uncore msrs. */ 2264 *puValue = 0; 2265 return VINF_SUCCESS; 2266 } 2267 2268 2269 /** @callback_method_impl{FNCPUMWRMSR} */ 2270 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2271 { 2272 /** @todo uncore msrs. */ 2273 return VINF_SUCCESS; 2274 } 2275 2276 2277 /** @callback_method_impl{FNCPUMRDMSR} */ 2278 static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2279 { 2280 /** @todo uncore msrs. */ 2281 *puValue = 0; 2282 return VINF_SUCCESS; 2283 } 2284 2285 2286 /** @callback_method_impl{FNCPUMWRMSR} */ 2287 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2288 { 2289 /** @todo uncore msrs. */ 2290 return VINF_SUCCESS; 2291 } 2292 2293 2294 /** @callback_method_impl{FNCPUMRDMSR} */ 2295 static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2296 { 2297 /** @todo uncore msrs. */ 2298 *puValue = 0; 2299 return VINF_SUCCESS; 2300 } 2301 2302 2303 /** @callback_method_impl{FNCPUMWRMSR} */ 2304 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2305 { 2306 /** @todo uncore msrs. */ 2307 return VINF_SUCCESS; 2308 } 2309 2310 2311 /** @callback_method_impl{FNCPUMRDMSR} */ 2312 static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2313 { 2314 /** @todo uncore msrs. */ 2315 *puValue = 0; 2316 return VINF_SUCCESS; 2317 } 2318 2319 2320 /** @callback_method_impl{FNCPUMWRMSR} */ 2321 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2322 { 2323 /** @todo uncore msrs. */ 2324 return VINF_SUCCESS; 2325 } 2326 2327 2328 /** @callback_method_impl{FNCPUMRDMSR} */ 2329 static DECLCALLBACK(int) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2330 { 2331 /** @todo uncore msrs. */ 2332 *puValue = 0; 2333 return VINF_SUCCESS; 2334 } 2335 2336 2337 /** @callback_method_impl{FNCPUMRDMSR} */ 2338 static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2339 { 2340 /** @todo uncore msrs. */ 2341 *puValue = 0; 2342 return VINF_SUCCESS; 2343 } 2344 2345 2346 /** @callback_method_impl{FNCPUMWRMSR} */ 2347 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2348 { 2349 /** @todo uncore msrs. */ 2350 return VINF_SUCCESS; 2351 } 2352 2353 2354 /** @callback_method_impl{FNCPUMRDMSR} */ 2355 static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2356 { 2357 /** @todo uncore msrs. */ 2358 *puValue = 0; 2359 return VINF_SUCCESS; 2360 } 2361 2362 2363 /** @callback_method_impl{FNCPUMWRMSR} */ 2364 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2365 { 2366 /** @todo uncore msrs. */ 2367 return VINF_SUCCESS; 2368 } 2173 2369 2174 2370 … … 3906 4102 cpumMsrRd_Ia32TscDeadline, 3907 4103 cpumMsrRd_Ia32X2ApicN, 4104 cpumMsrRd_Ia32DebugInterface, 3908 4105 cpumMsrRd_Ia32VmxBase, 3909 4106 cpumMsrRd_Ia32VmxPinbasedCtls, … … 3982 4179 cpumMsrRd_IntelI7RaplPp1EnergyStatus, 3983 4180 cpumMsrRd_IntelI7RaplPp1Policy, 4181 cpumMsrRd_IntelI7IvyConfigTdpNominal, 4182 cpumMsrRd_IntelI7IvyConfigTdpLevel1, 4183 cpumMsrRd_IntelI7IvyConfigTdpLevel2, 4184 cpumMsrRd_IntelI7IvyConfigTdpControl, 4185 cpumMsrRd_IntelI7IvyTurboActivationRatio, 4186 cpumMsrRd_IntelI7UncPerfGlobalCtrl, 4187 cpumMsrRd_IntelI7UncPerfGlobalStatus, 4188 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl, 4189 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl, 4190 cpumMsrRd_IntelI7UncPerfFixedCtr, 4191 cpumMsrRd_IntelI7UncCBoxConfig, 4192 cpumMsrRd_IntelI7UncArbPerfCtrN, 4193 cpumMsrRd_IntelI7UncArbPerfEvtSelN, 3984 4194 3985 4195 cpumMsrRd_P6LastBranchFromIp, … … 4133 4343 cpumMsrWr_Ia32TscDeadline, 4134 4344 cpumMsrWr_Ia32X2ApicN, 4345 cpumMsrWr_Ia32DebugInterface, 4135 4346 4136 4347 cpumMsrWr_Amd64Efer, … … 4176 4387 cpumMsrWr_IntelI7RaplPp1PowerLimit, 4177 4388 cpumMsrWr_IntelI7RaplPp1Policy, 4389 cpumMsrWr_IntelI7IvyConfigTdpControl, 4390 cpumMsrWr_IntelI7IvyTurboActivationRatio, 4391 cpumMsrWr_IntelI7UncPerfGlobalCtrl, 4392 cpumMsrWr_IntelI7UncPerfGlobalStatus, 4393 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl, 4394 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl, 4395 cpumMsrWr_IntelI7UncPerfFixedCtr, 4396 cpumMsrWr_IntelI7UncArbPerfCtrN, 4397 cpumMsrWr_IntelI7UncArbPerfEvtSelN, 4178 4398 4179 4399 cpumMsrWr_P6LastIntFromIp, … … 4512 4732 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline); 4513 4733 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN); 4734 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface); 4514 4735 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase); 4515 4736 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls); … … 4529 4750 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls); 4530 4751 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls); 4752 4531 4753 CPUM_ASSERT_RD_MSR_FN(Amd64Efer); 4532 4754 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget); … … 4538 4760 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase); 4539 4761 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux); 4762 4540 4763 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn); 4541 4764 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo100MHz); … … 4586 4809 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus); 4587 4810 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy); 4811 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal); 4812 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1); 4813 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2); 4814 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl); 4815 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio); 4816 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl); 4817 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus); 4818 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl); 4819 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl); 4820 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr); 4821 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig); 4822 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN); 4823 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN); 4588 4824 4589 4825 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp); … … 4726 4962 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline); 4727 4963 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN); 4964 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface); 4965 4728 4966 CPUM_ASSERT_WR_MSR_FN(Amd64Efer); 4729 4967 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget); … … 4768 5006 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit); 4769 5007 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy); 5008 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl); 5009 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio); 5010 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl); 5011 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus); 5012 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl); 5013 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl); 5014 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr); 5015 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN); 5016 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN); 4770 5017 4771 5018 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp); -
trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp
r49893 r49899 175 175 #include "cpus/Intel_Pentium_M_processor_2_00GHz.h" 176 176 #include "cpus/Intel_Core_i7_3960X.h" 177 #include "cpus/Intel_Core_i5_3570.h" 178 177 179 #include "cpus/AMD_FX_8150_Eight_Core.h" 178 180 #include "cpus/Quad_Core_AMD_Opteron_2384.h" … … 188 190 static CPUMDBENTRY const * const g_apCpumDbEntries[] = 189 191 { 192 #ifdef VBOX_CPUDB_Intel_Core_i5_3570 193 &g_Entry_Intel_Core_i5_3570, 194 #endif 190 195 #ifdef VBOX_CPUDB_Intel_Core_i7_3960X 191 196 &g_Entry_Intel_Core_i7_3960X, -
trunk/src/VBox/VMM/include/CPUMInternal.h
r49893 r49899 175 175 kCpumMsrRdFn_Ia32TscDeadline, 176 176 kCpumMsrRdFn_Ia32X2ApicN, 177 kCpumMsrRdFn_Ia32DebugInterface, 177 178 kCpumMsrRdFn_Ia32VmxBase, /**< Takes real value as reference. */ 178 179 kCpumMsrRdFn_Ia32VmxPinbasedCtls, /**< Takes real value as reference. */ … … 251 252 kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */ 252 253 kCpumMsrRdFn_IntelI7RaplPp1Policy, /**< Takes real value as reference. */ 254 kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /**< Takes real value as reference. */ 255 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /**< Takes real value as reference. */ 256 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /**< Takes real value as reference. */ 257 kCpumMsrRdFn_IntelI7IvyConfigTdpControl, 258 kCpumMsrRdFn_IntelI7IvyTurboActivationRatio, 259 kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl, 260 kCpumMsrRdFn_IntelI7UncPerfGlobalStatus, 261 kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl, 262 kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl, 263 kCpumMsrRdFn_IntelI7UncPerfFixedCtr, 264 kCpumMsrRdFn_IntelI7UncCBoxConfig, 265 kCpumMsrRdFn_IntelI7UncArbPerfCtrN, 266 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN, 253 267 254 268 kCpumMsrRdFn_P6LastBranchFromIp, … … 411 425 kCpumMsrWrFn_Ia32TscDeadline, 412 426 kCpumMsrWrFn_Ia32X2ApicN, 427 kCpumMsrWrFn_Ia32DebugInterface, 413 428 414 429 kCpumMsrWrFn_Amd64Efer, … … 453 468 kCpumMsrWrFn_IntelI7RaplPp1PowerLimit, 454 469 kCpumMsrWrFn_IntelI7RaplPp1Policy, 470 kCpumMsrWrFn_IntelI7IvyConfigTdpControl, 471 kCpumMsrWrFn_IntelI7IvyTurboActivationRatio, 472 kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl, 473 kCpumMsrWrFn_IntelI7UncPerfGlobalStatus, 474 kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl, 475 kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl, 476 kCpumMsrWrFn_IntelI7UncPerfFixedCtr, 477 kCpumMsrWrFn_IntelI7UncArbPerfCtrN, 478 kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN, 455 479 456 480 kCpumMsrWrFn_P6LastIntFromIp, -
trunk/src/VBox/VMM/tools/VBoxCpuReport.cpp
r49895 r49899 843 843 case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR" /* X */ : "I7_UNC_PERF_FIXED_CTR_CTRL"; /* >= S,H */ 844 844 case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR_CTRL" /* X*/ : "I7_UNC_PERF_FIXED_CTR"; /* >= S,H */ 845 case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_ADDR_OPCODE_MATCH" /* X */ : "I7_UNC_CB0_CONFIG"; /* >= S,H */ 845 case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_ADDR_OPCODE_MATCH" /* X */ : "I7_UNC_CBO_CONFIG"; /* >= S,H */ 846 case 0x00000397: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_IvyBridge ? NULL : "I7_IB_UNK_0000_0397"; 846 847 case 0x0000039c: return "I7_SB_MSR_PEBS_NUM_ALT"; 847 848 case 0x000003b0: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC0" /* X */ : "I7_UNC_ARB_PERF_CTR0"; /* >= S,H */ … … 898 899 case 0x00000600: return "IA32_DS_AREA"; 899 900 case 0x00000601: return "I7_SB_MSR_VR_CURRENT_CONFIG"; /* SandyBridge, IvyBridge. */ 901 case 0x00000602: return "I7_IB_UNK_0000_0602"; 900 902 case 0x00000603: return "I7_SB_MSR_VR_MISC_CONFIG"; /* SandyBridge, IvyBridge. */ 903 case 0x00000604: return "I7_IB_UNK_0000_0602"; 901 904 case 0x00000606: return "I7_SB_MSR_RAPL_POWER_UNIT"; /* SandyBridge, IvyBridge. */ 902 905 case 0x0000060a: return "I7_SB_MSR_PKGC3_IRTL"; /* SandyBridge, IvyBridge. */ … … 919 922 case 0x00000641: return "I7_HW_MSR_PP0_ENERGY_STATUS"; 920 923 case 0x00000642: return "I7_HW_MSR_PP0_POLICY"; 924 case 0x00000648: return "I7_IB_MSR_CONFIG_TDP_NOMINAL"; 925 case 0x00000649: return "I7_IB_MSR_CONFIG_TDP_LEVEL1"; 926 case 0x0000064a: return "I7_IB_MSR_CONFIG_TDP_LEVEL2"; 927 case 0x0000064b: return "I7_IB_MSR_CONFIG_TDP_CONTROL"; 928 case 0x0000064c: return "I7_IB_MSR_TURBO_ACTIVATION_RATIO"; 921 929 case 0x00000680: return "MSR_LASTBRANCH_0_FROM_IP"; 922 930 case 0x00000681: return "MSR_LASTBRANCH_1_FROM_IP"; … … 953 961 case 0x000006e0: return "IA32_TSC_DEADLINE"; 954 962 963 case 0x00000c80: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "IA32_DEBUG_INTERFACE" : NULL; /* Mentioned in an intel dataskit called 4th-gen-core-family-desktop-vol-1-datasheet.pdf. */ 964 case 0x00000c81: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c81" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */ 965 case 0x00000c82: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c82" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */ 966 case 0x00000c83: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c83" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */ 955 967 956 968 /* 0x1000..0x1004 seems to have been used by IBM 386 and 486 clones too. */ … … 1311 1323 case 0x00000db8: return "I7_SB_UNK_0000_0db8"; case 0x00000db9: return "I7_SB_UNK_0000_0db9"; 1312 1324 } 1325 1326 /* 1327 * Ditto for ivy bridge (observed on the i5-3570). There are some haswell 1328 * and sandybridge related docs on registers in this ares, but either 1329 * things are different for ivy or they're very incomplete. Again, kudos 1330 * to intel! 1331 */ 1332 if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_IvyBridge) 1333 switch (uMsr) 1334 { 1335 case 0x00000700: return "I7_IB_UNK_0000_0700"; case 0x00000701: return "I7_IB_UNK_0000_0701"; 1336 case 0x00000702: return "I7_IB_UNK_0000_0702"; case 0x00000703: return "I7_IB_UNK_0000_0703"; 1337 case 0x00000704: return "I7_IB_UNK_0000_0704"; case 0x00000705: return "I7_IB_UNK_0000_0705"; 1338 case 0x00000706: return "I7_IB_UNK_0000_0706"; case 0x00000707: return "I7_IB_UNK_0000_0707"; 1339 case 0x00000708: return "I7_IB_UNK_0000_0708"; case 0x00000709: return "I7_IB_UNK_0000_0709"; 1340 case 0x00000710: return "I7_IB_UNK_0000_0710"; case 0x00000711: return "I7_IB_UNK_0000_0711"; 1341 case 0x00000712: return "I7_IB_UNK_0000_0712"; case 0x00000713: return "I7_IB_UNK_0000_0713"; 1342 case 0x00000714: return "I7_IB_UNK_0000_0714"; case 0x00000715: return "I7_IB_UNK_0000_0715"; 1343 case 0x00000716: return "I7_IB_UNK_0000_0716"; case 0x00000717: return "I7_IB_UNK_0000_0717"; 1344 case 0x00000718: return "I7_IB_UNK_0000_0718"; case 0x00000719: return "I7_IB_UNK_0000_0719"; 1345 case 0x00000720: return "I7_IB_UNK_0000_0720"; case 0x00000721: return "I7_IB_UNK_0000_0721"; 1346 case 0x00000722: return "I7_IB_UNK_0000_0722"; case 0x00000723: return "I7_IB_UNK_0000_0723"; 1347 case 0x00000724: return "I7_IB_UNK_0000_0724"; case 0x00000725: return "I7_IB_UNK_0000_0725"; 1348 case 0x00000726: return "I7_IB_UNK_0000_0726"; case 0x00000727: return "I7_IB_UNK_0000_0727"; 1349 case 0x00000728: return "I7_IB_UNK_0000_0728"; case 0x00000729: return "I7_IB_UNK_0000_0729"; 1350 case 0x00000730: return "I7_IB_UNK_0000_0730"; case 0x00000731: return "I7_IB_UNK_0000_0731"; 1351 case 0x00000732: return "I7_IB_UNK_0000_0732"; case 0x00000733: return "I7_IB_UNK_0000_0733"; 1352 case 0x00000734: return "I7_IB_UNK_0000_0734"; case 0x00000735: return "I7_IB_UNK_0000_0735"; 1353 case 0x00000736: return "I7_IB_UNK_0000_0736"; case 0x00000737: return "I7_IB_UNK_0000_0737"; 1354 case 0x00000738: return "I7_IB_UNK_0000_0738"; case 0x00000739: return "I7_IB_UNK_0000_0739"; 1355 case 0x00000740: return "I7_IB_UNK_0000_0740"; case 0x00000741: return "I7_IB_UNK_0000_0741"; 1356 case 0x00000742: return "I7_IB_UNK_0000_0742"; case 0x00000743: return "I7_IB_UNK_0000_0743"; 1357 case 0x00000744: return "I7_IB_UNK_0000_0744"; case 0x00000745: return "I7_IB_UNK_0000_0745"; 1358 case 0x00000746: return "I7_IB_UNK_0000_0746"; case 0x00000747: return "I7_IB_UNK_0000_0747"; 1359 case 0x00000748: return "I7_IB_UNK_0000_0748"; case 0x00000749: return "I7_IB_UNK_0000_0749"; 1360 1361 } 1313 1362 return NULL; 1314 1363 } … … 1561 1610 case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtr" /* X */ : "IntelI7UncPerfFixedCtrCtrl"; /* >= S,H */ 1562 1611 case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtrCtrl" /* X*/ : "IntelI7UncPerfFixedCtr"; /* >= S,H */ 1563 case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncAddrOpcodeMatch" /* X */ : "IntelI7UncC bO_Config"; /* >= S,H */1612 case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncAddrOpcodeMatch" /* X */ : "IntelI7UncCBoxConfig"; /* >= S,H */ 1564 1613 case 0x0000039c: return "IntelI7SandyPebsNumAlt"; 1565 1614 case 0x000003b0: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfCtrN"; /* >= S,H */ … … 1634 1683 case 0x00000641: return "IntelI7RaplPp1EnergyStatus"; 1635 1684 case 0x00000642: return "IntelI7RaplPp1Policy"; 1685 case 0x00000648: return "IntelI7IvyConfigTdpNominal"; 1686 case 0x00000649: return "IntelI7IvyConfigTdpLevel1"; 1687 case 0x0000064a: return "IntelI7IvyConfigTdpLevel2"; 1688 case 0x0000064b: return "IntelI7IvyConfigTdpControl"; 1689 case 0x0000064c: return "IntelI7IvyTurboActivationRatio"; 1690 1636 1691 case 0x00000680: case 0x00000681: case 0x00000682: case 0x00000683: 1637 1692 case 0x00000684: case 0x00000685: case 0x00000686: case 0x00000687: … … 1652 1707 //case 0x000006dc: case 0x000006dd: case 0x000006de: case 0x000006df: 1653 1708 return "IntelLastBranchFromN"; 1654 case 0x000006e0: return "Ia32TscDeadline"; 1709 case 0x000006e0: return "Ia32TscDeadline"; /** @todo detect this correctly! */ 1710 1711 case 0x00000c80: return g_enmMicroarch > kCpumMicroarch_Intel_Core7_Nehalem ? "Ia32DebugInterface" : NULL; 1655 1712 1656 1713 case 0xc0000080: return "Amd64Efer"; … … 1881 1938 case 0x000001f3: return UINT64_C(0xfffff800); /* Ia32SmrrPhysMask - Only writable in SMM. */ 1882 1939 1940 /* these two have lock bits. */ 1941 case 0x0000064b: return UINT64_C(0x80000003); 1942 case 0x0000064c: return UINT64_C(0x800000ff); 1943 1883 1944 case 0xc0010015: return 1; /* SmmLock bit */ 1884 1945 … … 1901 1962 case 0x000000e7: 1902 1963 case 0x000000e8: 1903 return RT_BIT_32(2 7) - 1;1964 return RT_BIT_32(29) - 1; 1904 1965 } 1905 1966 return 0;
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