VirtualBox

Ignore:
Timestamp:
Oct 28, 2015 8:17:18 PM (9 years ago)
Author:
vboxsync
Message:

EFI/Firmware: 'svn merge /vendor/edk2/UDK2010.SR1 /vendor/edk2/current .', reverting and removing files+dirs listed in ReadMe.vbox, resolving conflicts with help from ../UDK2014.SP1/. This is a raw untested merge.

Location:
trunk/src/VBox/Devices/EFI/Firmware
Files:
39 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/EFI/Firmware

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c

    r48674 r58459  
    77
    88  Note that EhciDxe driver is enhanced to guarantee that the EHCI controller get attached
    9   to the EHCI controller before the UHCI driver attaches to the companion UHCI controller.
    10   This way avoids the control transfer on a shared port between EHCI and companion host
    11   controller when UHCI gets attached earlier than EHCI and a USB 2.0 device inserts.
    12 
    13 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
     9  to the EHCI controller before a UHCI or OHCI driver attaches to the companion UHCI or
     10  OHCI controller.  This way avoids the control transfer on a shared port between EHCI
     11  and companion host controller when UHCI or OHCI gets attached earlier than EHCI and a
     12  USB 2.0 device inserts.
     13
     14Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
    1415This program and the accompanying materials
    1516are licensed and made available under the terms and conditions of the BSD License
    … …  
    123124  UINT32                  DbgCtrlStatus;
    124125
     126  Ehc = EHC_FROM_THIS (This);
     127
     128  if (Ehc->DevicePath != NULL) {
     129    //
     130    // Report Status Code to indicate reset happens
     131    //
     132    REPORT_STATUS_CODE_WITH_DEVICE_PATH (
     133      EFI_PROGRESS_CODE,
     134      (EFI_IO_BUS_USB | EFI_IOB_PC_RESET),
     135      Ehc->DevicePath
     136      );
     137  }
     138
    125139  OldTpl  = gBS->RaiseTPL (EHC_TPL);
    126   Ehc     = EHC_FROM_THIS (This);
    127140
    128141  switch (Attributes) {
    … …  
    13921405  //
    13931406  if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) || (UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB)
    1394       || ((UsbClassCReg.ProgInterface != PCI_IF_EHCI) && (UsbClassCReg.ProgInterface !=PCI_IF_UHCI))) {
     1407      || ((UsbClassCReg.ProgInterface != PCI_IF_EHCI) && (UsbClassCReg.ProgInterface != PCI_IF_UHCI) && (UsbClassCReg.ProgInterface != PCI_IF_OHCI))) {
    13951408
    13961409    Status = EFI_UNSUPPORTED;
    … …  
    15361549
    15371550  @param  PciIo                  The PciIo on this device.
     1551  @param  DevicePath             The device path of host controller.
    15381552  @param  OriginalPciAttributes  Original PCI attributes.
    15391553
    … …  
    15441558USB2_HC_DEV *
    15451559EhcCreateUsb2Hc (
    1546   IN EFI_PCI_IO_PROTOCOL  *PciIo,
    1547   IN UINT64               OriginalPciAttributes
     1560  IN EFI_PCI_IO_PROTOCOL       *PciIo,
     1561  IN EFI_DEVICE_PATH_PROTOCOL  *DevicePath,
     1562  IN UINT64                    OriginalPciAttributes
    15481563  )
    15491564{
    … …  
    15791594
    15801595  Ehc->PciIo                 = PciIo;
     1596  Ehc->DevicePath            = DevicePath;
    15811597  Ehc->OriginalPciAttributes = OriginalPciAttributes;
    15821598
    … …  
    16221638
    16231639  @param  Event                   Pointer to this event
    1624   @param  Context                 Event hanlder private data
     1640  @param  Context                 Event handler private data
    16251641
    16261642**/
    … …  
    16761692  UINTN                   NumberOfHandles;
    16771693  UINTN                   Index;
    1678   UINTN                   UhciSegmentNumber;
    1679   UINTN                   UhciBusNumber;
    1680   UINTN                   UhciDeviceNumber;
    1681   UINTN                   UhciFunctionNumber;
     1694  UINTN                   CompanionSegmentNumber;
     1695  UINTN                   CompanionBusNumber;
     1696  UINTN                   CompanionDeviceNumber;
     1697  UINTN                   CompanionFunctionNumber;
    16821698  UINTN                   EhciSegmentNumber;
    16831699  UINTN                   EhciBusNumber;
    … …  
    16851701  UINTN                   EhciFunctionNumber;
    16861702  UINT32                  State;
     1703  EFI_DEVICE_PATH_PROTOCOL  *HcDevicePath;
    16871704
    16881705  //
    … …  
    17021719  }
    17031720
     1721  //
     1722  // Open Device Path Protocol for on USB host controller
     1723  //
     1724  HcDevicePath = NULL;
     1725  Status = gBS->OpenProtocol (
     1726                  Controller,
     1727                  &gEfiDevicePathProtocolGuid,
     1728                  (VOID **) &HcDevicePath,
     1729                  This->DriverBindingHandle,
     1730                  Controller,
     1731                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
     1732                  );
     1733
    17041734  PciAttributesSaved = FALSE;
    17051735  //
    … …  
    17251755                    );
    17261756  if (!EFI_ERROR (Status)) {
    1727     Supports &= EFI_PCI_DEVICE_ENABLE;
     1757    Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
    17281758    Status = PciIo->Attributes (
    17291759                      PciIo,
    … …  
    17551785  }
    17561786  //
    1757   // determine if the device is UHCI host controller or not. If yes, then find out the
     1787  // Determine if the device is UHCI or OHCI host controller or not. If yes, then find out the
    17581788  // companion usb ehci host controller and force EHCI driver get attached to it before
    1759   // UHCI driver attaches to UHCI host controller.
    1760   //
    1761   if ((UsbClassCReg.ProgInterface == PCI_IF_UHCI) &&
     1789  // UHCI or OHCI driver attaches to UHCI or OHCI host controller.
     1790  //
     1791  if ((UsbClassCReg.ProgInterface == PCI_IF_UHCI || UsbClassCReg.ProgInterface == PCI_IF_OHCI) &&
    17621792       (UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&
    17631793       (UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {
    17641794    Status = PciIo->GetLocation (
    17651795                    PciIo,
    1766                     &UhciSegmentNumber,
    1767                     &UhciBusNumber,
    1768                     &UhciDeviceNumber,
    1769                     &UhciFunctionNumber
     1796                    &CompanionSegmentNumber,
     1797                    &CompanionBusNumber,
     1798                    &CompanionDeviceNumber,
     1799                    &CompanionFunctionNumber
    17701800                    );
    17711801    if (EFI_ERROR (Status)) {
    … …  
    18251855        // same bus number, which may vary on different platform.
    18261856        //
    1827         if (EhciBusNumber == UhciBusNumber) {
     1857        if (EhciBusNumber == CompanionBusNumber) {
    18281858          gBS->CloseProtocol (
    18291859                    Controller,
    … …  
    18431873  // Create then install USB2_HC_PROTOCOL
    18441874  //
    1845   Ehc = EhcCreateUsb2Hc (PciIo, OriginalPciAttributes);
     1875  Ehc = EhcCreateUsb2Hc (PciIo, HcDevicePath, OriginalPciAttributes);
    18461876
    18471877  if (Ehc == NULL) {
    … …  
    20202050  PciIo = Ehc->PciIo;
    20212051
    2022   //
    2023   // Stop AsyncRequest Polling timer then stop the EHCI driver
    2024   // and uninstall the EHCI protocl.
    2025   //
    2026   gBS->SetTimer (Ehc->PollTimer, TimerCancel, EHC_ASYNC_POLL_INTERVAL);
    2027   EhcHaltHC (Ehc, EHC_GENERIC_TIMEOUT);
    2028 
    20292052  Status = gBS->UninstallProtocolInterface (
    20302053                  Controller,
    … …  
    20372060  }
    20382061
     2062  //
     2063  // Stop AsyncRequest Polling timer then stop the EHCI driver
     2064  // and uninstall the EHCI protocl.
     2065  //
     2066  gBS->SetTimer (Ehc->PollTimer, TimerCancel, EHC_ASYNC_POLL_INTERVAL);
     2067  EhcHaltHC (Ehc, EHC_GENERIC_TIMEOUT);
     2068
    20392069  if (Ehc->PollTimer != NULL) {
    20402070    gBS->CloseEvent (Ehc->PollTimer);
    … …  
    20532083  //
    20542084  // Disable routing of all ports to EHCI controller, so all ports are
    2055   // routed back to the UHCI controller.
     2085  // routed back to the UHCI or OHCI controller.
    20562086  //
    20572087  EhcClearOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h

    r48674 r58459  
    3333#include <Library/MemoryAllocationLib.h>
    3434#include <Library/PcdLib.h>
     35#include <Library/ReportStatusCodeLib.h>
    3536
    3637#include <IndustryStandard/Pci.h>
    … …  
    116117
    117118  EFI_PCI_IO_PROTOCOL       *PciIo;
     119  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;
    118120  UINT64                    OriginalPciAttributes;
    119121  USBHC_MEM_POOL            *MemPool;

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c

    r48674 r58459  
    33  This file provides the information dump support for EHCI when in debug mode.
    44
    5 Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2007 - 2013, Intel Corporation. All rights reserved.<BR>
    66This program and the accompanying materials
    77are licensed and made available under the terms and conditions of the BSD License
    … …  
    2929{
    3030  if (EHC_BIT_IS_SET (State, QTD_STAT_DO_PING)) {
    31     DEBUG ((EFI_D_INFO, "  Do_Ping"));
     31    DEBUG ((EFI_D_VERBOSE, "  Do_Ping"));
    3232  } else {
    33     DEBUG ((EFI_D_INFO, "  Do_Out"));
     33    DEBUG ((EFI_D_VERBOSE, "  Do_Out"));
    3434  }
    3535
    3636  if (EHC_BIT_IS_SET (State, QTD_STAT_DO_CS)) {
    37     DEBUG ((EFI_D_INFO, "  Do_CS"));
     37    DEBUG ((EFI_D_VERBOSE, "  Do_CS"));
    3838  } else {
    39     DEBUG ((EFI_D_INFO, "  Do_SS"));
     39    DEBUG ((EFI_D_VERBOSE, "  Do_SS"));
    4040  }
    4141
    4242  if (EHC_BIT_IS_SET (State, QTD_STAT_TRANS_ERR)) {
    43     DEBUG ((EFI_D_INFO, "  Transfer_Error"));
     43    DEBUG ((EFI_D_VERBOSE, "  Transfer_Error"));
    4444  }
    4545
    4646  if (EHC_BIT_IS_SET (State, QTD_STAT_BABBLE_ERR)) {
    47     DEBUG ((EFI_D_INFO, "  Babble_Error"));
     47    DEBUG ((EFI_D_VERBOSE, "  Babble_Error"));
    4848  }
    4949
    5050  if (EHC_BIT_IS_SET (State, QTD_STAT_BUFF_ERR)) {
    51     DEBUG ((EFI_D_INFO, "  Buffer_Error"));
     51    DEBUG ((EFI_D_VERBOSE, "  Buffer_Error"));
    5252  }
    5353
    5454  if (EHC_BIT_IS_SET (State, QTD_STAT_HALTED)) {
    55     DEBUG ((EFI_D_INFO, "  Halted"));
     55    DEBUG ((EFI_D_VERBOSE, "  Halted"));
    5656  }
    5757
    5858  if (EHC_BIT_IS_SET (State, QTD_STAT_ACTIVE)) {
    59     DEBUG ((EFI_D_INFO, "  Active"));
    60   }
    61 
    62   DEBUG ((EFI_D_INFO, "\n"));
     59    DEBUG ((EFI_D_VERBOSE, "  Active"));
     60  }
     61
     62  DEBUG ((EFI_D_VERBOSE, "\n"));
    6363}
    6464
    … …  
    8181
    8282  if (Msg != NULL) {
    83     DEBUG ((EFI_D_INFO, Msg));
    84   }
    85 
    86   DEBUG ((EFI_D_INFO, "Queue TD @ 0x%p, data length %d\n", Qtd, (UINT32)Qtd->DataLen));
     83    DEBUG ((EFI_D_VERBOSE, Msg));
     84  }
     85
     86  DEBUG ((EFI_D_VERBOSE, "Queue TD @ 0x%p, data length %d\n", Qtd, (UINT32)Qtd->DataLen));
    8787
    8888  QtdHw = &Qtd->QtdHw;
    8989
    90   DEBUG ((EFI_D_INFO, "Next QTD     : %x\n", QtdHw->NextQtd));
    91   DEBUG ((EFI_D_INFO, "AltNext QTD  : %x\n", QtdHw->AltNext));
    92   DEBUG ((EFI_D_INFO, "Status       : %x\n", QtdHw->Status));
     90  DEBUG ((EFI_D_VERBOSE, "Next QTD     : %x\n", QtdHw->NextQtd));
     91  DEBUG ((EFI_D_VERBOSE, "AltNext QTD  : %x\n", QtdHw->AltNext));
     92  DEBUG ((EFI_D_VERBOSE, "Status       : %x\n", QtdHw->Status));
    9393  EhcDumpStatus (QtdHw->Status);
    9494
    9595  if (QtdHw->Pid == QTD_PID_SETUP) {
    96     DEBUG ((EFI_D_INFO, "PID          : Setup\n"));
     96    DEBUG ((EFI_D_VERBOSE, "PID          : Setup\n"));
    9797
    9898  } else if (QtdHw->Pid == QTD_PID_INPUT) {
    99     DEBUG ((EFI_D_INFO, "PID          : IN\n"));
     99    DEBUG ((EFI_D_VERBOSE, "PID          : IN\n"));
    100100
    101101  } else if (QtdHw->Pid == QTD_PID_OUTPUT) {
    102     DEBUG ((EFI_D_INFO, "PID          : OUT\n"));
    103 
    104   }
    105 
    106   DEBUG ((EFI_D_INFO, "Error Count  : %d\n", QtdHw->ErrCnt));
    107   DEBUG ((EFI_D_INFO, "Current Page : %d\n", QtdHw->CurPage));
    108   DEBUG ((EFI_D_INFO, "IOC          : %d\n", QtdHw->Ioc));
    109   DEBUG ((EFI_D_INFO, "Total Bytes  : %d\n", QtdHw->TotalBytes));
    110   DEBUG ((EFI_D_INFO, "Data Toggle  : %d\n", QtdHw->DataToggle));
     102    DEBUG ((EFI_D_VERBOSE, "PID          : OUT\n"));
     103
     104  }
     105
     106  DEBUG ((EFI_D_VERBOSE, "Error Count  : %d\n", QtdHw->ErrCnt));
     107  DEBUG ((EFI_D_VERBOSE, "Current Page : %d\n", QtdHw->CurPage));
     108  DEBUG ((EFI_D_VERBOSE, "IOC          : %d\n", QtdHw->Ioc));
     109  DEBUG ((EFI_D_VERBOSE, "Total Bytes  : %d\n", QtdHw->TotalBytes));
     110  DEBUG ((EFI_D_VERBOSE, "Data Toggle  : %d\n", QtdHw->DataToggle));
    111111
    112112  for (Index = 0; Index < 5; Index++) {
    113     DEBUG ((EFI_D_INFO, "Page[%d]      : 0x%x\n", (UINT32)Index, QtdHw->Page[Index]));
     113    DEBUG ((EFI_D_VERBOSE, "Page[%d]      : 0x%x\n", (UINT32)Index, QtdHw->Page[Index]));
    114114  }
    115115}
    … …  
    137137
    138138  if (Msg != NULL) {
    139     DEBUG ((EFI_D_INFO, Msg));
    140   }
    141 
    142   DEBUG ((EFI_D_INFO, "Queue head @ 0x%p, interval %ld, next qh %p\n",
     139    DEBUG ((EFI_D_VERBOSE, Msg));
     140  }
     141
     142  DEBUG ((EFI_D_VERBOSE, "Queue head @ 0x%p, interval %ld, next qh %p\n",
    143143                                Qh, (UINT64)Qh->Interval, Qh->NextQh));
    144144
    145145  QhHw = &Qh->QhHw;
    146146
    147   DEBUG ((EFI_D_INFO, "Hoziontal link: %x\n", QhHw->HorizonLink));
    148   DEBUG ((EFI_D_INFO, "Device address: %d\n", QhHw->DeviceAddr));
    149   DEBUG ((EFI_D_INFO, "Inactive      : %d\n", QhHw->Inactive));
    150   DEBUG ((EFI_D_INFO, "EP number     : %d\n", QhHw->EpNum));
    151   DEBUG ((EFI_D_INFO, "EP speed      : %d\n", QhHw->EpSpeed));
    152   DEBUG ((EFI_D_INFO, "DT control    : %d\n", QhHw->DtCtrl));
    153   DEBUG ((EFI_D_INFO, "Reclaim head  : %d\n", QhHw->ReclaimHead));
    154   DEBUG ((EFI_D_INFO, "Max packet len: %d\n", QhHw->MaxPacketLen));
    155   DEBUG ((EFI_D_INFO, "Ctrl EP       : %d\n", QhHw->CtrlEp));
    156   DEBUG ((EFI_D_INFO, "Nak reload    : %d\n", QhHw->NakReload));
    157 
    158   DEBUG ((EFI_D_INFO, "SMask         : %x\n", QhHw->SMask));
    159   DEBUG ((EFI_D_INFO, "CMask         : %x\n", QhHw->CMask));
    160   DEBUG ((EFI_D_INFO, "Hub address   : %d\n", QhHw->HubAddr));
    161   DEBUG ((EFI_D_INFO, "Hub port      : %d\n", QhHw->PortNum));
    162   DEBUG ((EFI_D_INFO, "Multiplier    : %d\n", QhHw->Multiplier));
    163 
    164   DEBUG ((EFI_D_INFO, "Cur QTD       : %x\n", QhHw->CurQtd));
    165 
    166   DEBUG ((EFI_D_INFO, "Next QTD      : %x\n", QhHw->NextQtd));
    167   DEBUG ((EFI_D_INFO, "AltNext QTD   : %x\n", QhHw->AltQtd));
    168   DEBUG ((EFI_D_INFO, "Status        : %x\n", QhHw->Status));
     147  DEBUG ((EFI_D_VERBOSE, "Hoziontal link: %x\n", QhHw->HorizonLink));
     148  DEBUG ((EFI_D_VERBOSE, "Device address: %d\n", QhHw->DeviceAddr));
     149  DEBUG ((EFI_D_VERBOSE, "Inactive      : %d\n", QhHw->Inactive));
     150  DEBUG ((EFI_D_VERBOSE, "EP number     : %d\n", QhHw->EpNum));
     151  DEBUG ((EFI_D_VERBOSE, "EP speed      : %d\n", QhHw->EpSpeed));
     152  DEBUG ((EFI_D_VERBOSE, "DT control    : %d\n", QhHw->DtCtrl));
     153  DEBUG ((EFI_D_VERBOSE, "Reclaim head  : %d\n", QhHw->ReclaimHead));
     154  DEBUG ((EFI_D_VERBOSE, "Max packet len: %d\n", QhHw->MaxPacketLen));
     155  DEBUG ((EFI_D_VERBOSE, "Ctrl EP       : %d\n", QhHw->CtrlEp));
     156  DEBUG ((EFI_D_VERBOSE, "Nak reload    : %d\n", QhHw->NakReload));
     157
     158  DEBUG ((EFI_D_VERBOSE, "SMask         : %x\n", QhHw->SMask));
     159  DEBUG ((EFI_D_VERBOSE, "CMask         : %x\n", QhHw->CMask));
     160  DEBUG ((EFI_D_VERBOSE, "Hub address   : %d\n", QhHw->HubAddr));
     161  DEBUG ((EFI_D_VERBOSE, "Hub port      : %d\n", QhHw->PortNum));
     162  DEBUG ((EFI_D_VERBOSE, "Multiplier    : %d\n", QhHw->Multiplier));
     163
     164  DEBUG ((EFI_D_VERBOSE, "Cur QTD       : %x\n", QhHw->CurQtd));
     165
     166  DEBUG ((EFI_D_VERBOSE, "Next QTD      : %x\n", QhHw->NextQtd));
     167  DEBUG ((EFI_D_VERBOSE, "AltNext QTD   : %x\n", QhHw->AltQtd));
     168  DEBUG ((EFI_D_VERBOSE, "Status        : %x\n", QhHw->Status));
    169169
    170170  EhcDumpStatus (QhHw->Status);
    171171
    172172  if (QhHw->Pid == QTD_PID_SETUP) {
    173     DEBUG ((EFI_D_INFO, "PID           : Setup\n"));
     173    DEBUG ((EFI_D_VERBOSE, "PID           : Setup\n"));
    174174
    175175  } else if (QhHw->Pid == QTD_PID_INPUT) {
    176     DEBUG ((EFI_D_INFO, "PID           : IN\n"));
     176    DEBUG ((EFI_D_VERBOSE, "PID           : IN\n"));
    177177
    178178  } else if (QhHw->Pid == QTD_PID_OUTPUT) {
    179     DEBUG ((EFI_D_INFO, "PID           : OUT\n"));
    180   }
    181 
    182   DEBUG ((EFI_D_INFO, "Error Count   : %d\n", QhHw->ErrCnt));
    183   DEBUG ((EFI_D_INFO, "Current Page  : %d\n", QhHw->CurPage));
    184   DEBUG ((EFI_D_INFO, "IOC           : %d\n", QhHw->Ioc));
    185   DEBUG ((EFI_D_INFO, "Total Bytes   : %d\n", QhHw->TotalBytes));
    186   DEBUG ((EFI_D_INFO, "Data Toggle   : %d\n", QhHw->DataToggle));
     179    DEBUG ((EFI_D_VERBOSE, "PID           : OUT\n"));
     180  }
     181
     182  DEBUG ((EFI_D_VERBOSE, "Error Count   : %d\n", QhHw->ErrCnt));
     183  DEBUG ((EFI_D_VERBOSE, "Current Page  : %d\n", QhHw->CurPage));
     184  DEBUG ((EFI_D_VERBOSE, "IOC           : %d\n", QhHw->Ioc));
     185  DEBUG ((EFI_D_VERBOSE, "Total Bytes   : %d\n", QhHw->TotalBytes));
     186  DEBUG ((EFI_D_VERBOSE, "Data Toggle   : %d\n", QhHw->DataToggle));
    187187
    188188  for (Index = 0; Index < 5; Index++) {
    189     DEBUG ((EFI_D_INFO, "Page[%d]       : 0x%x\n", Index, QhHw->Page[Index]));
    190   }
    191 
    192   DEBUG ((EFI_D_INFO, "\n"));
     189    DEBUG ((EFI_D_VERBOSE, "Page[%d]       : 0x%x\n", Index, QhHw->Page[Index]));
     190  }
     191
     192  DEBUG ((EFI_D_VERBOSE, "\n"));
    193193
    194194  EFI_LIST_FOR_EACH (Entry, &Qh->Qtds) {
    … …  
    220220  for (Index = 0; Index < Len; Index++) {
    221221    if (Index % 16 == 0) {
    222       DEBUG ((EFI_D_INFO,"\n"));
     222      DEBUG ((EFI_D_VERBOSE,"\n"));
    223223    }
    224224
    225     DEBUG ((EFI_D_INFO, "%02x ", Buf[Index]));
    226   }
    227 
    228   DEBUG ((EFI_D_INFO, "\n"));
     225    DEBUG ((EFI_D_VERBOSE, "%02x ", Buf[Index]));
     226  }
     227
     228  DEBUG ((EFI_D_VERBOSE, "\n"));
    229229}
    230230
    … …  
    242242  UINT8   Index;
    243243
    244   DEBUG ((EFI_D_INFO, "  EHC_CAPLENGTH_OFFSET   = 0x%08x\n", EhcReadCapRegister (Ehc, EHC_CAPLENGTH_OFFSET)));
    245   DEBUG ((EFI_D_INFO, "  EHC_HCSPARAMS_OFFSET   = 0x%08x\n", EhcReadCapRegister (Ehc, EHC_HCSPARAMS_OFFSET)));
    246   DEBUG ((EFI_D_INFO, "  EHC_HCCPARAMS_OFFSET   = 0x%08x\n", EhcReadCapRegister (Ehc, EHC_HCCPARAMS_OFFSET)));
    247   DEBUG ((EFI_D_INFO, "  EHC_USBCMD_OFFSET      = 0x%08x\n", EhcReadOpReg (Ehc, EHC_USBCMD_OFFSET)));
    248   DEBUG ((EFI_D_INFO, "  EHC_USBSTS_OFFSET      = 0x%08x\n", EhcReadOpReg (Ehc, EHC_USBSTS_OFFSET)));
    249   DEBUG ((EFI_D_INFO, "  EHC_USBINTR_OFFSET     = 0x%08x\n", EhcReadOpReg (Ehc, EHC_USBINTR_OFFSET)));
    250   DEBUG ((EFI_D_INFO, "  EHC_FRINDEX_OFFSET     = 0x%08x\n", EhcReadOpReg (Ehc, EHC_FRINDEX_OFFSET)));
    251   DEBUG ((EFI_D_INFO, "  EHC_CTRLDSSEG_OFFSET   = 0x%08x\n", EhcReadOpReg (Ehc,  EHC_CTRLDSSEG_OFFSET)));
    252   DEBUG ((EFI_D_INFO, "  EHC_FRAME_BASE_OFFSET  = 0x%08x\n", EhcReadOpReg (Ehc,  EHC_FRAME_BASE_OFFSET)));
    253   DEBUG ((EFI_D_INFO, "  EHC_ASYNC_HEAD_OFFSET  = 0x%08x\n", EhcReadOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET)));
    254   DEBUG ((EFI_D_INFO, "  EHC_CONFIG_FLAG_OFFSET = 0x%08x\n", EhcReadOpReg (Ehc, EHC_CONFIG_FLAG_OFFSET)));
     244  DEBUG ((EFI_D_VERBOSE, "  EHC_CAPLENGTH_OFFSET   = 0x%08x\n", EhcReadCapRegister (Ehc, EHC_CAPLENGTH_OFFSET)));
     245  DEBUG ((EFI_D_VERBOSE, "  EHC_HCSPARAMS_OFFSET   = 0x%08x\n", EhcReadCapRegister (Ehc, EHC_HCSPARAMS_OFFSET)));
     246  DEBUG ((EFI_D_VERBOSE, "  EHC_HCCPARAMS_OFFSET   = 0x%08x\n", EhcReadCapRegister (Ehc, EHC_HCCPARAMS_OFFSET)));
     247  DEBUG ((EFI_D_VERBOSE, "  EHC_USBCMD_OFFSET      = 0x%08x\n", EhcReadOpReg (Ehc, EHC_USBCMD_OFFSET)));
     248  DEBUG ((EFI_D_VERBOSE, "  EHC_USBSTS_OFFSET      = 0x%08x\n", EhcReadOpReg (Ehc, EHC_USBSTS_OFFSET)));
     249  DEBUG ((EFI_D_VERBOSE, "  EHC_USBINTR_OFFSET     = 0x%08x\n", EhcReadOpReg (Ehc, EHC_USBINTR_OFFSET)));
     250  DEBUG ((EFI_D_VERBOSE, "  EHC_FRINDEX_OFFSET     = 0x%08x\n", EhcReadOpReg (Ehc, EHC_FRINDEX_OFFSET)));
     251  DEBUG ((EFI_D_VERBOSE, "  EHC_CTRLDSSEG_OFFSET   = 0x%08x\n", EhcReadOpReg (Ehc,  EHC_CTRLDSSEG_OFFSET)));
     252  DEBUG ((EFI_D_VERBOSE, "  EHC_FRAME_BASE_OFFSET  = 0x%08x\n", EhcReadOpReg (Ehc,  EHC_FRAME_BASE_OFFSET)));
     253  DEBUG ((EFI_D_VERBOSE, "  EHC_ASYNC_HEAD_OFFSET  = 0x%08x\n", EhcReadOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET)));
     254  DEBUG ((EFI_D_VERBOSE, "  EHC_CONFIG_FLAG_OFFSET = 0x%08x\n", EhcReadOpReg (Ehc, EHC_CONFIG_FLAG_OFFSET)));
    255255  for (Index = 0; Index < (UINT8) (Ehc->HcStructParams & HCSP_NPORTS); Index++) {
    256     DEBUG ((EFI_D_INFO, "  EHC_PORT_STAT_OFFSET(%d)  = 0x%08x\n", Index, EhcReadOpReg (Ehc, EHC_PORT_STAT_OFFSET + (4 * Index))));
    257   }
    258 }
     256    DEBUG ((EFI_D_VERBOSE, "  EHC_PORT_STAT_OFFSET(%d)  = 0x%08x\n", Index, EhcReadOpReg (Ehc, EHC_PORT_STAT_OFFSET + (4 * Index))));
     257  }
     258}

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf

    r48674 r58459  
    11## @file
    2 # 
    3 #  Component Description File For EhciDxe Module.
    4 #
    5 #  EhciDxe driver is responsible for managing the behavior of EHCI controller.
     2#  The EhciDxe driver is responsible for managing the behavior of EHCI controller.
    63#  It implements the interfaces of monitoring the status of all ports and transferring
    74#  Control, Bulk, Interrupt and Isochronous requests to Usb2.0 device.
    … …  
    129#  controller when UHCI gets attached earlier than EHCI and a USB 2.0 device inserts.
    1310#
    14 #  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
     11#  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
    1512#
    1613#  This program and the accompanying materials
    … …  
    2825  INF_VERSION                    = 0x00010005
    2926  BASE_NAME                      = EhciDxe
     27  MODULE_UNI_FILE                = EhciDxe.uni
    3028  FILE_GUID                      = BDFE430E-8F2A-4db0-9991-6F856594777E
    3129  MODULE_TYPE                    = UEFI_DRIVER
    … …  
    6563
    6664[FeaturePcd]
    67   gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport  ## SOMETIME_CONSUMES (enable/disable usb legacy support.)
     65  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport  ## CONSUMES
    6866
    6967[LibraryClasses]
    … …  
    7674  DebugLib
    7775  PcdLib
     76  ReportStatusCodeLib
    7877
    7978[Guids]
    80   gEfiEventExitBootServicesGuid                 ## PRODUCES ## Event
     79  gEfiEventExitBootServicesGuid                 ## SOMETIMES_CONSUMES ## Event
    8180
    8281[Protocols]
    … …  
    8584
    8685# [Event]
    87 #   ##
    88 #   # Periodic timer event for checking the result of interrupt transfer execution.
    89 #   #
    90 #   EVENT_TYPE_PERIODIC_TIMER                   ## PRODUCES
     86# EVENT_TYPE_PERIODIC_TIMER       ## CONSUMES
    9187#
     88
     89[UserExtensions.TianoCore."ExtraFiles"]
     90  EhciDxeExtra.uni

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c

    r48674 r58459  
    33  EHCI transfer scheduling routines.
    44
    5 Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2007 - 2013, Intel Corporation. All rights reserved.<BR>
    66This program and the accompanying materials
    77are licensed and made available under the terms and conditions of the BSD License
    … …  
    642642        PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));
    643643        if (QtdHw->AltNext == QTD_LINK (PciAddr, FALSE)) {
    644           DEBUG ((EFI_D_INFO, "EhcCheckUrbResult: Short packet read, break\n"));
     644          DEBUG ((EFI_D_VERBOSE, "EhcCheckUrbResult: Short packet read, break\n"));
    645645
    646646          Finished = TRUE;
    … …  
    648648        }
    649649
    650         DEBUG ((EFI_D_INFO, "EhcCheckUrbResult: Short packet read, continue\n"));
     650        DEBUG ((EFI_D_VERBOSE, "EhcCheckUrbResult: Short packet read, continue\n"));
    651651      }
    652652    }
    … …  
    695695
    696696  Status       = EFI_SUCCESS;
    697   Loop         = (TimeOut * EHC_1_MILLISECOND / EHC_SYNC_POLL_INTERVAL) + 1;
     697  Loop         = TimeOut * EHC_1_MILLISECOND;
    698698  Finished     = FALSE;
    699699  InfiniteLoop = FALSE;
    … …  
    715715    }
    716716
    717     gBS->Stall (EHC_SYNC_POLL_INTERVAL);
     717    gBS->Stall (EHC_1_MICROSECOND);
    718718  }
    719719

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.c

    r48674 r58459  
    33  Routine procedures for memory allocate/free.
    44
    5 Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2007 - 2013, Intel Corporation. All rights reserved.<BR>
    66This program and the accompanying materials
    77are licensed and made available under the terms and conditions of the BSD License
    … …  
    477477
    478478  if (NewBlock == NULL) {
    479     DEBUG ((EFI_D_INFO, "UsbHcAllocateMem: failed to allocate block\n"));
     479    DEBUG ((EFI_D_ERROR, "UsbHcAllocateMem: failed to allocate block\n"));
    480480    return NULL;
    481481  }

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.c

    r48674 r58459  
    33which is used to enable recovery function from USB Drivers.
    44
    5 Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
    66 
    77This program and the accompanying materials
    … …  
    402402
    403403/**
     404  Power On All EHCI Ports.
     405 
     406  @param  Ehc             The EHCI device.
     407
     408**/
     409VOID
     410EhcPowerOnAllPorts (
     411  IN PEI_USB2_HC_DEV          *Ehc
     412  )
     413{
     414  UINT8 PortNumber;
     415  UINT8 Index;
     416
     417  PortNumber = (UINT8)(Ehc->HcStructParams & HCSP_NPORTS);
     418  for (Index = 0; Index < PortNumber; Index++) {
     419    EhcSetOpRegBit (Ehc, EHC_PORT_STAT_OFFSET + 4 * Index, PORTSC_POWER);
     420  }
     421}
     422
     423/**
    404424  Initialize the HC hardware.
    405425  EHCI spec lists the five things to do to initialize the hardware.
    … …  
    444464    return Status;
    445465  }
     466
     467  EhcPowerOnAllPorts (Ehc); 
     468  MicroSecondDelay (EHC_ROOT_PORT_RECOVERY_STALL);
    446469 
    447470  Status = EhcInitSched (Ehc);
    … …  
    510533  @param  TimeOut               Indicates the maximum time, in millisecond, which the
    511534                                transfer is allowed to complete.
     535                                If Timeout is 0, then the caller must wait for the function
     536                                to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
    512537  @param  Translator            A pointr to the transaction translator data.                               
    513538  @param  TransferResult        A pointer to the detailed result information of the
    … …  
    973998  @param  DataLength             The size (in bytes) of the data buffer.
    974999  @param  TimeOut                Indicates the maximum timeout, in millisecond.
     1000                                 If Timeout is 0, then the caller must wait for the function
     1001                                 to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
    9751002  @param  Translator             Transaction translator to be used by this device.
    9761003  @param  TransferResult         Return the result of this control transfer.

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf

    r48674 r58459  
    11## @file
    2 # Component description file for EhcPeim PEIM to produce gPeiUsb2HostControllerPpiGuid
    3 # based on gPeiUsbControllerPpiGuid which is used to enable recovery function from USB Drivers.
     2# The EhcPeim driver is responsible for managing EHCI host controller at PEI phase.
    43#
    5 # Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
     4# It produces gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid
     5# which is used to enable recovery function from USB Drivers.
     6#
     7# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
    68#
    79# This program and the accompanying materials
    … …  
    1921  INF_VERSION                    = 0x00010005
    2022  BASE_NAME                      = EhciPei
     23  MODULE_UNI_FILE                = EhciPei.uni
    2124  FILE_GUID                      = BAB4F20F-0981-4b5f-A047-6EF83BEEAB3C
    2225  MODULE_TYPE                    = PEIM
    … …  
    5760
    5861[Ppis]
    59   gPeiUsb2HostControllerPpiGuid                 # PPI ALWAYS_PRODUCED
    60   gPeiUsbControllerPpiGuid                      # PPI ALWAYS_CONSUMED
     62  gPeiUsb2HostControllerPpiGuid                 ## PRODUCES
     63  gPeiUsbControllerPpiGuid                      ## CONSUMES
    6164
    6265
    … …  
    6467  gEfiPeiMemoryDiscoveredPpiGuid AND gPeiUsbControllerPpiGuid AND gEfiPeiBootInRecoveryModePpiGuid
    6568
    66 
     69[UserExtensions.TianoCore."ExtraFiles"]
     70  EhciPeiExtra.uni

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.c

    r48674 r58459  
    33which is used to enable recovery function from USB Drivers.
    44
    5 Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
    66 
    77This program and the accompanying materials
    … …  
    426426  UINTN                   Loop;
    427427  BOOLEAN                 Finished;
     428  BOOLEAN                 InfiniteLoop;
    428429
    429430  Status    = EFI_SUCCESS;
    430   Loop      = (TimeOut * EHC_1_MILLISECOND / EHC_SYNC_POLL_INTERVAL) + 1;
    431   Finished  = FALSE;
    432 
    433   for (Index = 0; Index < Loop; Index++) {
     431  Loop      = TimeOut * EHC_1_MILLISECOND;
     432  Finished     = FALSE;
     433  InfiniteLoop = FALSE;
     434
     435  //
     436  // If Timeout is 0, then the caller must wait for the function to be completed
     437  // until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
     438  //
     439  if (TimeOut == 0) {
     440    InfiniteLoop = TRUE;
     441  }
     442
     443  for (Index = 0; InfiniteLoop || (Index < Loop); Index++) {
    434444    Finished = EhcCheckUrbResult (Ehc, Urb);
    435445
    … …  
    438448    }
    439449
    440     MicroSecondDelay (EHC_SYNC_POLL_INTERVAL);
     450    MicroSecondDelay (EHC_1_MICROSECOND);
    441451  }
    442452

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c

    r48674 r58459  
    44for Atapi CD ROM device.
    55
    6 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
     6Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
    77
    88This program and the accompanying materials
    … …  
    14431443  //
    14441444  ZeroMem (&Packet, sizeof (ATAPI_PACKET_COMMAND));
     1445  ZeroMem (&Idata, sizeof (ATAPI_INQUIRY_DATA));
    14451446
    14461447  Packet.Inquiry.opcode             = ATA_CMD_INQUIRY;

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/IdeBusPei/IdeBusPei.inf

    r48674 r58459  
    11## @file
    22# PEIM to produce gEfiPeiVirtualBlockIoPpiGuid PPI for ATA controllers in the platform.
    3 # This PPI canl be consumed by PEIM which produce gEfiPeiDeviceRecoveryModulePpiGuid
     3# This PPI can be consumed by PEIM which produce gEfiPeiDeviceRecoveryModulePpiGuid
    44# for Atapi CD ROM device.
    55#
    66# This module discovers CDROM devices in Legacy and native mode and installs block IO ppis for them.
    7 # Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
     7# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
    88#
    99# This program and the accompanying materials
    … …  
    2121  INF_VERSION                    = 0x00010005
    2222  BASE_NAME                      = IdeBusPei
     23  MODULE_UNI_FILE                = IdeBusPei.uni
    2324  FILE_GUID                      = B7A5041A-78BA-49e3-B73B-54C757811FB6
    2425  MODULE_TYPE                    = PEIM
    … …  
    5253  PeiServicesTablePointerLib
    5354  MemoryAllocationLib
     55  PcdLib
    5456
    5557[Ppis]
    56   gPeiAtaControllerPpiGuid                      # PPI ALWAYS_CONSUMED
    57   gEfiPeiVirtualBlockIoPpiGuid                  # PPI ALWAYS_PRODUCED
     58  gPeiAtaControllerPpiGuid                      ## CONSUMES
     59  gEfiPeiVirtualBlockIoPpiGuid                  ## PRODUCES
    5860 
    5961[Pcd]
    60   gEfiMdeModulePkgTokenSpaceGuid.PcdSataSpinUpDelayInSecForRecoveryPath
     62  gEfiMdeModulePkgTokenSpaceGuid.PcdSataSpinUpDelayInSecForRecoveryPath   ## CONSUMES
    6163
    6264[Depex]
    6365  gEfiPeiMemoryDiscoveredPpiGuid AND gEfiPeiBootInRecoveryModePpiGuid AND gPeiAtaControllerPpiGuid
    6466
    65 
    66 
     67[UserExtensions.TianoCore."ExtraFiles"]
     68  IdeBusPeiExtra.uni

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupportDxe.inf

    r48674 r58459  
    55#  pci devices list template.
    66#
    7 #  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
     7#  Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
    88#
    99#  This program and the accompanying materials
    … …  
    2020  INF_VERSION                    = 0x00010005
    2121  BASE_NAME                      = IncompatiblePciDeviceSupport
     22  MODULE_UNI_FILE                = IncompatiblePciDeviceSupport.uni
    2223  FILE_GUID                      = AD70855E-0CC5-4abf-8979-BE762A949EA3
    2324  MODULE_TYPE                    = DXE_DRIVER
    … …  
    4445
    4546[Protocols]
    46   gEfiIncompatiblePciDeviceSupportProtocolGuid    ## PRODUCEDS
     47  gEfiIncompatiblePciDeviceSupportProtocolGuid    ## PRODUCES
    4748
    4849[Depex]
    4950  TRUE
     51
     52[UserExtensions.TianoCore."ExtraFiles"]
     53  IncompatiblePciDeviceSupportExtra.uni

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c

    r48674 r58459  
    99  PCI Root Bus and install PCI Host Bridge Resource Allocation Protocol.
    1010
    11 Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
     11Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
    1212This program and the accompanying materials
    1313are licensed and made available under the terms and conditions of the BSD License
    … …  
    240240  )
    241241{
    242   EFI_STATUS  Status;
     242  EFI_STATUS                Status;
     243  EFI_DEVICE_PATH_PROTOCOL  *ParentDevicePath;
    243244
    244245  //
    … …  
    284285  } 
    285286
    286   gFullEnumeration = (BOOLEAN) ((SearchHostBridgeHandle (Controller) ? FALSE : TRUE));
     287  if (PcdGetBool (PcdPciDisableBusEnumeration)) {
     288    gFullEnumeration = FALSE;
     289  } else {
     290    gFullEnumeration = (BOOLEAN) ((SearchHostBridgeHandle (Controller) ? FALSE : TRUE));
     291  }
     292
     293  //
     294  // Open Device Path Protocol for PCI root bridge
     295  //
     296  Status = gBS->OpenProtocol (
     297                  Controller,
     298                  &gEfiDevicePathProtocolGuid,
     299                  (VOID **) &ParentDevicePath,
     300                  This->DriverBindingHandle,
     301                  Controller,
     302                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
     303                  ); 
     304  ASSERT_EFI_ERROR (Status);
     305
     306  //
     307  // Report Status Code to indicate PCI bus starts
     308  //
     309  REPORT_STATUS_CODE_WITH_DEVICE_PATH (
     310    EFI_PROGRESS_CODE,
     311    (EFI_IO_BUS_PCI | EFI_IOB_PC_INIT),
     312    ParentDevicePath
     313    );
    287314
    288315  //

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h

    r48674 r58459  
    22  Header files and data structures needed by PCI Bus module.
    33
    4 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
    55This program and the accompanying materials
    66are licensed and made available under the terms and conditions of the BSD License
    … …  
    3333#include <Protocol/PciOverride.h>
    3434#include <Protocol/PciEnumerationComplete.h>
    35 #include <Protocol/DevicePathToText.h>
    3635
    3736#include <Library/DebugLib.h>

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf

    r48674 r58459  
    11## @file
    2 #  Component description file for PciBus module.
     2#  The PCI bus driver will probe all PCI devices and allocate MMIO and IO space for these devices.
     3#  Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable hot plug supporting.
    34#
    4 #  PCI bus driver. This module will probe all PCI devices and allocate MMIO and IO
    5 #  space for these devices. Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable
    6 #  hot plug supporting.
    7 #
    8 #  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
     5#  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
    96#
    107#  This program and the accompanying materials
    … …  
    2118  INF_VERSION                    = 0x00010005
    2219  BASE_NAME                      = PciBusDxe
     20  MODULE_UNI_FILE                = PciBusDxe.uni
    2321  FILE_GUID                      = 93B80004-9FB3-11d4-9A3A-0090273FC14D
    2422  MODULE_TYPE                    = UEFI_DRIVER
    … …  
    8482
    8583[Protocols]
    86   gEfiPciHotPlugRequestProtocolGuid               ## BY_START
     84  gEfiPciHotPlugRequestProtocolGuid               ## SOMETIMES_PRODUCES
    8785  gEfiPciIoProtocolGuid                           ## BY_START
    8886  gEfiDevicePathProtocolGuid                      ## BY_START
    8987  gEfiBusSpecificDriverOverrideProtocolGuid       ## BY_START
    90   gEfiLoadedImageProtocolGuid                     ## CONSUMED
    91   gEfiDecompressProtocolGuid                      ## CONSUMED
    92   gEfiPciHotPlugInitProtocolGuid                  ## CONSUMED
    93   gEfiPciHostBridgeResourceAllocationProtocolGuid ## CONSUMED
    94   gEfiPciPlatformProtocolGuid                     ## CONSUMED
    95   gEfiPciOverrideProtocolGuid                     ## CONSUMED
    96   gEfiPciEnumerationCompleteProtocolGuid          ## CONSUMED
    97   gEfiPciRootBridgeIoProtocolGuid                 ## CONSUMED
    98   gEfiIncompatiblePciDeviceSupportProtocolGuid    ## CONSUMED
    99   gEfiLoadFile2ProtocolGuid                       ## CONSUMED
    100   gEfiDevicePathToTextProtocolGuid                ## CONSUMED
     88  gEfiLoadedImageProtocolGuid                     ## SOMETIMES_CONSUMES
     89  gEfiDecompressProtocolGuid                      ## SOMETIMES_CONSUMES
     90  gEfiPciHotPlugInitProtocolGuid                  ## SOMETIMES_CONSUMES
     91  gEfiPciHostBridgeResourceAllocationProtocolGuid ## TO_START
     92  gEfiPciPlatformProtocolGuid                     ## SOMETIMES_CONSUMES
     93  gEfiPciOverrideProtocolGuid                     ## SOMETIMES_CONSUMES
     94  gEfiPciEnumerationCompleteProtocolGuid          ## PRODUCES
     95  gEfiPciRootBridgeIoProtocolGuid                 ## TO_START
     96  gEfiIncompatiblePciDeviceSupportProtocolGuid    ## SOMETIMES_CONSUMES
     97  gEfiLoadFile2ProtocolGuid                       ## SOMETIMES_PRODUCES
    10198
    10299[FeaturePcd]
    103   gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport
    104   gEfiMdeModulePkgTokenSpaceGuid.PcdPciBridgeIoAlignmentProbe
    105   gEfiMdeModulePkgTokenSpaceGuid.PcdUnalignedPciIoEnable
     100  gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport  ## CONSUMES
     101  gEfiMdeModulePkgTokenSpaceGuid.PcdPciBridgeIoAlignmentProbe   ## CONSUMES
     102  gEfiMdeModulePkgTokenSpaceGuid.PcdUnalignedPciIoEnable        ## CONSUMES
    106103
    107104[Pcd]
    108   gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize
    109   gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport
    110   gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport
    111   gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport
     105  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize         ## SOMETIMES_CONSUMES
     106  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport                ## CONSUMES
     107  gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport                  ## CONSUMES
     108  gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport                ## CONSUMES
     109  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration    ## SOMETIMES_CONSUMES
    112110
    113 # [Event]
    114 #   ##
    115 #   # Notify event set by CreateEventForHpc () for PCI Hot Plug controller.
    116 #   #
    117 #   EVT_NOTIFY_SIGNAL                   ## PRODUCES
    118 #
    119 #
     111[UserExtensions.TianoCore."ExtraFiles"]
     112  PciBusDxeExtra.uni

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c

    r48674 r58459  
    22  Supporting functions implementaion for PCI devices management.
    33
    4 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
    55This program and the accompanying materials
    66are licensed and made available under the terms and conditions of the BSD License
    … …  
    712712                             &Supports
    713713                             );
    714         Supports &= EFI_PCI_DEVICE_ENABLE;
     714        Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
    715715        PciIoDevice->PciIo.Attributes (
    716716                             &(PciIoDevice->PciIo),
    … …  
    764764                             &Supports
    765765                             );
    766         Supports &= EFI_PCI_DEVICE_ENABLE;
     766        Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
    767767        PciIoDevice->PciIo.Attributes (
    768768                             &(PciIoDevice->PciIo),

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c

    r48674 r58459  
    22  PCI eunmeration implementation on entire PCI bus system for PCI Bus module.
    33
    4 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
    55This program and the accompanying materials
    66are licensed and made available under the terms and conditions of the BSD License
    … …  
    3030  )
    3131{
    32   EFI_HANDLE                                        Handle;
    3332  EFI_HANDLE                                        HostBridgeHandle;
    3433  EFI_STATUS                                        Status;
    … …  
    8382  // Notify the pci bus enumeration is about to begin
    8483  //
    85   NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);
    86 
    87   //
    88   // Start the bus allocation phase
    89   //
    90   Status = PciHostBridgeEnumerator (PciResAlloc);
     84  Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);
    9185
    9286  if (EFI_ERROR (Status)) {
    … …  
    9589
    9690  //
    97   // Submit the resource request
    98   //
    99   Status = PciHostBridgeResourceAllocator (PciResAlloc);
     91  // Start the bus allocation phase
     92  //
     93  Status = PciHostBridgeEnumerator (PciResAlloc);
    10094
    10195  if (EFI_ERROR (Status)) {
    … …  
    10498
    10599  //
     100  // Submit the resource request
     101  //
     102  Status = PciHostBridgeResourceAllocator (PciResAlloc);
     103
     104  if (EFI_ERROR (Status)) {
     105    return Status;
     106  }
     107
     108  //
    106109  // Notify the pci bus enumeration is about to complete
    107110  //
    108   NotifyPhase (PciResAlloc, EfiPciHostBridgeEndEnumeration);
     111  Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeEndEnumeration);
     112
     113  if (EFI_ERROR (Status)) {
     114    return Status;
     115  }
    109116
    110117  //
    … …  
    127134  gFullEnumeration = FALSE;
    128135
    129   Handle = NULL;
    130136  Status = gBS->InstallProtocolInterface (
    131                   &Handle,
     137                  &HostBridgeHandle,
    132138                  &gEfiPciEnumerationCompleteProtocolGuid,
    133139                  EFI_NATIVE_INTERFACE,
    … …  
    795801      InitializePciDevice (Temp);
    796802      RemoveEntryList (CurrentLink);
    797       FreePciDevice (Temp);
    798803      return EFI_SUCCESS;
    799804    }
    … …  
    10361041    Status = RejectPciDevice (PciResNode->PciDev);
    10371042    if (Status == EFI_SUCCESS) {
     1043      DEBUG ((
     1044        EFI_D_ERROR,
     1045        "PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n",
     1046        PciResNode->PciDev->BusNumber, PciResNode->PciDev->DeviceNumber, PciResNode->PciDev->FunctionNumber
     1047        ));
    10381048
    10391049      //
    … …  
    18681878  }
    18691879
    1870   return EFI_SUCCESS;
     1880  return Status;
    18711881}
    18721882
    … …  
    20962106
    20972107  if (Operation == EfiPciHotPlugRequestAdd) {
     2108    //
     2109    // Report Status Code to indicate hot plug happens
     2110    //
     2111    REPORT_STATUS_CODE_WITH_DEVICE_PATH (
     2112      EFI_PROGRESS_CODE,
     2113      (EFI_IO_BUS_PCI | EFI_IOB_PC_HOTPLUG),
     2114      Temp->DevicePath
     2115      );
    20982116
    20992117    if (NumberOfChildren != NULL) {

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c

    r48674 r58459  
    22  PCI emumeration support functions implementation for PCI Bus module.
    33
    4 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
    55This program and the accompanying materials
    66are licensed and made available under the terms and conditions of the BSD License
    … …  
    335335    DEBUG ((
    336336      EFI_D_INFO,
    337       "   BAR[%d]: Type = %s; Alignment = 0x%x;\tLength = 0x%x;\tOffset = 0x%02x\n",
     337      "   BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
    338338      Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTypeMaxType)],
    339339      PciIoDevice->PciBar[Index].Alignment, PciIoDevice->PciBar[Index].Length, PciIoDevice->PciBar[Index].Offset
    … …  
    348348    DEBUG ((
    349349      EFI_D_INFO,
    350       " VFBAR[%d]: Type = %s; Alignment = 0x%x;\tLength = 0x%x;\tOffset = 0x%02x\n",
     350      " VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
    351351      Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBarTypeMaxType)],
    352352      PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice->VfPciBar[Index].Length, PciIoDevice->VfPciBar[Index].Offset
    … …  
    392392    return NULL;
    393393  }
    394 
    395   //
    396   // Create a device path for this PCI device and store it into its private data
    397   //
    398   CreatePciDevicePath (
    399     Bridge->DevicePath,
    400     PciIoDevice
    401     );
    402394
    403395  //
    … …  
    475467    return NULL;
    476468  }
    477 
    478   //
    479   // Create a device path for this PCI device and store it into its private data
    480   //
    481   CreatePciDevicePath (
    482     Bridge->DevicePath,
    483     PciIoDevice
    484     );
    485469
    486470  if (gFullEnumeration) {
    … …  
    635619  }
    636620
    637   //
    638   // Create a device path for this PCI device and store it into its private data
    639   //
    640   CreatePciDevicePath (
    641     Bridge->DevicePath,
    642     PciIoDevice
    643     );
    644 
    645621  if (gFullEnumeration) {
    646622    PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
    … …  
    972948  if (Option == EFI_SET_SUPPORTS) {
    973949
    974     Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |
     950    Attributes |= (UINT64) (EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |
    975951                  EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED        |
    976952                  EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE       |
    977953                  EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE      |
    978954                  EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM         |
    979                   EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE;
     955                  EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
    980956
    981957    if (IS_PCI_LPC (&PciIoDevice->Pci)) {
    982958        Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO;
    983         Attributes |= (mReserveIsaAliases ? EFI_PCI_IO_ATTRIBUTE_ISA_IO : \
    984                                             EFI_PCI_IO_ATTRIBUTE_ISA_IO_16);
     959        Attributes |= (mReserveIsaAliases ? (UINT64) EFI_PCI_IO_ATTRIBUTE_ISA_IO : \
     960                                            (UINT64) EFI_PCI_IO_ATTRIBUTE_ISA_IO_16);
    985961    }
    986962
    … …  
    1008984      if (IS_PCI_VGA (&PciIoDevice->Pci)) {
    1009985        Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY;
    1010         Attributes |= (mReserveVgaAliases ? EFI_PCI_IO_ATTRIBUTE_VGA_IO : \
    1011                                             EFI_PCI_IO_ATTRIBUTE_VGA_IO_16);
     986        Attributes |= (mReserveVgaAliases ? (UINT64) EFI_PCI_IO_ATTRIBUTE_VGA_IO : \
     987                                            (UINT64) EFI_PCI_IO_ATTRIBUTE_VGA_IO_16);
    1012988      }
    1013989    }
    … …  
    11451121    // Assume the PCI Root Bridge supports DAC
    11461122    //
    1147     PciIoDevice->Supports |= (EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
     1123    PciIoDevice->Supports |= (UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
    11481124                              EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
    11491125                              EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
    … …  
    14741450  UINT32      OriginalValue;
    14751451  UINT32      Mask;
    1476   UINT32      Data;
    1477   UINT8       Index;
    14781452  EFI_STATUS  Status;
    14791453
    … …  
    15931567      // Fix the length to support some spefic 64 bit BAR
    15941568      //
    1595       Data  = Value;
    1596       Index = 0;
    1597       for (Data = Value; Data != 0; Data >>= 1) {
    1598         Index ++;
    1599       }
    1600       Value |= ((UINT32)(-1) << Index);
     1569      Value |= ((UINT32) -1 << HighBitSet32 (Value));
    16011570
    16021571      //
    … …  
    16731642  UINT32      OriginalValue;
    16741643  UINT32      Mask;
    1675   UINT32      Data;
    1676   UINT8       Index;
    16771644  EFI_STATUS  Status;
    16781645
    … …  
    18111778      // Fix the length to support some spefic 64 bit BAR
    18121779      //
    1813       Data  = Value;
    1814       Index = 0;
    1815       for (Data = Value; Data != 0; Data >>= 1) {
    1816         Index ++;
    1817       }
    1818       Value |= ((UINT32)(-1) << Index);
     1780      Value |= ((UINT32)(-1) << HighBitSet32 (Value));
    18191781
    18201782      //
    … …  
    20422004  InitializePciLoadFile2 (PciIoDevice);
    20432005  PciIo = &PciIoDevice->PciIo;
     2006
     2007  //
     2008  // Create a device path for this PCI device and store it into its private data
     2009  //
     2010  CreatePciDevicePath (
     2011    Bridge->DevicePath,
     2012    PciIoDevice
     2013    );
    20442014
    20452015  //

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c

    r48674 r58459  
    22  EFI PCI IO protocol functions implementation for PCI Bus module.
    33
    4 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
    55This program and the accompanying materials
    66are licensed and made available under the terms and conditions of the BSD License
    … …  
    8686  )
    8787{
    88   if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
     88  if ((UINT32)Width >= EfiPciIoWidthMaximum) {
    8989    return EFI_INVALID_PARAMETER;
    9090  }
    … …  
    147147  UINT64  ExtendOffset;
    148148
    149   if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
     149  if ((UINT32)Width >= EfiPciIoWidthMaximum) {
    150150    return EFI_INVALID_PARAMETER;
    151151  }
    … …  
    216216  PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
    217217
    218   if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
     218  if ((UINT32)Width >= EfiPciIoWidthMaximum) {
    219219    return EFI_INVALID_PARAMETER;
    220220  }
    … …  
    323323  PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
    324324
    325   if (Width < 0 || Width > EfiPciIoWidthUint64) {
     325  if ((UINT32)Width > EfiPciIoWidthUint64) {
    326326    return EFI_INVALID_PARAMETER;
    327327  }
    … …  
    422422  PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
    423423
    424   if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
     424  if ((UINT32)Width >= EfiPciIoWidthMaximum) {
    425425    return EFI_INVALID_PARAMETER;
    426426  }
    … …  
    501501  PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
    502502
    503   if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
     503  if ((UINT32)Width >= EfiPciIoWidthMaximum) {
    504504    return EFI_INVALID_PARAMETER;
    505505  }
    … …  
    579579  PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
    580580
    581   if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
     581  if ((UINT32)Width >= EfiPciIoWidthMaximum) {
    582582    return EFI_INVALID_PARAMETER;
    583583  }
    … …  
    657657  PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
    658658
    659   if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
     659  if ((UINT32)Width >= EfiPciIoWidthMaximum) {
    660660    return EFI_INVALID_PARAMETER;
    661661  }
    … …  
    882882  PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
    883883
    884   if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
     884  if ((UINT32)Width >= EfiPciIoWidthMaximum) {
    885885    return EFI_INVALID_PARAMETER;
    886886  }
    … …  
    971971  PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
    972972
    973   if (Operation < 0 || Operation >= EfiPciIoOperationMaximum) {
     973  if ((UINT32)Operation >= EfiPciIoOperationMaximum) {
    974974    return EFI_INVALID_PARAMETER;
    975975  }
    … …  
    14491449    if (Operation == EfiPciIoAttributeOperationEnable) {
    14501450      PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
    1451       Temp->Attributes &= (~EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
     1451      Temp->Attributes &= (~(UINT64)EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
    14521452    } else {
    14531453      return EFI_UNSUPPORTED;
    … …  
    17801780  )
    17811781{
    1782 
    17831782  UINT8                             *Configuration;
    1784   UINT8                             NumConfig;
    17851783  PCI_IO_DEVICE                     *PciIoDevice;
    1786   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
    1787   EFI_ACPI_END_TAG_DESCRIPTOR       *PtrEnd;
    1788 
    1789   NumConfig   = 0;
     1784  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AddressSpace;
     1785  EFI_ACPI_END_TAG_DESCRIPTOR       *End;
    17901786
    17911787  PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
    … …  
    17951791  }
    17961792
    1797   if (BarIndex >= PCI_MAX_BAR) {
     1793  if ((BarIndex >= PCI_MAX_BAR) || (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown)) {
    17981794    return EFI_UNSUPPORTED;
    17991795  }
    … …  
    18081804
    18091805  if (Resources != NULL) {
    1810 
    1811     if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeUnknown) {
    1812       NumConfig = 1;
    1813     }
    1814 
    1815     Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
     1806    Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
    18161807    if (Configuration == NULL) {
    18171808      return EFI_OUT_OF_RESOURCES;
    18181809    }
    18191810
    1820     Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
    1821 
    1822     if (NumConfig == 1) {
    1823       Ptr->Desc         = ACPI_ADDRESS_SPACE_DESCRIPTOR;
    1824       Ptr->Len          = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
    1825 
    1826       Ptr->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;
    1827       Ptr->AddrLen      = PciIoDevice->PciBar[BarIndex].Length;
    1828       Ptr->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;
    1829 
    1830       switch (PciIoDevice->PciBar[BarIndex].BarType) {
    1831       case PciBarTypeIo16:
    1832       case PciBarTypeIo32:
    1833         //
    1834         // Io
    1835         //
    1836         Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
    1837         break;
    1838 
    1839       case PciBarTypeMem32:
    1840         //
    1841         // Mem
    1842         //
    1843         Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
    1844         //
    1845         // 32 bit
    1846         //
    1847         Ptr->AddrSpaceGranularity = 32;
    1848         break;
    1849 
    1850       case PciBarTypePMem32:
    1851         //
    1852         // Mem
    1853         //
    1854         Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
    1855         //
    1856         // prefechable
    1857         //
    1858         Ptr->SpecificFlag = 0x6;
    1859         //
    1860         // 32 bit
    1861         //
    1862         Ptr->AddrSpaceGranularity = 32;
    1863         break;
    1864 
    1865       case PciBarTypeMem64:
    1866         //
    1867         // Mem
    1868         //
    1869         Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
    1870         //
    1871         // 64 bit
    1872         //
    1873         Ptr->AddrSpaceGranularity = 64;
    1874         break;
    1875 
    1876       case PciBarTypePMem64:
    1877         //
    1878         // Mem
    1879         //
    1880         Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
    1881         //
    1882         // prefechable
    1883         //
    1884         Ptr->SpecificFlag = 0x6;
    1885         //
    1886         // 64 bit
    1887         //
    1888         Ptr->AddrSpaceGranularity = 64;
    1889         break;
    1890 
    1891       default:
    1892         break;
    1893       }
    1894 
    1895       Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));
     1811    AddressSpace = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
     1812
     1813    AddressSpace->Desc         = ACPI_ADDRESS_SPACE_DESCRIPTOR;
     1814    AddressSpace->Len          = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
     1815
     1816    AddressSpace->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;
     1817    AddressSpace->AddrLen      = PciIoDevice->PciBar[BarIndex].Length;
     1818    AddressSpace->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;
     1819
     1820    switch (PciIoDevice->PciBar[BarIndex].BarType) {
     1821    case PciBarTypeIo16:
     1822    case PciBarTypeIo32:
     1823      //
     1824      // Io
     1825      //
     1826      AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
     1827      break;
     1828
     1829    case PciBarTypeMem32:
     1830      //
     1831      // Mem
     1832      //
     1833      AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
     1834      //
     1835      // 32 bit
     1836      //
     1837      AddressSpace->AddrSpaceGranularity = 32;
     1838      break;
     1839
     1840    case PciBarTypePMem32:
     1841      //
     1842      // Mem
     1843      //
     1844      AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
     1845      //
     1846      // prefechable
     1847      //
     1848      AddressSpace->SpecificFlag = 0x6;
     1849      //
     1850      // 32 bit
     1851      //
     1852      AddressSpace->AddrSpaceGranularity = 32;
     1853      break;
     1854
     1855    case PciBarTypeMem64:
     1856      //
     1857      // Mem
     1858      //
     1859      AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
     1860      //
     1861      // 64 bit
     1862      //
     1863      AddressSpace->AddrSpaceGranularity = 64;
     1864      break;
     1865
     1866    case PciBarTypePMem64:
     1867      //
     1868      // Mem
     1869      //
     1870      AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
     1871      //
     1872      // prefechable
     1873      //
     1874      AddressSpace->SpecificFlag = 0x6;
     1875      //
     1876      // 64 bit
     1877      //
     1878      AddressSpace->AddrSpaceGranularity = 64;
     1879      break;
     1880
     1881    default:
     1882      break;
    18961883    }
    18971884
    … …  
    18991886    // put the checksum
    19001887    //
    1901     PtrEnd            = (EFI_ACPI_END_TAG_DESCRIPTOR *) ((UINT8 *) Ptr);
    1902     PtrEnd->Desc      = ACPI_END_TAG_DESCRIPTOR;
    1903     PtrEnd->Checksum = 0;
    1904 
    1905     *Resources        = Configuration;
     1888    End           = (EFI_ACPI_END_TAG_DESCRIPTOR *) (AddressSpace + 1);
     1889    End->Desc     = ACPI_END_TAG_DESCRIPTOR;
     1890    End->Checksum = 0;
     1891
     1892    *Resources    = Configuration;
    19061893  }
    19071894

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c

    r48674 r58459  
    22  Internal library implementation for PCI Bus module.
    33
    4 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
    55This program and the accompanying materials
    66are licensed and made available under the terms and conditions of the BSD License
    … …  
    183183  if ((BridgeResource != NULL) && (BridgeResource->Length != 0)) {
    184184    DEBUG ((
    185       EFI_D_INFO, "Type = %s; Base = 0x%x;\tLength = 0x%x;\tAlignment = 0x%x\n",
     185      EFI_D_INFO, "Type = %s; Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx\n",
    186186      mBarTypeStr[MIN (BridgeResource->ResType, PciBarTypeMaxType)],
    187187      BridgeResource->PciDev->PciBar[BridgeResource->Bar].BaseAddress,
    … …  
    196196        Bar = Resource->Virtual ? Resource->PciDev->VfPciBar : Resource->PciDev->PciBar;
    197197        DEBUG ((
    198           EFI_D_INFO, " Base = 0x%x;\tLength = 0x%x;\tAlignment = 0x%x;\tOwner = %s ",
     198          EFI_D_INFO, " Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx;\tOwner = %s ",
    199199          Bar[Resource->Bar].BaseAddress, Resource->Length, Resource->Alignment,
    200200          IS_PCI_BRIDGE (&Resource->PciDev->Pci)     ? L"PPB" :
    … …  
    226226        }
    227227      } else {
    228         DEBUG ((EFI_D_INFO, " Padding:Length = 0x%x;\tAlignment = 0x%x\n", Resource->Length, Resource->Alignment));
     228        DEBUG ((EFI_D_INFO, " Padding:Length = 0x%lx;\tAlignment = 0x%lx\n", Resource->Length, Resource->Alignment));
    229229      }
    230230    }
    … …  
    291291  PCI_RESOURCE_NODE                *ChildMem64Node;
    292292  PCI_RESOURCE_NODE                *ChildPMem64Node;
    293   EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *ToText;
    294293  CHAR16                           *Str;
    295294
    … …  
    310309      ));
    311310  } else {
    312     Status = gBS->LocateProtocol (
    313                     &gEfiDevicePathToTextProtocolGuid,
    314                     NULL,
    315                     (VOID **) &ToText
    316                     );
    317     Str = NULL;
    318     if (!EFI_ERROR (Status)) {
    319       Str = ToText->ConvertDevicePathToText (
    320                       DevicePathFromHandle (Bridge->Handle),
    321                       FALSE,
    322                       FALSE
    323                       );
    324     }
     311    Str = ConvertDevicePathToText (
     312            DevicePathFromHandle (Bridge->Handle),
     313            FALSE,
     314            FALSE
     315            );
    325316    DEBUG ((EFI_D_INFO, "Root Bridge %s\n", Str != NULL ? Str : L""));
    326317    if (Str != NULL) {
    … …  
    569560                                AcpiConfig
    570561                                );
     562        //
     563        // If SubmitResources returns error, PciBus isn't able to start.
     564        // It's a fatal error so assertion is added.
     565        //
     566        DEBUG ((EFI_D_INFO, "PciBus: HostBridge->SubmitResources() - %r\n", Status));
     567        ASSERT_EFI_ERROR (Status);
    571568      }
    572569
    … …  
    599596    //
    600597    Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);
     598    DEBUG ((EFI_D_INFO, "PciBus: HostBridge->NotifyPhase(AllocateResources) - %r\n", Status));
    601599    if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
    602600      //
    … …  
    753751  // Notify pci bus driver starts to program the resource
    754752  //
    755   NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);
     753  Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);
     754
     755  if (EFI_ERROR (Status)) {
     756    return Status;
     757  }
    756758
    757759  RootBridgeDev     = NULL;
    … …  
    892894  // Notify the resource allocation phase is to end
    893895  //
    894   NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);
    895 
    896   return EFI_SUCCESS;
     896  Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);
     897
     898  return Status;
    897899}
    898900
    … …  
    14371439  // Notify the bus allocation phase is about to start
    14381440  //
    1439   NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);
     1441  Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);
     1442
     1443  if (EFI_ERROR (Status)) {
     1444    return Status;
     1445  }
    14401446
    14411447  DEBUG((EFI_D_INFO, "PCI Bus First Scanning\n"));
    … …  
    15251531    // Notify the bus allocation phase is about to start for the 2nd time
    15261532    //
    1527     NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);
     1533    Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);
     1534
     1535    if (EFI_ERROR (Status)) {
     1536      return Status;
     1537    }
    15281538
    15291539    DEBUG((EFI_D_INFO, "PCI Bus Second Scanning\n"));
    … …  
    15631573  // Notify the resource allocation phase is to start
    15641574  //
    1565   NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginResourceAllocation);
     1575  Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginResourceAllocation);
     1576
     1577  if (EFI_ERROR (Status)) {
     1578    return Status;
     1579  }
    15661580
    15671581  RootBridgeHandle = NULL;

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c

    r48674 r58459  
    22  PCI Rom supporting funtions implementation for PCI Bus module.
    33
    4 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
    55This program and the accompanying materials
    66are licensed and made available under the terms and conditions of the BSD License
    … …  
    328328  PCI_EXPANSION_ROM_HEADER  *RomHeader;
    329329  PCI_DATA_STRUCTURE        *RomPcir;
    330 
     330  UINT8                     Indicator;
     331
     332  Indicator = 0;
    331333  RomHeader = RomImage;
    332334  if (RomHeader == NULL) {
    333335    return FALSE;
    334336  }
    335   ASSERT (RomHeader->Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE);
    336 
    337   while ((UINT8 *) RomHeader < (UINT8 *) RomImage + RomSize) {
     337
     338  do {
    338339    if (RomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
    339340      RomHeader = (PCI_EXPANSION_ROM_HEADER *) ((UINT8 *) RomHeader + 512);
    … …  
    341342    }
    342343
    343     RomPcir    = (PCI_DATA_STRUCTURE *) ((UINT8 *) RomHeader + RomHeader->PcirOffset);
    344     ASSERT (RomPcir->Signature == PCI_DATA_STRUCTURE_SIGNATURE);
     344    //
     345    // The PCI Data Structure must be DWORD aligned.
     346    //
     347    if (RomHeader->PcirOffset == 0 ||
     348        (RomHeader->PcirOffset & 3) != 0 ||
     349        (UINT8 *) RomHeader + RomHeader->PcirOffset + sizeof (PCI_DATA_STRUCTURE) > (UINT8 *) RomImage + RomSize) {
     350      break;
     351    }
     352
     353    RomPcir = (PCI_DATA_STRUCTURE *) ((UINT8 *) RomHeader + RomHeader->PcirOffset);
     354    if (RomPcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) {
     355      break;
     356    }
    345357
    346358    if (RomPcir->CodeType == PCI_CODE_TYPE_EFI_IMAGE) {
    … …  
    348360    }
    349361
    350     RomHeader = (PCI_EXPANSION_ROM_HEADER *) ((UINT8 *) RomHeader + RomPcir->Length * 512);
    351   }
     362    Indicator = RomPcir->Indicator;
     363    RomHeader = (PCI_EXPANSION_ROM_HEADER *) ((UINT8 *) RomHeader + RomPcir->ImageLength * 512);
     364  } while (((UINT8 *) RomHeader < (UINT8 *) RomImage + RomSize) && ((Indicator & 0x80) == 0x00));
    352365
    353366  return FALSE;
    354367}
    355 
    356368
    357369/**

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h

    r48674 r58459  
    22  PCI Rom supporting funtions declaration for PCI Bus module.
    33
    4 Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
    55This program and the accompanying materials
    66are licensed and made available under the terms and conditions of the BSD License
    … …  
    7777  );
    7878
    79 
    8079/**
    8180  Get Pci device's oprom information.

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c

    r48674 r58459  
    22  PCI resouces support functions implemntation for PCI Bus module.
    33
    4 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
    55This program and the accompanying materials
    66are licensed and made available under the terms and conditions of the BSD License
    … …  
    14731473  case PPB_BAR_0:
    14741474  case PPB_BAR_1:
    1475     PciIo->Pci.Write (
     1475    switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {
     1476
     1477      case PciBarTypeIo16:
     1478      case PciBarTypeIo32:
     1479      case PciBarTypeMem32:
     1480      case PciBarTypePMem32:
     1481
     1482        PciIo->Pci.Write (
    14761483                 PciIo,
    14771484                 EfiPciIoWidthUint32,
    … …  
    14811488                 );
    14821489
    1483     Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
    1484     Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;
    1485 
     1490        Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
     1491        Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;
     1492        break;
     1493
     1494      case PciBarTypeMem64:
     1495      case PciBarTypePMem64:
     1496
     1497        Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
     1498
     1499        PciIo->Pci.Write (
     1500                 PciIo,
     1501                 EfiPciIoWidthUint32,
     1502                 (Node->PciDev->PciBar[Node->Bar]).Offset,
     1503                 1,
     1504                 &Address32
     1505                 );
     1506
     1507        Address32 = (UINT32) RShiftU64 (Address, 32);
     1508
     1509        PciIo->Pci.Write (
     1510                 PciIo,
     1511                 EfiPciIoWidthUint32,
     1512                 (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
     1513                 1,
     1514                 &Address32
     1515                 );
     1516
     1517        Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
     1518        Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;
     1519        break;
     1520
     1521      default:
     1522        break;
     1523    }
    14861524    break;
    14871525

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c

    r48674 r58459  
    33  The UHCI driver model and HC protocol routines.
    44
    5 Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
    66This program and the accompanying materials
    77are licensed and made available under the terms and conditions of the BSD License
    … …  
    5454  }
    5555
    56   Uhc     = UHC_FROM_USB2_HC_PROTO (This);
     56  Uhc = UHC_FROM_USB2_HC_PROTO (This);
     57
     58  if (Uhc->DevicePath != NULL) {
     59    //
     60    // Report Status Code to indicate reset happens
     61    //
     62    REPORT_STATUS_CODE_WITH_DEVICE_PATH (
     63      EFI_PROGRESS_CODE,
     64      (EFI_IO_BUS_USB | EFI_IOB_PC_RESET),
     65      Uhc->DevicePath
     66      );
     67  }
    5768
    5869  OldTpl  = gBS->RaiseTPL (UHCI_TPL);
    … …  
    14191430
    14201431  @param  PciIo                  The PCIIO to use.
     1432  @param  DevicePath             The device path of host controller.
    14211433  @param  OriginalPciAttributes  The original PCI attributes.
    14221434
    … …  
    14261438USB_HC_DEV *
    14271439UhciAllocateDev (
    1428   IN EFI_PCI_IO_PROTOCOL    *PciIo,
    1429   IN UINT64                 OriginalPciAttributes
     1440  IN EFI_PCI_IO_PROTOCOL       *PciIo,
     1441  IN EFI_DEVICE_PATH_PROTOCOL  *DevicePath,
     1442  IN UINT64                    OriginalPciAttributes
    14301443  )
    14311444{
    … …  
    14611474
    14621475  Uhc->PciIo                 = PciIo;
     1476  Uhc->DevicePath            = DevicePath;
    14631477  Uhc->OriginalPciAttributes = OriginalPciAttributes;
    14641478  Uhc->MemPool               = UsbHcInitMemPool (PciIo, TRUE, 0);
    … …  
    15371551{
    15381552  USB_HC_DEV          *Uhc;
     1553  EFI_STATUS          Status;
    15391554
    15401555  //
    … …  
    15421557  //
    15431558  Uhc = UHC_FROM_USB2_HC_PROTO (This);
     1559
     1560
     1561  Status = gBS->UninstallProtocolInterface (
     1562                  Controller,
     1563                  &gEfiUsb2HcProtocolGuid,
     1564                  &Uhc->Usb2Hc
     1565                  );
     1566  if (EFI_ERROR (Status)) {
     1567    return ;
     1568  }
     1569
    15441570  UhciStopHc (Uhc, UHC_GENERIC_TIMEOUT);
    1545 
    1546   gBS->UninstallProtocolInterface (
    1547         Controller,
    1548         &gEfiUsb2HcProtocolGuid,
    1549         &Uhc->Usb2Hc
    1550         );
    1551 
    15521571  UhciFreeAllAsyncReq (Uhc);
    15531572  UhciDestoryFrameList (Uhc);
    … …  
    15701589
    15711590  @param  Event                   Pointer to this event
    1572   @param  Context                 Event hanlder private data
     1591  @param  Context                 Event handler private data
    15731592
    15741593**/
    … …  
    16231642  UINT64              OriginalPciAttributes;
    16241643  BOOLEAN             PciAttributesSaved;
     1644  EFI_DEVICE_PATH_PROTOCOL  *HcDevicePath;
    16251645
    16261646  //
    … …  
    16411661  }
    16421662
     1663  //
     1664  // Open Device Path Protocol for on USB host controller
     1665  //
     1666  HcDevicePath = NULL;
     1667  Status = gBS->OpenProtocol (
     1668                  Controller,
     1669                  &gEfiDevicePathProtocolGuid,
     1670                  (VOID **) &HcDevicePath,
     1671                  This->DriverBindingHandle,
     1672                  Controller,
     1673                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
     1674                  );
     1675
    16431676  PciAttributesSaved = FALSE;
    16441677  //
    … …  
    16721705                    );
    16731706  if (!EFI_ERROR (Status)) {
    1674     Supports &= EFI_PCI_DEVICE_ENABLE;
     1707    Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
    16751708    Status = PciIo->Attributes (
    16761709                      PciIo,
    … …  
    16851718  }
    16861719
    1687   Uhc = UhciAllocateDev (PciIo, OriginalPciAttributes);
     1720  Uhc = UhciAllocateDev (PciIo, HcDevicePath, OriginalPciAttributes);
    16881721
    16891722  if (Uhc == NULL) {

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h

    r48674 r58459  
    33  The definition for UHCI driver model and HC protocol routines.
    44
    5 Copyright (c) 2004 - 2010, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2004 - 2012, Intel Corporation. All rights reserved.<BR>
    66This program and the accompanying materials
    77are licensed and made available under the terms and conditions of the BSD License
    … …  
    3434#include <Library/MemoryAllocationLib.h>
    3535#include <Library/PcdLib.h>
     36#include <Library/ReportStatusCodeLib.h>
    3637
    3738#include <IndustryStandard/Pci.h>
    … …  
    113114  EFI_USB2_HC_PROTOCOL      Usb2Hc;
    114115  EFI_PCI_IO_PROTOCOL       *PciIo;
     116  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;
    115117  UINT64                    OriginalPciAttributes;
    116118

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/UhciDxe/UhciDebug.c

    r48674 r58459  
    2727  )
    2828{
    29   DEBUG ((EFI_D_INFO, "&QhSw @ 0x%p\n", QhSw));
    30   DEBUG ((EFI_D_INFO, "QhSw.NextQh    - 0x%p\n", QhSw->NextQh));
    31   DEBUG ((EFI_D_INFO, "QhSw.TDs       - 0x%p\n", QhSw->TDs));
    32   DEBUG ((EFI_D_INFO, "QhSw.QhHw:\n"));
    33   DEBUG ((EFI_D_INFO, " Horizon  Link - %x\n", QhSw->QhHw.HorizonLink));
    34   DEBUG ((EFI_D_INFO, " Vertical Link - %x\n\n", QhSw->QhHw.VerticalLink));
     29  DEBUG ((EFI_D_VERBOSE, "&QhSw @ 0x%p\n", QhSw));
     30  DEBUG ((EFI_D_VERBOSE, "QhSw.NextQh    - 0x%p\n", QhSw->NextQh));
     31  DEBUG ((EFI_D_VERBOSE, "QhSw.TDs       - 0x%p\n", QhSw->TDs));
     32  DEBUG ((EFI_D_VERBOSE, "QhSw.QhHw:\n"));
     33  DEBUG ((EFI_D_VERBOSE, " Horizon  Link - %x\n", QhSw->QhHw.HorizonLink));
     34  DEBUG ((EFI_D_VERBOSE, " Vertical Link - %x\n\n", QhSw->QhHw.VerticalLink));
    3535}
    3636
    … …  
    5252
    5353  while (CurTdSw != NULL) {
    54     DEBUG ((EFI_D_INFO, "TdSw @ 0x%p\n",           CurTdSw));
    55     DEBUG ((EFI_D_INFO, "TdSw.NextTd   - 0x%p\n",  CurTdSw->NextTd));
    56     DEBUG ((EFI_D_INFO, "TdSw.DataLen  - %d\n",    CurTdSw->DataLen));
    57     DEBUG ((EFI_D_INFO, "TdSw.Data     - 0x%p\n",  CurTdSw->Data));
    58     DEBUG ((EFI_D_INFO, "TdHw:\n"));
    59     DEBUG ((EFI_D_INFO, " NextLink     - 0x%x\n",  CurTdSw->TdHw.NextLink));
    60     DEBUG ((EFI_D_INFO, " ActualLen    - %d\n",    CurTdSw->TdHw.ActualLen));
    61     DEBUG ((EFI_D_INFO, " Status       - 0x%x\n",  CurTdSw->TdHw.Status));
    62     DEBUG ((EFI_D_INFO, " IOC          - %d\n",    CurTdSw->TdHw.IntOnCpl));
    63     DEBUG ((EFI_D_INFO, " IsIsoCh      - %d\n",    CurTdSw->TdHw.IsIsoch));
    64     DEBUG ((EFI_D_INFO, " LowSpeed     - %d\n",    CurTdSw->TdHw.LowSpeed));
    65     DEBUG ((EFI_D_INFO, " ErrorCount   - %d\n",    CurTdSw->TdHw.ErrorCount));
    66     DEBUG ((EFI_D_INFO, " ShortPacket  - %d\n",    CurTdSw->TdHw.ShortPacket));
    67     DEBUG ((EFI_D_INFO, " PidCode      - 0x%x\n",  CurTdSw->TdHw.PidCode));
    68     DEBUG ((EFI_D_INFO, " DevAddr      - %d\n",    CurTdSw->TdHw.DeviceAddr));
    69     DEBUG ((EFI_D_INFO, " EndPoint     - %d\n",    CurTdSw->TdHw.EndPoint));
    70     DEBUG ((EFI_D_INFO, " DataToggle   - %d\n",    CurTdSw->TdHw.DataToggle));
    71     DEBUG ((EFI_D_INFO, " MaxPacketLen - %d\n",    CurTdSw->TdHw.MaxPacketLen));
    72     DEBUG ((EFI_D_INFO, " DataBuffer   - 0x%x\n\n",CurTdSw->TdHw.DataBuffer));
     54    DEBUG ((EFI_D_VERBOSE, "TdSw @ 0x%p\n",           CurTdSw));
     55    DEBUG ((EFI_D_VERBOSE, "TdSw.NextTd   - 0x%p\n",  CurTdSw->NextTd));
     56    DEBUG ((EFI_D_VERBOSE, "TdSw.DataLen  - %d\n",    CurTdSw->DataLen));
     57    DEBUG ((EFI_D_VERBOSE, "TdSw.Data     - 0x%p\n",  CurTdSw->Data));
     58    DEBUG ((EFI_D_VERBOSE, "TdHw:\n"));
     59    DEBUG ((EFI_D_VERBOSE, " NextLink     - 0x%x\n",  CurTdSw->TdHw.NextLink));
     60    DEBUG ((EFI_D_VERBOSE, " ActualLen    - %d\n",    CurTdSw->TdHw.ActualLen));
     61    DEBUG ((EFI_D_VERBOSE, " Status       - 0x%x\n",  CurTdSw->TdHw.Status));
     62    DEBUG ((EFI_D_VERBOSE, " IOC          - %d\n",    CurTdSw->TdHw.IntOnCpl));
     63    DEBUG ((EFI_D_VERBOSE, " IsIsoCh      - %d\n",    CurTdSw->TdHw.IsIsoch));
     64    DEBUG ((EFI_D_VERBOSE, " LowSpeed     - %d\n",    CurTdSw->TdHw.LowSpeed));
     65    DEBUG ((EFI_D_VERBOSE, " ErrorCount   - %d\n",    CurTdSw->TdHw.ErrorCount));
     66    DEBUG ((EFI_D_VERBOSE, " ShortPacket  - %d\n",    CurTdSw->TdHw.ShortPacket));
     67    DEBUG ((EFI_D_VERBOSE, " PidCode      - 0x%x\n",  CurTdSw->TdHw.PidCode));
     68    DEBUG ((EFI_D_VERBOSE, " DevAddr      - %d\n",    CurTdSw->TdHw.DeviceAddr));
     69    DEBUG ((EFI_D_VERBOSE, " EndPoint     - %d\n",    CurTdSw->TdHw.EndPoint));
     70    DEBUG ((EFI_D_VERBOSE, " DataToggle   - %d\n",    CurTdSw->TdHw.DataToggle));
     71    DEBUG ((EFI_D_VERBOSE, " MaxPacketLen - %d\n",    CurTdSw->TdHw.MaxPacketLen));
     72    DEBUG ((EFI_D_VERBOSE, " DataBuffer   - 0x%x\n\n",CurTdSw->TdHw.DataBuffer));
    7373
    7474    CurTdSw = CurTdSw->NextTd;

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf

    r48674 r58459  
    11## @file
    2 # 
    3 #  Component Description File For UhciDxe Module.
    4 #
    5 #  UhciDxe driver is responsible for managing the behavior of UHCI controller.
     2#  The UhciDxe driver is responsible for managing the behavior of UHCI controller.
    63#  It implements the interfaces of monitoring the status of all ports and transferring
    74#  Control, Bulk, Interrupt and Isochronous requests to Usb1.x device
    85#
    9 #  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
     6#  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
    107#
    118#  This program and the accompanying materials
    … …  
    2320  INF_VERSION                    = 0x00010005
    2421  BASE_NAME                      = UhciDxe
     22  MODULE_UNI_FILE                = UhciDxe.uni
    2523  FILE_GUID                      = 2FB92EFA-2EE0-4bae-9EB6-7464125E1EF7
    2624  MODULE_TYPE                    = UEFI_DRIVER
    … …  
    6159
    6260[FeaturePcd]
    63   gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport  ## SOMETIME_CONSUMES (enable/disable usb legacy support.)
     61  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport  ## CONSUMES
    6462
    6563[LibraryClasses]
    … …  
    7270  DebugLib
    7371  PcdLib
     72  ReportStatusCodeLib
    7473
    7574[Guids]
    76   gEfiEventExitBootServicesGuid                 ## PRODUCES ## Event
     75  gEfiEventExitBootServicesGuid                 ## SOMETIMES_CONSUMES ## Event
    7776
    7877[Protocols]
    … …  
    8180
    8281# [Event]
    83 #   ##
    84 #   # Periodic timer event for checking the result of interrupt transfer execution.
    85 #   #
    86 #   EVENT_TYPE_PERIODIC_TIMER                   ## PRODUCES
     82# EVENT_TYPE_PERIODIC_TIMER       ## CONSUMES
    8783#
     84
     85[UserExtensions.TianoCore."ExtraFiles"]
     86  UhciDxeExtra.uni

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c

    r48674 r58459  
    33  The EHCI register operation routines.
    44
    5 Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2007 - 2013, Intel Corporation. All rights reserved.<BR>
    66This program and the accompanying materials
    77are licensed and made available under the terms and conditions of the BSD License
    … …  
    581581  Finished     = FALSE;
    582582  Status       = EFI_SUCCESS;
    583   Delay        = (TimeOut * UHC_1_MILLISECOND / UHC_SYNC_POLL_INTERVAL) + 1;
     583  Delay        = TimeOut * UHC_1_MILLISECOND;
    584584  InfiniteLoop = FALSE;
    585585
    … …  
    603603    }
    604604
    605     gBS->Stall (UHC_SYNC_POLL_INTERVAL);
     605    gBS->Stall (UHC_1_MICROSECOND);
    606606  }
    607607

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/UhciPei/UhcPeim.c

    r48674 r58459  
    33which is used to enable recovery function from USB Drivers.
    44
    5 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved. <BR>
     5Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved. <BR>
    66 
    77This program and the accompanying materials
    … …  
    154154  @param  DataLength             The size (in bytes) of the data buffer.
    155155  @param  TimeOut                Indicates the maximum timeout, in millisecond.
     156                                 If Timeout is 0, then the caller must wait for the function
     157                                 to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
    156158  @param  TransferResult         Return the result of this control transfer.
    157159
    … …  
    392394  @param  TimeOut               Indicates the maximum time, in millisecond, which the
    393395                                transfer is allowed to complete.
     396                                If Timeout is 0, then the caller must wait for the function
     397                                to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
    394398  @param  TransferResult        A pointer to the detailed result information of the
    395399                                bulk transfer.
    … …  
    10441048    return EFI_OUT_OF_RESOURCES;
    10451049  }
    1046  
     1050  ASSERT (UhcDev->ConfigQH != NULL);
     1051
    10471052  Status = CreateQH(UhcDev, &UhcDev->BulkQH);
    10481053  if (Status != EFI_SUCCESS) {
    10491054    return EFI_OUT_OF_RESOURCES;
    10501055  }
     1056  ASSERT (UhcDev->BulkQH != NULL);
    10511057
    10521058  //
    … …  
    25092515  UINTN   ErrTDPos;
    25102516  UINTN   Delay;
     2517  BOOLEAN InfiniteLoop;
    25112518
    25122519  ErrTDPos          = 0;
    25132520  *TransferResult   = EFI_USB_NOERROR;
    25142521  *ActualLen        = 0;
    2515 
    2516   Delay = (TimeOut * STALL_1_MILLI_SECOND / 200) + 1;
     2522  InfiniteLoop      = FALSE;
     2523
     2524  Delay = TimeOut * STALL_1_MILLI_SECOND;
     2525  //
     2526  // If Timeout is 0, then the caller must wait for the function to be completed
     2527  // until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
     2528  //
     2529  if (TimeOut == 0) {
     2530    InfiniteLoop = TRUE;
     2531  }
    25172532
    25182533  do {
    … …  
    25262541      break;
    25272542    }
    2528     MicroSecondDelay (200);
     2543    MicroSecondDelay (STALL_1_MICRO_SECOND);
    25292544    Delay--;
    25302545
    2531   } while (Delay != 0);
    2532 
     2546  } while (InfiniteLoop || (Delay != 0));
    25332547
    25342548  if (*TransferResult != EFI_USB_NOERROR) {
    … …  
    25672581  UINTN   ScrollNum;
    25682582  UINTN   Delay;
     2583  BOOLEAN InfiniteLoop;
    25692584
    25702585  ErrTDPos          = 0;
    25712586  *TransferResult   = EFI_USB_NOERROR;
    25722587  *ActualLen        = 0;
    2573 
    2574   Delay = (TimeOut * STALL_1_MILLI_SECOND / 200) + 1;
     2588  InfiniteLoop      = FALSE;
     2589
     2590  Delay = TimeOut * STALL_1_MILLI_SECOND;
     2591  //
     2592  // If Timeout is 0, then the caller must wait for the function to be completed
     2593  // until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
     2594  //
     2595  if (TimeOut == 0) {
     2596    InfiniteLoop = TRUE;
     2597  }
    25752598
    25762599  do {
    … …  
    25832606      break;
    25842607    }
    2585     MicroSecondDelay (200);
     2608    MicroSecondDelay (STALL_1_MICRO_SECOND);
    25862609    Delay--;
    25872610
    2588   } while (Delay != 0);
     2611  } while (InfiniteLoop || (Delay != 0));
    25892612
    25902613  //

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/UhciPei/UhcPeim.h

    r48674 r58459  
    22Private Header file for Usb Host Controller PEIM
    33
    4 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
    55 
    66This program and the accompanying materials
    … …  
    9595#define ERROR_PACKET_ID       0x55
    9696
     97#define STALL_1_MICRO_SECOND  1
    9798#define STALL_1_MILLI_SECOND  1000
    9899

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/UhciPei/UhciPei.inf

    r48674 r58459  
    11## @file
    2 # Component description file for UhcPeim PEIM to produce gPeiUsbHostControllerPpiGuid based on gPeiUsbControllerPpiGuid
    3 # which is used to enable recovery function from USB Drivers.
     2# The UhcPeim driver is responsible for managing the behavior of UHCI controller at PEI phase.
    43#
    5 # Usb Host Controller PEIM to support recovery from USB device.
    6 # Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
     4# It produces gPeiUsbHostControllerPpiGuid based on gPeiUsbControllerPpiGuid which is used
     5# to enable recovery function from USB Drivers.
     6#
     7# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
    78#
    89# This program and the accompanying materials
    … …  
    2021  INF_VERSION                    = 0x00010005
    2122  BASE_NAME                      = UhciPei
     23  MODULE_UNI_FILE                = UhciPei.uni
    2224  FILE_GUID                      = C463CEAC-FC57-4f36-88B7-356C750C3BCA
    2325  MODULE_TYPE                    = PEIM
    … …  
    5254
    5355[Ppis]
    54   gPeiUsbHostControllerPpiGuid                  # PPI ALWAYS_PRODUCED
    55   gPeiUsbControllerPpiGuid                      # PPI ALWAYS_CONSUMED
     56  gPeiUsbHostControllerPpiGuid                  ## PRODUCES
     57  gPeiUsbControllerPpiGuid                      ## CONSUMES
    5658
    5759
    … …  
    5961  gEfiPeiMemoryDiscoveredPpiGuid AND gPeiUsbControllerPpiGuid AND gEfiPeiBootInRecoveryModePpiGuid
    6062
    61 
     63[UserExtensions.TianoCore."ExtraFiles"]
     64  UhciPeiExtra.uni

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c

    r48674 r58459  
    22  The XHCI controller driver.
    33
    4 Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
    55This program and the accompanying materials
    66are licensed and made available under the terms and conditions of the BSD License
    … …  
    3333};
    3434
     35USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {
     36  {XHC_PORTSC_CSC, EfiUsbPortConnectChange},
     37  {XHC_PORTSC_PEC, EfiUsbPortEnableChange},
     38  {XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange},
     39  {XHC_PORTSC_PRC, EfiUsbPortResetChange}
     40};
     41
    3542USB_PORT_STATE_MAP  mUsbHubPortStateMap[] = {
    3643  {XHC_HUB_PORTSC_CCS,   USB_PORT_STAT_CONNECTION},
    … …  
    4552  {XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},
    4653  {XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET}
     54};
     55
     56USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {
     57  {XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange},
     58  {XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange},
     59  {XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange},
     60  {XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange},
     61  {XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange}
    4762};
    4863
    … …  
    144159  EFI_TPL            OldTpl;
    145160
     161  Xhc = XHC_FROM_THIS (This);
     162 
     163  if (Xhc->DevicePath != NULL) {
     164    //
     165    // Report Status Code to indicate reset happens
     166    //
     167    REPORT_STATUS_CODE_WITH_DEVICE_PATH (
     168      EFI_PROGRESS_CODE,
     169      (EFI_IO_BUS_USB | EFI_IOB_PC_RESET),
     170      Xhc->DevicePath
     171      );
     172  } 
     173
    146174  OldTpl = gBS->RaiseTPL (XHC_TPL);
    147 
    148   Xhc    = XHC_FROM_THIS (This);
    149175
    150176  switch (Attributes) {
    … …  
    154180  //
    155181  case EFI_USB_HC_RESET_HOST_CONTROLLER:
     182    if ((Xhc->DebugCapSupOffset != 0xFFFFFFFF) && ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&
     183        ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0)) {
     184      Status = EFI_SUCCESS;
     185      goto ON_EXIT;
     186    }
    156187    //
    157188    // Host Controller must be Halt when Reset it
    … …  
    417448  }
    418449
     450  MapSize = sizeof (mUsbClearPortChangeMap) / sizeof (USB_CLEAR_PORT_MAP);
     451
     452  for (Index = 0; Index < MapSize; Index++) {
     453    if (XHC_BIT_IS_SET (State, mUsbClearPortChangeMap[Index].HwState)) {
     454      XhcClearRootHubPortFeature (This, PortNumber, (EFI_USB_PORT_FEATURE)mUsbClearPortChangeMap[Index].Selector);
     455    }
     456  }
     457
    419458  //
    420459  // Poll the root port status register to enable/disable corresponding device slot if there is a device attached/detached.
    … …  
    454493  UINT32                  State;
    455494  UINT32                  TotalPort;
    456   UINT8                   SlotId;
    457   USB_DEV_ROUTE           RouteChart;
    458495  EFI_STATUS              Status;
    459496  EFI_TPL                 OldTpl;
    … …  
    511548    }
    512549
    513     RouteChart.Route.RouteString = 0;
    514     RouteChart.Route.RootPortNum = PortNumber + 1;
    515     RouteChart.Route.TierNum     = 1;
    516     //
    517     // If the port reset operation happens after the usb super speed device is enabled,
    518     // The subsequent configuration, such as getting device descriptor, will fail.
    519     // So here a workaround is introduced to skip the reset operation if the device is enabled.
    520     //
    521     SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
    522     if (SlotId == 0) {
    523       //
    524       // 4.3.1 Resetting a Root Hub Port
    525       // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.
    526       //
    527       State |= XHC_PORTSC_RESET;
    528       XhcWriteOpReg (Xhc, Offset, State);
    529       XhcWaitOpRegBit(Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
    530     }
     550    //
     551    // 4.3.1 Resetting a Root Hub Port
     552    // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.
     553    //
     554    State |= XHC_PORTSC_RESET;
     555    XhcWriteOpReg (Xhc, Offset, State);
     556    XhcWaitOpRegBit(Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
    531557    break;
    532558
    … …  
    748774  EFI_USB_PORT_STATUS     PortStatus;
    749775  UINT32                  State;
     776  EFI_USB_DEVICE_REQUEST  ClearPortRequest;
     777  UINTN                   Len;
    750778
    751779  //
    … …  
    793821  Status          = EFI_DEVICE_ERROR;
    794822  *TransferResult = EFI_USB_ERR_SYSTEM;
     823  Len             = 0;
    795824
    796825  if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
    … …  
    824853      }
    825854    }
     855
     856    if (Xhc->UsbDevContext[SlotId].XhciDevAddr == 0) {
     857      Status = EFI_DEVICE_ERROR;
     858      goto ON_EXIT;
     859    }
    826860    //
    827861    // The actual device address has been assigned by XHCI during initializing the device slot.
    … …  
    833867    Status = EFI_SUCCESS;
    834868    goto ON_EXIT;
    835   }
    836  
    837   //
    838   // If the port reset operation happens after the usb super speed device is enabled,
    839   // The subsequent configuration, such as getting device descriptor, will fail.
    840   // So here a workaround is introduced to skip the reset operation if the device is enabled.
    841   //
    842   if ((Request->Request     == USB_REQ_SET_FEATURE) &&
    843       (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER)) &&
    844       (Request->Value       == EfiUsbPortReset)) {
    845     if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
    846       Status = EFI_SUCCESS;
    847       goto ON_EXIT;
    848     }
    849869  }
    850870
    … …  
    890910  } else if (*TransferResult == EFI_USB_ERR_STALL) {
    891911    RecoveryStatus = XhcRecoverHaltedEndpoint(Xhc, Urb);
    892     ASSERT_EFI_ERROR (RecoveryStatus);
     912    if (EFI_ERROR (RecoveryStatus)) {
     913      DEBUG ((EFI_D_ERROR, "XhcControlTransfer: XhcRecoverHaltedEndpoint failed\n"));
     914    }
    893915    Status = EFI_DEVICE_ERROR;
    894916    goto FREE_URB;
    … …  
    897919  }
    898920
     921  Xhc->PciIo->Flush (Xhc->PciIo);
     922 
     923  if (Urb->DataMap != NULL) {
     924    Status = Xhc->PciIo->Unmap (Xhc->PciIo, Urb->DataMap);
     925    ASSERT_EFI_ERROR (Status);
     926    if (EFI_ERROR (Status)) {
     927      Status = EFI_DEVICE_ERROR;
     928      goto FREE_URB;
     929    } 
     930  }
     931
    899932  //
    900933  // Hook Get_Descriptor request from UsbBus as we need evaluate context and configure endpoint.
    … …  
    906939      ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE))))) {
    907940    DescriptorType = (UINT8)(Request->Value >> 8);
    908     if ((DescriptorType == USB_DESC_TYPE_DEVICE) && (*DataLength == sizeof (EFI_USB_DEVICE_DESCRIPTOR))) {
     941    if ((DescriptorType == USB_DESC_TYPE_DEVICE) && ((*DataLength == sizeof (EFI_USB_DEVICE_DESCRIPTOR)) || ((DeviceSpeed == EFI_USB_SPEED_FULL) && (*DataLength == 8)))) {
    909942        ASSERT (Data != NULL);
    910943        //
    … …  
    926959          Status = XhcEvaluateContext64 (Xhc, SlotId, MaxPacket0);
    927960        }
    928         ASSERT_EFI_ERROR (Status);
    929961    } else if (DescriptorType == USB_DESC_TYPE_CONFIG) {
    930962      ASSERT (Data != NULL);
    … …  
    937969        Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool(*DataLength);
    938970        CopyMem (Xhc->UsbDevContext[SlotId].ConfDesc[Index], Data, *DataLength);
     971        //
     972        // Default to use AlternateSetting 0 for all interfaces.
     973        //
     974        Xhc->UsbDevContext[SlotId].ActiveAlternateSetting = AllocateZeroPool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]->NumInterfaces * sizeof (UINT8));
    939975      }
    940976    } else if (((DescriptorType == USB_DESC_TYPE_HUB) ||
    … …  
    962998        Status = XhcConfigHubContext64 (Xhc, SlotId, HubDesc->NumPorts, TTT, MTT);
    963999      }
    964       ASSERT_EFI_ERROR (Status);
    9651000    }
    9661001  } else if ((Request->Request     == USB_REQ_SET_CONFIG) &&
    … …  
    9761011          Status = XhcSetConfigCmd64 (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
    9771012        }
    978         ASSERT_EFI_ERROR (Status);
    9791013        break;
     1014      }
     1015    }
     1016  } else if ((Request->Request     == USB_REQ_SET_INTERFACE) &&
     1017             (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_INTERFACE))) {
     1018    //
     1019    // Hook Set_Interface request from UsbBus as we need configure interface setting.
     1020    // Request->Value indicates AlterlateSetting to set
     1021    // Request->Index indicates Interface to set
     1022    //
     1023    if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] != (UINT8) Request->Value) {
     1024      if (Xhc->HcCParams.Data.Csz == 0) {
     1025        Status = XhcSetInterface (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Xhc->UsbDevContext[SlotId].ActiveConfiguration - 1], Request);
     1026      } else {
     1027        Status = XhcSetInterface64 (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Xhc->UsbDevContext[SlotId].ActiveConfiguration - 1], Request);
    9801028      }
    9811029    }
    … …  
    9971045        PortStatus.PortStatus |= USB_PORT_STAT_SUPER_SPEED;
    9981046      }
    999     } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
     1047    } else {
    10001048      //
    1001       // For high speed hub, its bit9~10 presents the attached device speed.
     1049      // For high or full/low speed hub, its bit9~10 presents the attached device speed.
    10021050      //
    10031051      if (XHC_BIT_IS_SET (State, BIT9)) {
    … …  
    10061054        PortStatus.PortStatus |= USB_PORT_STAT_HIGH_SPEED;
    10071055      }
    1008     } else {
    1009       ASSERT (0);
    10101056    }
    10111057
    … …  
    10241070      if (XHC_BIT_IS_SET (State, mUsbHubPortChangeMap[Index].HwState)) {
    10251071        PortStatus.PortChangeStatus = (UINT16) (PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);
     1072      }
     1073    }
     1074
     1075    MapSize = sizeof (mUsbHubClearPortChangeMap) / sizeof (USB_CLEAR_PORT_MAP);
     1076
     1077    for (Index = 0; Index < MapSize; Index++) {
     1078      if (XHC_BIT_IS_SET (State, mUsbHubClearPortChangeMap[Index].HwState)) {
     1079        ZeroMem (&ClearPortRequest, sizeof (EFI_USB_DEVICE_REQUEST));
     1080        ClearPortRequest.RequestType  = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);
     1081        ClearPortRequest.Request      = (UINT8) USB_REQ_CLEAR_FEATURE;
     1082        ClearPortRequest.Value        = mUsbHubClearPortChangeMap[Index].Selector;
     1083        ClearPortRequest.Index        = Request->Index;
     1084        ClearPortRequest.Length       = 0;
     1085
     1086        XhcControlTransfer (
     1087          This,
     1088          DeviceAddress,
     1089          DeviceSpeed,
     1090          MaximumPacketLength,
     1091          &ClearPortRequest,
     1092          EfiUsbNoData,
     1093          NULL,
     1094          &Len,
     1095          Timeout,
     1096          Translator,
     1097          TransferResult
     1098          );
    10261099      }
    10271100    }
    … …  
    11731246  } else if (*TransferResult == EFI_USB_ERR_STALL) {
    11741247    RecoveryStatus = XhcRecoverHaltedEndpoint(Xhc, Urb);
    1175     ASSERT_EFI_ERROR (RecoveryStatus);
     1248    if (EFI_ERROR (RecoveryStatus)) {
     1249      DEBUG ((EFI_D_ERROR, "XhcBulkTransfer: XhcRecoverHaltedEndpoint failed\n"));
     1250    }
    11761251    Status = EFI_DEVICE_ERROR;
    11771252  }
    11781253
    1179   FreePool (Urb);
     1254  Xhc->PciIo->Flush (Xhc->PciIo);
     1255  XhcFreeUrb (Xhc, Urb);
    11801256
    11811257ON_EXIT:
    … …  
    13431419
    13441420ON_EXIT:
     1421  Xhc->PciIo->Flush (Xhc->PciIo);
    13451422  gBS->RestoreTPL (OldTpl);
    13461423
    … …  
    14701547  } else if (*TransferResult == EFI_USB_ERR_STALL) {
    14711548    RecoveryStatus = XhcRecoverHaltedEndpoint(Xhc, Urb);
    1472     ASSERT_EFI_ERROR (RecoveryStatus);
     1549    if (EFI_ERROR (RecoveryStatus)) {
     1550      DEBUG ((EFI_D_ERROR, "XhcSyncInterruptTransfer: XhcRecoverHaltedEndpoint failed\n"));
     1551    }
    14731552    Status = EFI_DEVICE_ERROR;
    14741553  }
    14751554
    1476   FreePool (Urb);
     1555  Xhc->PciIo->Flush (Xhc->PciIo);
     1556  XhcFreeUrb (Xhc, Urb);
    14771557
    14781558ON_EXIT:
    … …  
    16741754
    16751755  @param  PciIo                  The PciIo on this device.
     1756  @param  DevicePath             The device path of host controller.
    16761757  @param  OriginalPciAttributes  Original PCI attributes.
    16771758
    … …  
    16821763USB_XHCI_INSTANCE*
    16831764XhcCreateUsbHc (
    1684   IN EFI_PCI_IO_PROTOCOL  *PciIo,
    1685   IN UINT64               OriginalPciAttributes
     1765  IN EFI_PCI_IO_PROTOCOL       *PciIo,
     1766  IN EFI_DEVICE_PATH_PROTOCOL  *DevicePath,
     1767  IN UINT64                    OriginalPciAttributes
    16861768  )
    16871769{
    … …  
    17021784  Xhc->Signature             = XHCI_INSTANCE_SIG;
    17031785  Xhc->PciIo                 = PciIo;
     1786  Xhc->DevicePath            = DevicePath;
    17041787  Xhc->OriginalPciAttributes = OriginalPciAttributes;
    17051788  CopyMem (&Xhc->Usb2Hc, &gXhciUsb2HcTemplate, sizeof (EFI_USB2_HC_PROTOCOL));
    … …  
    17271810  ExtCapReg            = (UINT16) (Xhc->HcCParams.Data.ExtCapReg);
    17281811  Xhc->ExtCapRegBase   = ExtCapReg << 2;
    1729   Xhc->UsbLegSupOffset = XhcGetLegSupCapAddr (Xhc);
     1812  Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
     1813  Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG);
    17301814
    17311815  DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
    … …  
    17361820  DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
    17371821  DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));
     1822  DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));
    17381823
    17391824  //
    … …  
    17631848
    17641849  @param  Event                   Pointer to this event
    1765   @param  Context                 Event hanlder private data
     1850  @param  Context                 Event handler private data
    17661851
    17671852**/
    … …  
    17911876  }
    17921877
     1878  XhcClearBiosOwnership (Xhc);
     1879
    17931880  //
    17941881  // Restore original PCI attributes
    … …  
    18001887                  NULL
    18011888                  );
    1802 
    1803   XhcClearBiosOwnership (Xhc);
    18041889}
    18051890
    … …  
    18311916  BOOLEAN                 PciAttributesSaved;
    18321917  USB_XHCI_INSTANCE       *Xhc;
     1918  EFI_DEVICE_PATH_PROTOCOL  *HcDevicePath;
    18331919
    18341920  //
    … …  
    18481934  }
    18491935
     1936  //
     1937  // Open Device Path Protocol for on USB host controller
     1938  //
     1939  HcDevicePath = NULL;
     1940  Status = gBS->OpenProtocol (
     1941                  Controller,
     1942                  &gEfiDevicePathProtocolGuid,
     1943                  (VOID **) &HcDevicePath,
     1944                  This->DriverBindingHandle,
     1945                  Controller,
     1946                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
     1947                  );
     1948
    18501949  PciAttributesSaved = FALSE;
    18511950  //
    … …  
    18711970                    );
    18721971  if (!EFI_ERROR (Status)) {
    1873     Supports &= EFI_PCI_DEVICE_ENABLE;
     1972    Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
    18741973    Status = PciIo->Attributes (
    18751974                      PciIo,
    … …  
    18881987  // Create then install USB2_HC_PROTOCOL
    18891988  //
    1890   Xhc = XhcCreateUsbHc (PciIo, OriginalPciAttributes);
     1989  Xhc = XhcCreateUsbHc (PciIo, HcDevicePath, OriginalPciAttributes);
    18911990
    18921991  if (Xhc == NULL) {
    … …  
    20492148  }
    20502149
    2051   Xhc   = XHC_FROM_THIS (Usb2Hc);
    2052   PciIo = Xhc->PciIo;
    2053 
    2054   //
    2055   // Stop AsyncRequest Polling timer then stop the XHCI driver
    2056   // and uninstall the XHCI protocl.
    2057   //
    2058   gBS->SetTimer (Xhc->PollTimer, TimerCancel, 0);
    2059 
    2060   //
    2061   // Disable the device slots occupied by these devices on its downstream ports.
    2062   // Entry 0 is reserved.
    2063   //
    2064   for (Index = 0; Index < 255; Index++) {
    2065     if (!Xhc->UsbDevContext[Index + 1].Enabled ||
    2066         (Xhc->UsbDevContext[Index + 1].SlotId == 0)) {
    2067       continue;
    2068     }
    2069     if (Xhc->HcCParams.Data.Csz == 0) {
    2070       XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
    2071     } else {
    2072       XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
    2073     }
    2074   }
    2075 
    2076   XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
    2077   XhcClearBiosOwnership (Xhc);
    2078 
    20792150  Status = gBS->UninstallProtocolInterface (
    20802151                  Controller,
    … …  
    20872158  }
    20882159
     2160  Xhc   = XHC_FROM_THIS (Usb2Hc);
     2161  PciIo = Xhc->PciIo;
     2162
     2163  //
     2164  // Stop AsyncRequest Polling timer then stop the XHCI driver
     2165  // and uninstall the XHCI protocl.
     2166  //
     2167  gBS->SetTimer (Xhc->PollTimer, TimerCancel, 0);
     2168
     2169  //
     2170  // Disable the device slots occupied by these devices on its downstream ports.
     2171  // Entry 0 is reserved.
     2172  //
     2173  for (Index = 0; Index < 255; Index++) {
     2174    if (!Xhc->UsbDevContext[Index + 1].Enabled ||
     2175        (Xhc->UsbDevContext[Index + 1].SlotId == 0)) {
     2176      continue;
     2177    }
     2178    if (Xhc->HcCParams.Data.Csz == 0) {
     2179      XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
     2180    } else {
     2181      XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
     2182    }
     2183  }
     2184
    20892185  if (Xhc->PollTimer != NULL) {
    20902186    gBS->CloseEvent (Xhc->PollTimer);
    … …  
    20952191  }
    20962192
     2193  XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
     2194  XhcClearBiosOwnership (Xhc);
    20972195  XhciDelAllAsyncIntTransfers (Xhc);
    20982196  XhcFreeSched (Xhc);

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h

    r48674 r58459  
    33  Provides some data structure definitions used by the XHCI host controller driver.
    44
    5 Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
    66This program and the accompanying materials
    77are licensed and made available under the terms and conditions of the BSD License
    … …  
    3131#include <Library/UefiLib.h>
    3232#include <Library/DebugLib.h>
     33#include <Library/ReportStatusCodeLib.h>
    3334
    3435#include <IndustryStandard/Pci.h>
    … …  
    4041#include "XhciSched.h"
    4142#include "ComponentName.h"
    42 
     43#include "UsbHcMem.h"
     44
     45//
     46// The unit is microsecond, setting it as 1us.
     47//
     48#define XHC_1_MICROSECOND            (1)
    4349//
    4450// Convert millisecond to microsecond.
    … …  
    191197  //
    192198  EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
     199  //
     200  // A device has an active Configuration.
     201  //
     202  UINT8                     ActiveConfiguration;
     203  //
     204  // Every interface has an active AlternateSetting.
     205  //
     206  UINT8                     *ActiveAlternateSetting;
    193207};
    194208
    … …  
    197211  EFI_PCI_IO_PROTOCOL       *PciIo;
    198212  UINT64                    OriginalPciAttributes;
     213  USBHC_MEM_POOL            *MemPool;
    199214
    200215  EFI_USB2_HC_PROTOCOL      Usb2Hc;
    … …  
    219234  UINT32                    PageSize;
    220235  UINT64                    *ScratchBuf;
     236  VOID                      *ScratchMap;
    221237  UINT32                    MaxScratchpadBufs;
     238  UINT64                    *ScratchEntry;
     239  UINTN                     *ScratchEntryMap;
    222240  UINT32                    ExtCapRegBase;
    223241  UINT32                    UsbLegSupOffset;
     242  UINT32                    DebugCapSupOffset;
    224243  UINT64                    *DCBAA;
     244  VOID                      *DCBAAMap;
    225245  UINT32                    MaxSlotsEn;
    226246  //

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf

    r48674 r58459  
    11## @file
    2 #
    3 #  Component Description File For XhciDxe Module.
    4 #
    5 #  XhciDxe driver is responsible for managing the behavior of XHCI controller.
     2#  The XhciDxe driver is responsible for managing the behavior of XHCI controller.
    63#  It implements the interfaces of monitoring the status of all ports and transferring
    74#  Control, Bulk, Interrupt and Isochronous requests to those attached usb LS/FS/HS/SS devices.
    85#
    9 #  Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
     6#  Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
    107#
    118#  This program and the accompanying materials
    … …  
    2320  INF_VERSION                    = 0x00010005
    2421  BASE_NAME                      = XhciDxe
     22  MODULE_UNI_FILE                = XhciDxe.uni
    2523  FILE_GUID                      = B7F50E91-A759-412c-ADE4-DCD03E7F7C28
    2624  MODULE_TYPE                    = UEFI_DRIVER
    … …  
    4341  XhciReg.c
    4442  XhciSched.c
     43  UsbHcMem.c
     44  UsbHcMem.h 
    4545  ComponentName.c
    4646  ComponentName.h
    … …  
    6060  BaseMemoryLib
    6161  DebugLib
     62  ReportStatusCodeLib
    6263
    6364[Guids]
    64   gEfiEventExitBootServicesGuid                 ## PRODUCES ## Event
     65  gEfiEventExitBootServicesGuid                 ## SOMETIMES_CONSUMES ## Event
    6566
    6667[Protocols]
    … …  
    6970
    7071# [Event]
    71 #   ##
    72 #   # Periodic timer event for checking the result of interrupt transfer execution.
    73 #   #
    74 #   EVENT_TYPE_PERIODIC_TIMER                   ## PRODUCES
     72# EVENT_TYPE_PERIODIC_TIMER       ## CONSUMES
    7573#
     74
     75[UserExtensions.TianoCore."ExtraFiles"]
     76  XhciDxeExtra.uni

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c

    r48674 r58459  
    33  The XHCI register operation routines.
    44
    5 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
    66This program and the accompanying materials
    77are licensed and made available under the terms and conditions of the BSD License
    … …  
    500500  @param  Bit          The bit of the register to wait for.
    501501  @param  WaitToSet    Wait the bit to set or clear.
    502   @param  Timeout      The time to wait before abort (in millisecond, ms).
     502  @param  Timeout      The time to wait before abort (in microsecond, us).
    503503
    504504  @retval EFI_SUCCESS  The bit successfully changed by host controller.
    … …  
    518518  UINTN                   Loop;
    519519
    520   Loop   = (Timeout * XHC_1_MILLISECOND / XHC_POLL_DELAY) + 1;
     520  Loop   = (Timeout / XHC_POLL_DELAY) + 1;
    521521
    522522  for (Index = 0; Index < Loop; Index++) {
    … …  
    544544  UINT32                    Buffer;
    545545
     546  if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
     547    return;
     548  }
     549
    546550  DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
    547551
    … …  
    564568  UINT32                    Buffer;
    565569
     570  if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
     571    return;
     572  }
     573
    566574  DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
    567575
    … …  
    572580
    573581/**
    574   Calculate the XHCI legacy support capability register offset.
     582  Calculate the offset of the XHCI capability.
    575583
    576584  @param  Xhc     The XHCI Instance.
     585  @param  CapId   The XHCI Capability ID.
    577586
    578587  @return The offset of XHCI legacy support capability register.
    … …  
    580589**/
    581590UINT32
    582 XhcGetLegSupCapAddr (
    583   IN USB_XHCI_INSTANCE    *Xhc
     591XhcGetCapabilityAddr (
     592  IN USB_XHCI_INSTANCE    *Xhc,
     593  IN UINT8                CapId
    584594  )
    585595{
    … …  
    595605    //
    596606    Data = XhcReadExtCapReg (Xhc, ExtCapOffset);
    597     if ((Data & 0xFF) == 0x1) {
     607    if ((Data & 0xFF) == CapId) {
    598608      return ExtCapOffset;
    599609    }
    … …  
    605615  } while (NextExtCapReg != 0);
    606616
    607   return 0;
     617  return 0xFFFFFFFF;
    608618}
    609619
    … …  
    647657
    648658  @param  Xhc          The XHCI Instance.
    649   @param  Timeout      Time to wait before abort (in millisecond, ms).
     659  @param  Timeout      Time to wait before abort (in microsecond, us).
    650660
    651661  @retval EFI_SUCCESS  The XHCI host controller is reset.
    … …  
    660670{
    661671  EFI_STATUS              Status;
     672
     673  Status = EFI_SUCCESS;
    662674
    663675  DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));
    … …  
    673685  }
    674686
    675   XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
    676   Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
     687  if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||
     688      ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {
     689    XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
     690    Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
     691  }
     692
    677693  return Status;
    678694}
    … …  
    683699
    684700  @param  Xhc          The XHCI Instance.
    685   @param  Timeout      Time to wait before abort (in millisecond, ms).
     701  @param  Timeout      Time to wait before abort (in microsecond, us).
    686702
    687703  @return EFI_SUCCESS  The XHCI host controller is halt.
    … …  
    707723
    708724  @param  Xhc          The XHCI Instance.
    709   @param  Timeout      Time to wait before abort (in millisecond, ms).
     725  @param  Timeout      Time to wait before abort (in microsecond, us).
    710726
    711727  @return EFI_SUCCESS  The XHCI host controller is running.

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h

    r48674 r58459  
    33  This file contains the register definition of XHCI host controller.
    44
    5 Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
    66This program and the accompanying materials
    77are licensed and made available under the terms and conditions of the BSD License
    … …  
    2929#define USB_HUB_CLASS_CODE          0x09
    3030#define USB_HUB_SUBCLASS_CODE       0x00
     31
     32#define XHC_CAP_USB_LEGACY          0x01
     33#define XHC_CAP_USB_DEBUG           0x0A
    3134
    3235//============================================//
    … …  
    6770#define XHC_ERSTBA_OFFSET                  0x30 // Event Ring Segment Table Base Address Register Offset
    6871#define XHC_ERDP_OFFSET                    0x38 // Event Ring Dequeue Pointer Register Offset
     72
     73//
     74// Debug registers offset
     75//
     76#define XHC_DC_DCCTRL                      0x20
    6977
    7078#define USBLEGSP_BIOS_SEMAPHORE            BIT16 // HC BIOS Owned Semaphore
    … …  
    162170#define XHC_PORTSC_PLS                     (BIT5|BIT6|BIT7|BIT8)     // Port Link State
    163171#define XHC_PORTSC_PP                      BIT9  // Port Power
    164 #define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12|BIT13) // Port Speed
     172#define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12)      // Port Speed
    165173#define XHC_PORTSC_LWS                     BIT16 // Port Link State Write Strobe
    166174#define XHC_PORTSC_CSC                     BIT17 // Connect Status Change
    … …  
    182190#define XHC_HUB_PORTSC_OCC                 BIT19 // Hub's Over-Current Change
    183191#define XHC_HUB_PORTSC_PRC                 BIT20 // Hub's Port Reset Change
     192#define XHC_HUB_PORTSC_BHRC                BIT21 // Hub's Port Warm Reset Change
    184193#define XHC_IMAN_IP                        BIT0  // Interrupt Pending
    185194#define XHC_IMAN_IE                        BIT1  // Interrupt Enable
    … …  
    187196#define XHC_IMODI_MASK                     0x0000FFFF  // Interrupt Moderation Interval
    188197#define XHC_IMODC_MASK                     0xFFFF0000  // Interrupt Moderation Counter
     198
     199//
     200//  Hub Class Feature Selector for Clear Port Feature Request
     201//  It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.
     202//  For more details, Please refer to USB 3.0 Spec Table 10-7.
     203//
     204typedef enum {
     205  Usb3PortBHPortReset          = 28,
     206  Usb3PortBHPortResetChange    = 29
     207} XHC_PORT_FEATURE;
    189208
    190209//
    … …  
    197216} USB_PORT_STATE_MAP;
    198217
     218//
     219// Structure to map the hardware port states to feature selector for clear port feature request.
     220//
     221typedef struct {
     222  UINT32                  HwState;
     223  UINT16                  Selector;
     224} USB_CLEAR_PORT_MAP;
     225
    199226/**
    200227  Read 1-byte width XHCI capability register.
    … …  
    373400  @param  Bit          The bit of the register to wait for.
    374401  @param  WaitToSet    Wait the bit to set or clear.
    375   @param  Timeout      The time to wait before abort (in millisecond, ms).
     402  @param  Timeout      The time to wait before abort (in microsecond, us).
    376403
    377404  @retval EFI_SUCCESS  The bit successfully changed by host controller.
    … …  
    449476
    450477/**
     478  Read XHCI extended capability register.
     479
     480  @param  Xhc          The XHCI Instance.
     481  @param  Offset       The offset of the extended capability register.
     482
     483  @return The register content read
     484
     485**/
     486UINT32
     487XhcReadExtCapReg (
     488  IN  USB_XHCI_INSTANCE   *Xhc,
     489  IN  UINT32              Offset
     490  );
     491
     492/**
    451493  Whether the XHCI host controller is halted.
    452494
    … …  
    480522
    481523  @param  Xhc          The XHCI Instance.
    482   @param  Timeout      Time to wait before abort (in millisecond, ms).
     524  @param  Timeout      Time to wait before abort (in microsecond, us).
    483525
    484526  @retval EFI_SUCCESS  The XHCI host controller is reset.
    … …  
    496538
    497539  @param  Xhc          The XHCI Instance.
    498   @param  Timeout      Time to wait before abort (in millisecond, ms).
     540  @param  Timeout      Time to wait before abort (in microsecond, us).
    499541
    500542  @return EFI_SUCCESS  The XHCI host controller is halt.
    … …  
    512554
    513555  @param  Xhc          The XHCI Instance.
    514   @param  Timeout      Time to wait before abort (in millisecond, ms).
     556  @param  Timeout      Time to wait before abort (in microsecond, us).
    515557
    516558  @return EFI_SUCCESS  The XHCI host controller is running.
    … …  
    525567
    526568/**
    527   Calculate the XHCI legacy support capability register offset.
     569  Calculate the offset of the XHCI capability.
    528570
    529571  @param  Xhc     The XHCI Instance.
     572  @param  CapId   The XHCI Capability ID.
    530573
    531574  @return The offset of XHCI legacy support capability register.
    … …  
    533576**/
    534577UINT32
    535 XhcGetLegSupCapAddr (
    536   IN USB_XHCI_INSTANCE    *Xhc
     578XhcGetCapabilityAddr (
     579  IN USB_XHCI_INSTANCE    *Xhc,
     580  IN UINT8                CapId
    537581  );
    538582

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c

    r48674 r58459  
    33  XHCI transfer scheduling routines.
    44
    5 Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
    66This program and the accompanying materials
    77are licensed and made available under the terms and conditions of the BSD License
    … …  
    110110  }
    111111
    112   FreePool (Urb);
     112  XhcFreeUrb (Xhc, Urb);
    113113
    114114ON_EXIT:
    … …  
    177177  Status = XhcCreateTransferTrb (Xhc, Urb);
    178178  ASSERT_EFI_ERROR (Status);
     179  if (EFI_ERROR (Status)) {
     180    DEBUG ((EFI_D_ERROR, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status));
     181    FreePool (Urb);
     182    Urb = NULL;
     183  }
    179184
    180185  return Urb;
     186}
     187
     188/**
     189  Free an allocated URB.
     190
     191  @param  Xhc                   The XHCI device.
     192  @param  Urb                   The URB to free.
     193
     194**/
     195VOID
     196XhcFreeUrb (
     197  IN USB_XHCI_INSTANCE    *Xhc,
     198  IN URB                  *Urb
     199  )
     200{
     201  if ((Xhc == NULL) || (Urb == NULL)) {
     202    return;
     203  }
     204 
     205  if (Urb->DataMap != NULL) {
     206    Xhc->PciIo->Unmap (Xhc->PciIo, Urb->DataMap);
     207  }
     208
     209  FreePool (Urb);
    181210}
    182211
    … …  
    205234  UINTN                         Len;
    206235  UINTN                         TrbNum;
     236  EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
     237  EFI_PHYSICAL_ADDRESS          PhyAddr;
     238  VOID                          *Map;
     239  EFI_STATUS                    Status;
    207240
    208241  SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
    … …  
    221254  EPRing    = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
    222255  Urb->Ring = EPRing;
    223   OutputContext = (VOID *)(UINTN)Xhc->DCBAA[SlotId];
     256  OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
    224257  if (Xhc->HcCParams.Data.Csz == 0) {
    225258    EPType  = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
    226259  } else {
    227260    EPType  = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
     261  }
     262 
     263  if (Urb->Data != NULL) {
     264    if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
     265      MapOp = EfiPciIoOperationBusMasterWrite;
     266    } else {
     267      MapOp = EfiPciIoOperationBusMasterRead;
     268    }
     269   
     270    Len = Urb->DataLen;
     271    Status  = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
     272   
     273    if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
     274      DEBUG ((EFI_D_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
     275      return EFI_OUT_OF_RESOURCES;
     276    }
     277   
     278    Urb->DataPhy  = (VOID *) ((UINTN) PhyAddr);
     279    Urb->DataMap  = Map;
    228280  }
    229281
    … …  
    268320        XhcSyncTrsRing (Xhc, EPRing);
    269321        TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
    270         TrbStart->TrbCtrData.TRBPtrLo  = XHC_LOW_32BIT(Urb->Data);
    271         TrbStart->TrbCtrData.TRBPtrHi  = XHC_HIGH_32BIT(Urb->Data);
     322        TrbStart->TrbCtrData.TRBPtrLo  = XHC_LOW_32BIT(Urb->DataPhy);
     323        TrbStart->TrbCtrData.TRBPtrHi  = XHC_HIGH_32BIT(Urb->DataPhy);
    272324        TrbStart->TrbCtrData.Lenth     = (UINT32) Urb->DataLen;
    273325        TrbStart->TrbCtrData.TDSize    = 0;
    … …  
    334386        }
    335387        TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
    336         TrbStart->TrbNormal.TRBPtrLo  = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen);
    337         TrbStart->TrbNormal.TRBPtrHi  = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen);
     388        TrbStart->TrbNormal.TRBPtrLo  = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
     389        TrbStart->TrbNormal.TRBPtrHi  = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
    338390        TrbStart->TrbNormal.Lenth     = (UINT32) Len;
    339391        TrbStart->TrbNormal.TDSize    = 0;
    … …  
    369421        }
    370422        TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
    371         TrbStart->TrbNormal.TRBPtrLo  = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen);
    372         TrbStart->TrbNormal.TRBPtrHi  = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen);
     423        TrbStart->TrbNormal.TRBPtrLo  = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
     424        TrbStart->TrbNormal.TRBPtrHi  = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
    373425        TrbStart->TrbNormal.Lenth     = (UINT32) Len;
    374426        TrbStart->TrbNormal.TDSize    = 0;
    … …  
    413465{
    414466  VOID                  *Dcbaa;
     467  EFI_PHYSICAL_ADDRESS  DcbaaPhy;
    415468  UINT64                CmdRing;
     469  EFI_PHYSICAL_ADDRESS  CmdRingPhy;
    416470  UINTN                 Entries;
    417471  UINT32                MaxScratchpadBufs;
    418472  UINT64                *ScratchBuf;
    419   UINT64                *ScratchEntryBuf;
     473  EFI_PHYSICAL_ADDRESS  ScratchPhy;
     474  UINT64                *ScratchEntry;
     475  EFI_PHYSICAL_ADDRESS  ScratchEntryPhy;
    420476  UINT32                Index;
     477  UINTN                 *ScratchEntryMap;
     478  EFI_STATUS            Status;
     479
     480  //
     481  // Initialize memory management.
     482  //
     483  Xhc->MemPool = UsbHcInitMemPool (Xhc->PciIo);
     484  ASSERT (Xhc->MemPool != NULL);
    421485
    422486  //
    … …  
    435499  //
    436500  Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);
    437   Dcbaa   = AllocatePages (EFI_SIZE_TO_PAGES (Entries));
     501  Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries);
    438502  ASSERT (Dcbaa != NULL);
    439503  ZeroMem (Dcbaa, Entries);
    … …  
    448512  ASSERT (MaxScratchpadBufs <= 1023);
    449513  if (MaxScratchpadBufs != 0) {
    450     ScratchBuf = AllocateAlignedPages (EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)), Xhc->PageSize);
    451     ASSERT (ScratchBuf != NULL);
     514    //
     515    // Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them
     516    //
     517    ScratchEntryMap = AllocateZeroPool (sizeof (UINTN) * MaxScratchpadBufs);
     518    ASSERT (ScratchEntryMap != NULL);
     519    Xhc->ScratchEntryMap = ScratchEntryMap;
     520   
     521    //
     522    // Allocate the buffer to record the host address for each entry
     523    //
     524    ScratchEntry = AllocateZeroPool (sizeof (UINT64) * MaxScratchpadBufs);
     525    ASSERT (ScratchEntry != NULL);
     526    Xhc->ScratchEntry = ScratchEntry;
     527
     528    ScratchPhy = 0;
     529    Status = UsbHcAllocateAlignedPages (
     530               Xhc->PciIo,
     531               EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
     532               Xhc->PageSize,
     533               (VOID **) &ScratchBuf,
     534               &ScratchPhy,
     535               &Xhc->ScratchMap
     536               );
     537    ASSERT_EFI_ERROR (Status);
     538
    452539    ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));
    453540    Xhc->ScratchBuf = ScratchBuf;
    454541
     542    //
     543    // Allocate each scratch buffer
     544    //
    455545    for (Index = 0; Index < MaxScratchpadBufs; Index++) {
    456       ScratchEntryBuf = AllocateAlignedPages (EFI_SIZE_TO_PAGES (Xhc->PageSize), Xhc->PageSize);
    457       ASSERT (ScratchEntryBuf != NULL);
    458       ZeroMem (ScratchEntryBuf, Xhc->PageSize);
    459       *ScratchBuf++   = (UINT64)(UINTN)ScratchEntryBuf;
    460     }
    461 
     546      ScratchEntryPhy = 0;
     547      Status = UsbHcAllocateAlignedPages (
     548                 Xhc->PciIo,
     549                 EFI_SIZE_TO_PAGES (Xhc->PageSize),
     550                 Xhc->PageSize,
     551                 (VOID **) &ScratchEntry[Index],
     552                 &ScratchEntryPhy,
     553                 (VOID **) &ScratchEntryMap[Index]
     554                 );
     555      ASSERT_EFI_ERROR (Status);
     556      ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);
     557      //
     558      // Fill with the PCI device address
     559      //
     560      *ScratchBuf++ = ScratchEntryPhy;
     561    }
    462562    //
    463563    // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
    464564    // Device Context Base Address Array points to the Scratchpad Buffer Array.
    465565    //
    466     *(UINT64 *)Dcbaa = (UINT64)(UINTN)Xhc->ScratchBuf;
     566    *(UINT64 *)Dcbaa = (UINT64)(UINTN) ScratchPhy;
    467567  }
    468568
    … …  
    476576  // So divide it to two 32-bytes width register access.
    477577  //
    478   XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(Xhc->DCBAA));
    479   XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (Xhc->DCBAA));
     578  DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries);
     579  XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(DcbaaPhy));
     580  XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
     581
    480582  DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
    481583
    … …  
    493595  //
    494596  CmdRing  = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
    495   ASSERT ((CmdRing & 0x3F) == 0);
    496   CmdRing |= XHC_CRCR_RCS;
     597  CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN) CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
     598  ASSERT ((CmdRingPhy & 0x3F) == 0);
     599  CmdRingPhy |= XHC_CRCR_RCS;
    497600  //
    498601  // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
    499602  // So divide it to two 32-bytes width register access.
    500603  //
    501   XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRing));
    502   XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRing));
     604  XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRingPhy));
     605  XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));
    503606
    504607  DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0));
    … …  
    548651  UINT8                       Dci;
    549652  UINT8                       SlotId;
     653  EFI_PHYSICAL_ADDRESS        PhyAddr;
    550654
    551655  Status = EFI_SUCCESS;
    … …  
    573677             (TRB_TEMPLATE **) (UINTN) &EvtTrb
    574678             );
    575   ASSERT (!EFI_ERROR(Status));
     679  if (EFI_ERROR(Status)) {
     680    DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
     681    goto Done;
     682  }
    576683
    577684  //
    … …  
    579686  //
    580687  ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
    581   CmdSetTRDeq.PtrLo    = XHC_LOW_32BIT (Urb->Ring->RingEnqueue) | Urb->Ring->RingPCS;
    582   CmdSetTRDeq.PtrHi    = XHC_HIGH_32BIT (Urb->Ring->RingEnqueue);
     688  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
     689  CmdSetTRDeq.PtrLo    = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
     690  CmdSetTRDeq.PtrHi    = XHC_HIGH_32BIT (PhyAddr);
    583691  CmdSetTRDeq.CycleBit = 1;
    584692  CmdSetTRDeq.Type     = TRB_TYPE_SET_TR_DEQUE;
    … …  
    591699             (TRB_TEMPLATE **) (UINTN) &EvtTrb
    592700             );
    593   ASSERT (!EFI_ERROR(Status));
     701  if (EFI_ERROR(Status)) {
     702    DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));
     703    goto Done;
     704  }
    594705
    595706  //
    … …  
    598709  XhcRingDoorBell (Xhc, SlotId, Dci);
    599710
     711Done:
    600712  return Status;
    601713}
    … …  
    616728  VOID                        *Buf;
    617729  EVENT_RING_SEG_TABLE_ENTRY  *ERSTBase;
     730  UINTN                       Size;
     731  EFI_PHYSICAL_ADDRESS        ERSTPhy;
     732  EFI_PHYSICAL_ADDRESS        DequeuePhy;
    618733
    619734  ASSERT (EventRing != NULL);
    620735
    621   Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER));
     736  Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;
     737  Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
    622738  ASSERT (Buf != NULL);
    623739  ASSERT (((UINTN) Buf & 0x3F) == 0);
    624   ZeroMem (Buf, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);
     740  ZeroMem (Buf, Size);
    625741
    626742  EventRing->EventRingSeg0    = Buf;
    … …  
    628744  EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
    629745  EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
     746 
     747  DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
     748 
    630749  //
    631750  // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
    … …  
    634753  EventRing->EventRingCCS = 1;
    635754
    636   Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER));
     755  Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;
     756  Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
    637757  ASSERT (Buf != NULL);
    638758  ASSERT (((UINTN) Buf & 0x3F) == 0);
    639   ZeroMem (Buf, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);
     759  ZeroMem (Buf, Size);
    640760
    641761  ERSTBase              = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
    642762  EventRing->ERSTBase   = ERSTBase;
    643   ERSTBase->PtrLo       = XHC_LOW_32BIT (EventRing->EventRingSeg0);
    644   ERSTBase->PtrHi       = XHC_HIGH_32BIT (EventRing->EventRingSeg0);
     763  ERSTBase->PtrLo       = XHC_LOW_32BIT (DequeuePhy);
     764  ERSTBase->PtrHi       = XHC_HIGH_32BIT (DequeuePhy);
    645765  ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;
     766
     767  ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size);
    646768
    647769  //
    … …  
    662784    Xhc,
    663785    XHC_ERDP_OFFSET,
    664     XHC_LOW_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue)
     786    XHC_LOW_32BIT((UINT64)(UINTN)DequeuePhy)
    665787    );
    666788  XhcWriteRuntimeReg (
    667789    Xhc,
    668790    XHC_ERDP_OFFSET + 4,
    669     XHC_HIGH_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue)
     791    XHC_HIGH_32BIT((UINT64)(UINTN)DequeuePhy)
    670792    );
    671793  //
    … …  
    678800    Xhc,
    679801    XHC_ERSTBA_OFFSET,
    680     XHC_LOW_32BIT((UINT64)(UINTN)ERSTBase)
     802    XHC_LOW_32BIT((UINT64)(UINTN)ERSTPhy)
    681803    );
    682804  XhcWriteRuntimeReg (
    683805    Xhc,
    684806    XHC_ERSTBA_OFFSET + 4,
    685     XHC_HIGH_32BIT((UINT64)(UINTN)ERSTBase)
     807    XHC_HIGH_32BIT((UINT64)(UINTN)ERSTPhy)
    686808    );
    687809  //
    … …  
    708830  VOID                  *Buf;
    709831  LINK_TRB              *EndTrb;
    710 
    711   Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TrbNum));
     832  EFI_PHYSICAL_ADDRESS  PhyAddr;
     833
     834  Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);
    712835  ASSERT (Buf != NULL);
    713836  ASSERT (((UINTN) Buf & 0x3F) == 0);
    … …  
    726849  EndTrb        = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
    727850  EndTrb->Type  = TRB_TYPE_LINK;
    728   EndTrb->PtrLo = XHC_LOW_32BIT (Buf);
    729   EndTrb->PtrHi = XHC_HIGH_32BIT (Buf);
     851  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
     852  EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);
     853  EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);
    730854  //
    731855  // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
    … …  
    752876)
    753877{
    754   UINT8                         Index;
    755   EVENT_RING_SEG_TABLE_ENTRY    *TablePtr;
    756   VOID                          *RingBuf;
    757   EVENT_RING_SEG_TABLE_ENTRY    *EventRingPtr;
    758 
    759878  if(EventRing->EventRingSeg0 == NULL) {
    760879    return EFI_SUCCESS;
    … …  
    762881
    763882  //
    764   // Get the Event Ring Segment Table base address
    765   //
    766   TablePtr = (EVENT_RING_SEG_TABLE_ENTRY *)(EventRing->ERSTBase);
    767 
    768   //
    769   // Get all the TRBs Ring and release
    770   //
    771   for (Index = 0; Index < ERST_NUMBER; Index++) {
    772     EventRingPtr = TablePtr + Index;
    773     RingBuf      = (VOID *)(UINTN)(EventRingPtr->PtrLo | LShiftU64 ((UINT64)EventRingPtr->PtrHi, 32));
    774 
    775     if(RingBuf != NULL) {
    776       FreePages (RingBuf, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER));
    777       ZeroMem (EventRingPtr, sizeof (EVENT_RING_SEG_TABLE_ENTRY));
    778     }
    779   }
    780 
    781   FreePages (TablePtr, EFI_SIZE_TO_PAGES (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER));
     883  // Free EventRing Segment 0
     884  //
     885  UsbHcFreeMem (Xhc->MemPool, EventRing->EventRingSeg0, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);
     886
     887  //
     888  // Free ESRT table
     889  //
     890  UsbHcFreeMem (Xhc->MemPool, EventRing->ERSTBase, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);
    782891  return EFI_SUCCESS;
    783892}
    … …  
    794903  )
    795904{
    796   UINT32    Index;
    797   UINT64    *ScratchBuf;
    798 
     905  UINT32                  Index;
     906  UINT64                  *ScratchEntry;
     907 
    799908  if (Xhc->ScratchBuf != NULL) {
    800     ScratchBuf = Xhc->ScratchBuf;
     909    ScratchEntry = Xhc->ScratchEntry;
    801910    for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {
    802       FreeAlignedPages ((VOID*)(UINTN)*ScratchBuf++, EFI_SIZE_TO_PAGES (Xhc->PageSize));
    803     }
    804     FreeAlignedPages (Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)));
    805   }
     911      //
     912      // Free Scratchpad Buffers
     913      //
     914      UsbHcFreeAlignedPages (Xhc->PciIo, (VOID*)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);
     915    }
     916    //
     917    // Free Scratchpad Buffer Array
     918    //
     919    UsbHcFreeAlignedPages (Xhc->PciIo, Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)), Xhc->ScratchMap);
     920    FreePool (Xhc->ScratchEntryMap);
     921    FreePool (Xhc->ScratchEntry);
     922  }
     923
     924  if (Xhc->CmdRing.RingSeg0 != NULL) {
     925    UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
     926    Xhc->CmdRing.RingSeg0 = NULL;
     927  }
     928 
     929  XhcFreeEventRing (Xhc,&Xhc->EventRing);
    806930
    807931  if (Xhc->DCBAA != NULL) {
    808     FreePages (Xhc->DCBAA, EFI_SIZE_TO_PAGES((Xhc->MaxSlotsEn + 1) * sizeof(UINT64)));
     932    UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof(UINT64));
    809933    Xhc->DCBAA = NULL;
    810934  }
    811 
    812   if (Xhc->CmdRing.RingSeg0 != NULL){
    813     FreePages (Xhc->CmdRing.RingSeg0, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER));
    814     Xhc->CmdRing.RingSeg0 = NULL;
    815   }
    816 
    817   XhcFreeEventRing (Xhc,&Xhc->EventRing);
     935 
     936  //
     937  // Free memory pool at last
     938  //
     939  if (Xhc->MemPool != NULL) {
     940    UsbHcFreeMemPool (Xhc->MemPool);
     941    Xhc->MemPool = NULL;
     942  }
    818943}
    819944
    … …  
    9191044  UINT32                  High;
    9201045  UINT32                  Low;
     1046  EFI_PHYSICAL_ADDRESS    PhyAddr;
    9211047
    9221048  ASSERT ((Xhc != NULL) && (Urb != NULL));
    … …  
    9561082      continue;
    9571083    }
    958 
    959     TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
     1084   
     1085    //
     1086    // Need convert pci device address to host address
     1087    //
     1088    PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
     1089    TRBPtr = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
    9601090
    9611091    //
    … …  
    9781108        CheckedUrb->Finished = TRUE;
    9791109        DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));
    980         break;
     1110        goto EXIT;
    9811111
    9821112      case TRB_COMPLETION_BABBLE_ERROR:
    … …  
    9841114        CheckedUrb->Finished = TRUE;
    9851115        DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));
    986         break;
     1116        goto EXIT;
    9871117
    9881118      case TRB_COMPLETION_DATA_BUFFER_ERROR:
    … …  
    9901120        CheckedUrb->Finished = TRUE;
    9911121        DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));
    992         break;
     1122        goto EXIT;
    9931123
    9941124      case TRB_COMPLETION_USB_TRANSACTION_ERROR:
    … …  
    9961126        CheckedUrb->Finished = TRUE;
    9971127        DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));
    998         break;
     1128        goto EXIT;
    9991129
    10001130      case TRB_COMPLETION_SHORT_PACKET:
    … …  
    10171147        CheckedUrb->Result  |= EFI_USB_ERR_TIMEOUT;
    10181148        CheckedUrb->Finished = TRUE;
    1019         break;
     1149        goto EXIT;
    10201150    }
    10211151
    … …  
    10491179  XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);
    10501180
    1051   if ((XhcDequeue & (~0x0F)) != ((UINT64)(UINTN)Xhc->EventRing.EventRingDequeue & (~0x0F))) {
     1181  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));
     1182
     1183  if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) {
    10521184    //
    10531185    // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
    10541186    // So divide it to two 32-bytes width register access.
    10551187    //
    1056     XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (Xhc->EventRing.EventRingDequeue) | BIT3);
    1057     XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (Xhc->EventRing.EventRingDequeue));
     1188    XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (PhyAddr) | BIT3);
     1189    XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (PhyAddr));
    10581190  }
    10591191
    … …  
    11021234
    11031235  Status = EFI_SUCCESS;
    1104   Loop   = (Timeout * XHC_1_MILLISECOND / XHC_POLL_DELAY) + 1;
     1236  Loop   = Timeout * XHC_1_MILLISECOND;
    11051237  if (Timeout == 0) {
    11061238    Loop = 0xFFFFFFFF;
    … …  
    11141246      break;
    11151247    }
    1116     gBS->Stall (XHC_POLL_DELAY);
     1248    gBS->Stall (XHC_1_MICROSECOND);
    11171249  }
    11181250
    … …  
    11601292      RemoveEntryList (&Urb->UrbList);
    11611293      FreePool (Urb->Data);
    1162       FreePool (Urb);
     1294      XhcFreeUrb (Xhc, Urb);
    11631295      return EFI_SUCCESS;
    11641296    }
    … …  
    11871319    RemoveEntryList (&Urb->UrbList);
    11881320    FreePool (Urb->Data);
    1189     FreePool (Urb);
     1321    XhcFreeUrb (Xhc, Urb);
    11901322  }
    11911323}
    … …  
    12181350}
    12191351
     1352/**
     1353  Flush data from PCI controller specific address to mapped system
     1354  memory address.
     1355
     1356  @param  Xhc                The XHCI device.
     1357  @param  Urb                The URB to unmap.
     1358
     1359  @retval EFI_SUCCESS        Success to flush data to mapped system memory.
     1360  @retval EFI_DEVICE_ERROR   Fail to flush data to mapped system memory.
     1361
     1362**/
     1363EFI_STATUS
     1364XhcFlushAsyncIntMap (
     1365  IN  USB_XHCI_INSTANCE   *Xhc,
     1366  IN  URB                 *Urb
     1367  )
     1368{
     1369  EFI_STATUS                    Status;
     1370  EFI_PHYSICAL_ADDRESS          PhyAddr;
     1371  EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
     1372  EFI_PCI_IO_PROTOCOL           *PciIo;
     1373  UINTN                         Len;
     1374  VOID                          *Map;
     1375
     1376  PciIo = Xhc->PciIo;
     1377  Len   = Urb->DataLen;
     1378
     1379  if (Urb->Ep.Direction == EfiUsbDataIn) {
     1380    MapOp = EfiPciIoOperationBusMasterWrite;
     1381  } else {
     1382    MapOp = EfiPciIoOperationBusMasterRead;
     1383  }
     1384
     1385  if (Urb->DataMap != NULL) {
     1386    Status = PciIo->Unmap (PciIo, Urb->DataMap);
     1387    if (EFI_ERROR (Status)) {
     1388      goto ON_ERROR;
     1389    }
     1390  }
     1391
     1392  Urb->DataMap = NULL;
     1393
     1394  Status = PciIo->Map (PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
     1395  if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
     1396    goto ON_ERROR;
     1397  }
     1398
     1399  Urb->DataPhy  = (VOID *) ((UINTN) PhyAddr);
     1400  Urb->DataMap  = Map;
     1401  return EFI_SUCCESS;
     1402
     1403ON_ERROR:
     1404  return EFI_DEVICE_ERROR;
     1405}
    12201406
    12211407/**
    … …  
    12611447    // active, check the next one.
    12621448    //
    1263     Status = XhcCheckUrbResult (Xhc, Urb);
     1449    XhcCheckUrbResult (Xhc, Urb);
    12641450
    12651451    if (!Urb->Finished) {
    12661452      continue;
     1453    }
     1454
     1455    //
     1456    // Flush any PCI posted write transactions from a PCI host
     1457    // bridge to system memory.
     1458    //
     1459    Status = XhcFlushAsyncIntMap (Xhc, Urb);
     1460    if (EFI_ERROR (Status)) {
     1461      DEBUG ((EFI_D_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
    12671462    }
    12681463
    … …  
    13421537
    13431538  Status = EFI_SUCCESS;
     1539
     1540  if ((PortState->PortChangeStatus & (USB_PORT_STAT_C_CONNECTION | USB_PORT_STAT_C_ENABLE | USB_PORT_STAT_C_OVERCURRENT | USB_PORT_STAT_C_RESET)) == 0) {
     1541    return EFI_SUCCESS;
     1542  }
    13441543
    13451544  if (ParentRouteChart.Dword == 0) {
    … …  
    13571556  }
    13581557
     1558  SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
     1559  if (SlotId != 0) {
     1560    if (Xhc->HcCParams.Data.Csz == 0) {
     1561      Status = XhcDisableSlotCmd (Xhc, SlotId);
     1562    } else {
     1563      Status = XhcDisableSlotCmd64 (Xhc, SlotId);
     1564    }
     1565  }
     1566
    13591567  if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&
    13601568      ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {
    … …  
    13741582    //
    13751583    SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
    1376     if (SlotId == 0) {
     1584    if ((SlotId == 0) && ((PortState->PortChangeStatus & USB_PORT_STAT_C_RESET) != 0)) {
    13771585      if (Xhc->HcCParams.Data.Csz == 0) {
    13781586        Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);
    … …  
    13801588        Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);
    13811589      }
    1382       ASSERT_EFI_ERROR (Status);
    1383     }
    1384   } else if ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) == 0) {
    1385     //
    1386     // Device is detached. Disable the allocated device slot and release resource.
    1387     //
    1388     SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
    1389     if (SlotId != 0) {
    1390       if (Xhc->HcCParams.Data.Csz == 0) {
    1391         Status = XhcDisableSlotCmd (Xhc, SlotId);
    1392       } else {
    1393         Status = XhcDisableSlotCmd64 (Xhc, SlotId);
    1394       }
    1395       ASSERT_EFI_ERROR (Status);
    1396     }
    1397   }
     1590    }
     1591  }
     1592
    13981593  return Status;
    13991594}
    … …  
    15841779      //
    15851780      TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
    1586       TrsTrb           = (TRB_TEMPLATE *)(UINTN)((TrsTrb->Parameter1 | LShiftU64 ((UINT64)TrsTrb->Parameter2, 32)) & ~0x0F);
     1781      TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0;  // Use host address
    15871782    }
    15881783  }
    … …  
    16261821  )
    16271822{
    1628   EFI_STATUS          Status;
    1629   TRB_TEMPLATE        *EvtTrb;
    1630 
    16311823  ASSERT (EvtRing != NULL);
    16321824
    1633   EvtTrb     = EvtRing->EventRingDequeue;
    16341825  *NewEvtTrb = EvtRing->EventRingDequeue;
    16351826
    … …  
    16381829  }
    16391830
    1640   Status = EFI_SUCCESS;
    1641 
    16421831  EvtRing->EventRingDequeue++;
    16431832  //
    … …  
    16481837  }
    16491838
    1650   return Status;
     1839  return EFI_SUCCESS;
    16511840}
    16521841
    … …  
    17351924  UINT8                       ParentSlotId;
    17361925  DEVICE_CONTEXT              *ParentDeviceContext;
     1926  EFI_PHYSICAL_ADDRESS        PhyAddr;
    17371927
    17381928  ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
    … …  
    17461936              (TRB_TEMPLATE **) (UINTN) &EvtTrb
    17471937              );
    1748   ASSERT_EFI_ERROR (Status);
     1938  if (EFI_ERROR (Status)) {
     1939    DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
     1940    return Status;
     1941  }
    17491942  ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
    17501943  DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
    … …  
    17621955  // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
    17631956  //
    1764   InputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT)));
     1957  InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));
    17651958  ASSERT (InputContext != NULL);
    17661959  ASSERT (((UINTN) InputContext & 0x3F) == 0);
    … …  
    18512044  // Init the DCS(dequeue cycle state) as the transfer ring's CCS
    18522045  //
    1853   InputContext->EP[0].PtrLo = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0) | BIT0;
    1854   InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0);
     2046  PhyAddr = UsbHcGetPciAddrForHostAddr (
     2047              Xhc->MemPool,
     2048              ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
     2049              sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
     2050              );
     2051  InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
     2052  InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
    18552053
    18562054  //
    18572055  // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
    18582056  //
    1859   OutputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT)));
     2057  OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));
    18602058  ASSERT (OutputContext != NULL);
    18612059  ASSERT (((UINTN) OutputContext & 0x3F) == 0);
    … …  
    18672065  //    a pointer to the Output Device Context data structure (6.2.1).
    18682066  //
    1869   Xhc->DCBAA[SlotId] = (UINT64) (UINTN) OutputContext;
     2067  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT));
     2068  //
     2069  // Fill DCBAA with PCI device address
     2070  //
     2071  Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
    18702072
    18712073  //
    … …  
    18742076  //
    18752077  ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
    1876   CmdTrbAddr.PtrLo    = XHC_LOW_32BIT (Xhc->UsbDevContext[SlotId].InputContext);
    1877   CmdTrbAddr.PtrHi    = XHC_HIGH_32BIT (Xhc->UsbDevContext[SlotId].InputContext);
     2078  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
     2079  CmdTrbAddr.PtrLo    = XHC_LOW_32BIT (PhyAddr);
     2080  CmdTrbAddr.PtrHi    = XHC_HIGH_32BIT (PhyAddr);
    18782081  CmdTrbAddr.CycleBit = 1;
    18792082  CmdTrbAddr.Type     = TRB_TYPE_ADDRESS_DEV;
    … …  
    18852088             (TRB_TEMPLATE **) (UINTN) &EvtTrb
    18862089             );
    1887   ASSERT (!EFI_ERROR(Status));
    1888 
    1889   DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;
    1890   DEBUG ((EFI_D_INFO, "    Address %d assigned successfully\n", DeviceAddress));
    1891 
    1892   Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
     2090  if (!EFI_ERROR (Status)) {
     2091    DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;
     2092    DEBUG ((EFI_D_INFO, "    Address %d assigned successfully\n", DeviceAddress));
     2093    Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
     2094  }
    18932095
    18942096  return Status;
    … …  
    19282130  UINT8                       ParentSlotId;
    19292131  DEVICE_CONTEXT_64           *ParentDeviceContext;
     2132  EFI_PHYSICAL_ADDRESS        PhyAddr;
    19302133
    19312134  ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
    … …  
    19392142              (TRB_TEMPLATE **) (UINTN) &EvtTrb
    19402143              );
    1941   ASSERT_EFI_ERROR (Status);
     2144  if (EFI_ERROR (Status)) {
     2145    DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
     2146    return Status;
     2147  }
    19422148  ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
    19432149  DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
    … …  
    19552161  // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
    19562162  //
    1957   InputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT_64)));
     2163  InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));
    19582164  ASSERT (InputContext != NULL);
    19592165  ASSERT (((UINTN) InputContext & 0x3F) == 0);
    … …  
    20442250  // Init the DCS(dequeue cycle state) as the transfer ring's CCS
    20452251  //
    2046   InputContext->EP[0].PtrLo = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0) | BIT0;
    2047   InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0);
     2252  PhyAddr = UsbHcGetPciAddrForHostAddr (
     2253              Xhc->MemPool,
     2254              ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
     2255              sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
     2256              );
     2257  InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
     2258  InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
    20482259
    20492260  //
    20502261  // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
    20512262  //
    2052   OutputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT_64)));
     2263  OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));
    20532264  ASSERT (OutputContext != NULL);
    20542265  ASSERT (((UINTN) OutputContext & 0x3F) == 0);
    … …  
    20602271  //    a pointer to the Output Device Context data structure (6.2.1).
    20612272  //
    2062   Xhc->DCBAA[SlotId] = (UINT64) (UINTN) OutputContext;
     2273  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64));
     2274  //
     2275  // Fill DCBAA with PCI device address
     2276  //
     2277  Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
    20632278
    20642279  //
    … …  
    20672282  //
    20682283  ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
    2069   CmdTrbAddr.PtrLo    = XHC_LOW_32BIT (Xhc->UsbDevContext[SlotId].InputContext);
    2070   CmdTrbAddr.PtrHi    = XHC_HIGH_32BIT (Xhc->UsbDevContext[SlotId].InputContext);
     2284  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
     2285  CmdTrbAddr.PtrLo    = XHC_LOW_32BIT (PhyAddr);
     2286  CmdTrbAddr.PtrHi    = XHC_HIGH_32BIT (PhyAddr);
    20712287  CmdTrbAddr.CycleBit = 1;
    20722288  CmdTrbAddr.Type     = TRB_TYPE_ADDRESS_DEV;
    … …  
    20782294             (TRB_TEMPLATE **) (UINTN) &EvtTrb
    20792295             );
    2080   ASSERT (!EFI_ERROR(Status));
    2081 
    2082   DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;
    2083   DEBUG ((EFI_D_INFO, "    Address %d assigned successfully\n", DeviceAddress));
    2084 
    2085   Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
    2086 
     2296  if (!EFI_ERROR (Status)) {
     2297    DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;
     2298    DEBUG ((EFI_D_INFO, "    Address %d assigned successfully\n", DeviceAddress));
     2299    Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
     2300  }
    20872301  return Status;
    20882302}
    … …  
    21452359             (TRB_TEMPLATE **) (UINTN) &EvtTrb
    21462360             );
    2147   ASSERT_EFI_ERROR(Status);
     2361  if (EFI_ERROR (Status)) {
     2362    DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
     2363    return Status;
     2364  }
    21482365  //
    21492366  // Free the slot's device context entry
    … …  
    21582375      RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
    21592376      if (RingSeg != NULL) {
    2160         FreePages (RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER));
     2377        UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
    21612378      }
    21622379      FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
     2380      Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
    21632381    }
    21642382  }
    … …  
    21702388  }
    21712389
     2390  if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {
     2391    FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);
     2392  }
     2393
    21722394  if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
    2173     FreePages (Xhc->UsbDevContext[SlotId].InputContext, EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT)));
     2395    UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
    21742396  }
    21752397
    21762398  if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
    2177     FreePages (Xhc->UsbDevContext[SlotId].OutputContext, EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT)));
     2399    UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));
    21782400  }
    21792401  //
    … …  
    22442466             (TRB_TEMPLATE **) (UINTN) &EvtTrb
    22452467             );
    2246   ASSERT_EFI_ERROR(Status);
     2468  if (EFI_ERROR (Status)) {
     2469    DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
     2470    return Status;
     2471  }
    22472472  //
    22482473  // Free the slot's device context entry
    … …  
    22572482      RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
    22582483      if (RingSeg != NULL) {
    2259         FreePages (RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER));
     2484        UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
    22602485      }
    22612486      FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
     2487      Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
    22622488    }
    22632489  }
    … …  
    22692495  }
    22702496
     2497  if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {
     2498    FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);
     2499  }
     2500
    22712501  if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
    2272     FreePages (Xhc->UsbDevContext[SlotId].InputContext, EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT_64)));
     2502    UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
    22732503  }
    22742504
    22752505  if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
    2276     FreePages (Xhc->UsbDevContext[SlotId].OutputContext, EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT_64)));
     2506     UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
    22772507  }
    22782508  //
    … …  
    22872517}
    22882518
     2519/**
     2520  Initialize endpoint context in input context.
     2521
     2522  @param Xhc            The XHCI Instance.
     2523  @param SlotId         The slot id to be configured.
     2524  @param DeviceSpeed    The device's speed.
     2525  @param InputContext   The pointer to the input context.
     2526  @param IfDesc         The pointer to the usb device interface descriptor.
     2527
     2528  @return The maximum device context index of endpoint.
     2529
     2530**/
     2531UINT8
     2532EFIAPI
     2533XhcInitializeEndpointContext (
     2534  IN USB_XHCI_INSTANCE          *Xhc,
     2535  IN UINT8                      SlotId,
     2536  IN UINT8                      DeviceSpeed,
     2537  IN INPUT_CONTEXT              *InputContext,
     2538  IN USB_INTERFACE_DESCRIPTOR   *IfDesc
     2539  )
     2540{
     2541  USB_ENDPOINT_DESCRIPTOR       *EpDesc;
     2542  UINTN                         NumEp;
     2543  UINTN                         EpIndex;
     2544  UINT8                         EpAddr;
     2545  UINT8                         Direction;
     2546  UINT8                         Dci;
     2547  UINT8                         MaxDci;
     2548  EFI_PHYSICAL_ADDRESS          PhyAddr;
     2549  UINT8                         Interval;
     2550  TRANSFER_RING                 *EndpointTransferRing;
     2551
     2552  MaxDci = 0;
     2553
     2554  NumEp = IfDesc->NumEndpoints;
     2555
     2556  EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
     2557  for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
     2558    while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
     2559      EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
     2560    }
     2561
     2562    EpAddr    = (UINT8)(EpDesc->EndpointAddress & 0x0F);
     2563    Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
     2564
     2565    Dci = XhcEndpointToDci (EpAddr, Direction);
     2566    ASSERT (Dci < 32);
     2567    if (Dci > MaxDci) {
     2568      MaxDci = Dci;
     2569    }
     2570
     2571    InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
     2572    InputContext->EP[Dci-1].MaxPacketSize     = EpDesc->MaxPacketSize;
     2573
     2574    if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
     2575      //
     2576      // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
     2577      //
     2578      InputContext->EP[Dci-1].MaxBurstSize = 0x0;
     2579    } else {
     2580      InputContext->EP[Dci-1].MaxBurstSize = 0x0;
     2581    }
     2582
     2583    switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
     2584      case USB_ENDPOINT_BULK:
     2585        if (Direction == EfiUsbDataIn) {
     2586          InputContext->EP[Dci-1].CErr   = 3;
     2587          InputContext->EP[Dci-1].EPType = ED_BULK_IN;
     2588        } else {
     2589          InputContext->EP[Dci-1].CErr   = 3;
     2590          InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
     2591        }
     2592
     2593        InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
     2594        if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
     2595          EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
     2596          Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
     2597          CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
     2598        }
     2599
     2600        break;
     2601      case USB_ENDPOINT_ISO:
     2602        if (Direction == EfiUsbDataIn) {
     2603          InputContext->EP[Dci-1].CErr   = 0;
     2604          InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
     2605        } else {
     2606          InputContext->EP[Dci-1].CErr   = 0;
     2607          InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
     2608        }
     2609        //
     2610        // Do not support isochronous transfer now.
     2611        //
     2612        DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
     2613        EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
     2614        continue;
     2615      case USB_ENDPOINT_INTERRUPT:
     2616        if (Direction == EfiUsbDataIn) {
     2617          InputContext->EP[Dci-1].CErr   = 3;
     2618          InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
     2619        } else {
     2620          InputContext->EP[Dci-1].CErr   = 3;
     2621          InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
     2622        }
     2623        InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
     2624        InputContext->EP[Dci-1].MaxESITPayload   = EpDesc->MaxPacketSize;
     2625        //
     2626        // Get the bInterval from descriptor and init the the interval field of endpoint context
     2627        //
     2628        if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
     2629          Interval = EpDesc->Interval;
     2630          //
     2631          // Calculate through the bInterval field of Endpoint descriptor.
     2632          //
     2633          ASSERT (Interval != 0);
     2634          InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
     2635        } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
     2636          Interval = EpDesc->Interval;
     2637          ASSERT (Interval >= 1 && Interval <= 16);
     2638          //
     2639          // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
     2640          //
     2641          InputContext->EP[Dci-1].Interval         = Interval - 1;
     2642          InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
     2643          InputContext->EP[Dci-1].MaxESITPayload   = 0x0002;
     2644          InputContext->EP[Dci-1].MaxBurstSize     = 0x0;
     2645          InputContext->EP[Dci-1].CErr             = 3;
     2646        }
     2647
     2648        if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
     2649          EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
     2650          Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
     2651          CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
     2652        }
     2653        break;
     2654
     2655      case USB_ENDPOINT_CONTROL:
     2656        //
     2657        // Do not support control transfer now.
     2658        //
     2659        DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
     2660      default:
     2661        DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
     2662        EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
     2663        continue;
     2664    }
     2665
     2666    PhyAddr = UsbHcGetPciAddrForHostAddr (
     2667                Xhc->MemPool,
     2668                ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
     2669                sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
     2670                );
     2671    PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
     2672    PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
     2673    InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
     2674    InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
     2675
     2676    EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
     2677  }
     2678
     2679  return MaxDci;
     2680}
     2681
     2682/**
     2683  Initialize endpoint context in input context.
     2684
     2685  @param Xhc            The XHCI Instance.
     2686  @param SlotId         The slot id to be configured.
     2687  @param DeviceSpeed    The device's speed.
     2688  @param InputContext   The pointer to the input context.
     2689  @param IfDesc         The pointer to the usb device interface descriptor.
     2690
     2691  @return The maximum device context index of endpoint.
     2692
     2693**/
     2694UINT8
     2695EFIAPI
     2696XhcInitializeEndpointContext64 (
     2697  IN USB_XHCI_INSTANCE          *Xhc,
     2698  IN UINT8                      SlotId,
     2699  IN UINT8                      DeviceSpeed,
     2700  IN INPUT_CONTEXT_64           *InputContext,
     2701  IN USB_INTERFACE_DESCRIPTOR   *IfDesc
     2702  )
     2703{
     2704  USB_ENDPOINT_DESCRIPTOR       *EpDesc;
     2705  UINTN                         NumEp;
     2706  UINTN                         EpIndex;
     2707  UINT8                         EpAddr;
     2708  UINT8                         Direction;
     2709  UINT8                         Dci;
     2710  UINT8                         MaxDci;
     2711  EFI_PHYSICAL_ADDRESS          PhyAddr;
     2712  UINT8                         Interval;
     2713  TRANSFER_RING                 *EndpointTransferRing;
     2714
     2715  MaxDci = 0;
     2716
     2717  NumEp = IfDesc->NumEndpoints;
     2718
     2719  EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
     2720  for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
     2721    while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
     2722      EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
     2723    }
     2724
     2725    EpAddr    = (UINT8)(EpDesc->EndpointAddress & 0x0F);
     2726    Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
     2727
     2728    Dci = XhcEndpointToDci (EpAddr, Direction);
     2729    ASSERT (Dci < 32);
     2730    if (Dci > MaxDci) {
     2731      MaxDci = Dci;
     2732    }
     2733
     2734    InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
     2735    InputContext->EP[Dci-1].MaxPacketSize     = EpDesc->MaxPacketSize;
     2736
     2737    if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
     2738      //
     2739      // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
     2740      //
     2741      InputContext->EP[Dci-1].MaxBurstSize = 0x0;
     2742    } else {
     2743      InputContext->EP[Dci-1].MaxBurstSize = 0x0;
     2744    }
     2745
     2746    switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
     2747      case USB_ENDPOINT_BULK:
     2748        if (Direction == EfiUsbDataIn) {
     2749          InputContext->EP[Dci-1].CErr   = 3;
     2750          InputContext->EP[Dci-1].EPType = ED_BULK_IN;
     2751        } else {
     2752          InputContext->EP[Dci-1].CErr   = 3;
     2753          InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
     2754        }
     2755
     2756        InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
     2757        if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
     2758          EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
     2759          Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
     2760          CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
     2761        }
     2762
     2763        break;
     2764      case USB_ENDPOINT_ISO:
     2765        if (Direction == EfiUsbDataIn) {
     2766          InputContext->EP[Dci-1].CErr   = 0;
     2767          InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
     2768        } else {
     2769          InputContext->EP[Dci-1].CErr   = 0;
     2770          InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
     2771        }
     2772        //
     2773        // Do not support isochronous transfer now.
     2774        //
     2775        DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
     2776        EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
     2777        continue;
     2778      case USB_ENDPOINT_INTERRUPT:
     2779        if (Direction == EfiUsbDataIn) {
     2780          InputContext->EP[Dci-1].CErr   = 3;
     2781          InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
     2782        } else {
     2783          InputContext->EP[Dci-1].CErr   = 3;
     2784          InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
     2785        }
     2786        InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
     2787        InputContext->EP[Dci-1].MaxESITPayload   = EpDesc->MaxPacketSize;
     2788        //
     2789        // Get the bInterval from descriptor and init the the interval field of endpoint context
     2790        //
     2791        if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
     2792          Interval = EpDesc->Interval;
     2793          //
     2794          // Calculate through the bInterval field of Endpoint descriptor.
     2795          //
     2796          ASSERT (Interval != 0);
     2797          InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
     2798        } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
     2799          Interval = EpDesc->Interval;
     2800          ASSERT (Interval >= 1 && Interval <= 16);
     2801          //
     2802          // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
     2803          //
     2804          InputContext->EP[Dci-1].Interval         = Interval - 1;
     2805          InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
     2806          InputContext->EP[Dci-1].MaxESITPayload   = 0x0002;
     2807          InputContext->EP[Dci-1].MaxBurstSize     = 0x0;
     2808          InputContext->EP[Dci-1].CErr             = 3;
     2809        }
     2810
     2811        if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
     2812          EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
     2813          Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
     2814          CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
     2815        }
     2816        break;
     2817
     2818      case USB_ENDPOINT_CONTROL:
     2819        //
     2820        // Do not support control transfer now.
     2821        //
     2822        DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
     2823      default:
     2824        DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
     2825        EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
     2826        continue;
     2827    }
     2828
     2829    PhyAddr = UsbHcGetPciAddrForHostAddr (
     2830                Xhc->MemPool,
     2831                ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
     2832                sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
     2833                );
     2834    PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
     2835    PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
     2836    InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
     2837    InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
     2838
     2839    EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
     2840  }
     2841
     2842  return MaxDci;
     2843}
    22892844
    22902845/**
    … …  
    23092864{
    23102865  EFI_STATUS                  Status;
    2311 
    23122866  USB_INTERFACE_DESCRIPTOR    *IfDesc;
    2313   USB_ENDPOINT_DESCRIPTOR     *EpDesc;
    23142867  UINT8                       Index;
    2315   UINTN                       NumEp;
    2316   UINTN                       EpIndex;
    2317   UINT8                       EpAddr;
    2318   UINT8                       Direction;
    23192868  UINT8                       Dci;
    23202869  UINT8                       MaxDci;
    2321   UINT32                      PhyAddr;
    2322   UINT8                       Interval;
    2323 
    2324   TRANSFER_RING               *EndpointTransferRing;
     2870  EFI_PHYSICAL_ADDRESS        PhyAddr;
     2871
    23252872  CMD_TRB_CONFIG_ENDPOINT     CmdTrbCfgEP;
    23262873  INPUT_CONTEXT               *InputContext;
    … …  
    23412888  IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
    23422889  for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
    2343     while (IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) {
     2890    while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
    23442891      IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
    23452892    }
    23462893
    2347     NumEp = IfDesc->NumEndpoints;
    2348 
    2349     EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
    2350     for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
    2351       while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
    2352         EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
    2353       }
    2354 
    2355       EpAddr    = (UINT8)(EpDesc->EndpointAddress & 0x0F);
    2356       Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
    2357 
    2358       Dci = XhcEndpointToDci (EpAddr, Direction);
    2359       ASSERT (Dci < 32);
    2360       if (Dci > MaxDci) {
    2361         MaxDci = Dci;
    2362       }
    2363 
    2364       InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
    2365       InputContext->EP[Dci-1].MaxPacketSize     = EpDesc->MaxPacketSize;
    2366 
    2367       if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
    2368         //
    2369         // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
    2370         //
    2371         InputContext->EP[Dci-1].MaxBurstSize = 0x0;
    2372       } else {
    2373         InputContext->EP[Dci-1].MaxBurstSize = 0x0;
    2374       }
    2375 
    2376       switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
    2377         case USB_ENDPOINT_BULK:
    2378           if (Direction == EfiUsbDataIn) {
    2379             InputContext->EP[Dci-1].CErr   = 3;
    2380             InputContext->EP[Dci-1].EPType = ED_BULK_IN;
    2381           } else {
    2382             InputContext->EP[Dci-1].CErr   = 3;
    2383             InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
    2384           }
    2385 
    2386           InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
    2387           if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
    2388             EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
    2389             Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
    2390             CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
    2391           }
    2392 
    2393           break;
    2394         case USB_ENDPOINT_ISO:
    2395           if (Direction == EfiUsbDataIn) {
    2396             InputContext->EP[Dci-1].CErr   = 0;
    2397             InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
    2398           } else {
    2399             InputContext->EP[Dci-1].CErr   = 0;
    2400             InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
    2401           }
    2402           break;
    2403         case USB_ENDPOINT_INTERRUPT:
    2404           if (Direction == EfiUsbDataIn) {
    2405             InputContext->EP[Dci-1].CErr   = 3;
    2406             InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
    2407           } else {
    2408             InputContext->EP[Dci-1].CErr   = 3;
    2409             InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
    2410           }
    2411           InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
    2412           InputContext->EP[Dci-1].MaxESITPayload   = EpDesc->MaxPacketSize;
    2413           //
    2414           // Get the bInterval from descriptor and init the the interval field of endpoint context
    2415           //
    2416           if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
    2417             Interval = EpDesc->Interval;
    2418             //
    2419             // Hard code the interval to MAX first, need calculate through the bInterval field of Endpoint descriptor.
    2420             //
    2421             InputContext->EP[Dci-1].Interval = 6;
    2422           } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
    2423             Interval = EpDesc->Interval;
    2424             ASSERT (Interval >= 1 && Interval <= 16);
    2425             //
    2426             // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
    2427             //
    2428             InputContext->EP[Dci-1].Interval         = Interval - 1;
    2429             InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
    2430             InputContext->EP[Dci-1].MaxESITPayload   = 0x0002;
    2431             InputContext->EP[Dci-1].MaxBurstSize     = 0x0;
    2432             InputContext->EP[Dci-1].CErr             = 3;
    2433           }
    2434 
    2435           if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
    2436             EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
    2437             Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
    2438             CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
    2439           }
    2440           break;
    2441 
    2442         case USB_ENDPOINT_CONTROL:
    2443         default:
    2444           ASSERT (0);
    2445           break;
    2446       }
    2447 
    2448       PhyAddr  = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);
    2449       PhyAddr &= ~(0x0F);
    2450       PhyAddr |= ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
    2451       InputContext->EP[Dci-1].PtrLo = PhyAddr;
    2452       InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);
    2453 
    2454       EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
    2455     }
     2894    Dci = XhcInitializeEndpointContext (Xhc, SlotId, DeviceSpeed, InputContext, IfDesc);
     2895    if (Dci > MaxDci) {
     2896      MaxDci = Dci;
     2897    }
     2898
    24562899    IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
    24572900  }
    … …  
    24632906  //
    24642907  ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
    2465   CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (InputContext);
    2466   CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (InputContext);
     2908  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
     2909  CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (PhyAddr);
     2910  CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (PhyAddr);
    24672911  CmdTrbCfgEP.CycleBit = 1;
    24682912  CmdTrbCfgEP.Type     = TRB_TYPE_CON_ENDPOINT;
    … …  
    24752919             (TRB_TEMPLATE **) (UINTN) &EvtTrb
    24762920             );
    2477   ASSERT_EFI_ERROR(Status);
     2921  if (EFI_ERROR (Status)) {
     2922    DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
     2923  } else {
     2924    Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
     2925  }
    24782926
    24792927  return Status;
    … …  
    25012949{
    25022950  EFI_STATUS                  Status;
    2503 
    25042951  USB_INTERFACE_DESCRIPTOR    *IfDesc;
    2505   USB_ENDPOINT_DESCRIPTOR     *EpDesc;
    25062952  UINT8                       Index;
    2507   UINTN                       NumEp;
    2508   UINTN                       EpIndex;
    2509   UINT8                       EpAddr;
    2510   UINT8                       Direction;
    25112953  UINT8                       Dci;
    25122954  UINT8                       MaxDci;
    2513   UINT32                      PhyAddr;
    2514   UINT8                       Interval;
    2515 
    2516   TRANSFER_RING               *EndpointTransferRing;
     2955  EFI_PHYSICAL_ADDRESS        PhyAddr;
     2956
    25172957  CMD_TRB_CONFIG_ENDPOINT     CmdTrbCfgEP;
    25182958  INPUT_CONTEXT_64            *InputContext;
    … …  
    25332973  IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
    25342974  for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
    2535     while (IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) {
     2975    while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
    25362976      IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
    25372977    }
    25382978
    2539     NumEp = IfDesc->NumEndpoints;
    2540 
    2541     EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
    2542     for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
    2543       while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
    2544         EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
    2545       }
    2546 
    2547       EpAddr    = (UINT8)(EpDesc->EndpointAddress & 0x0F);
    2548       Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
    2549 
    2550       Dci = XhcEndpointToDci (EpAddr, Direction);
    2551       ASSERT (Dci < 32);
    2552       if (Dci > MaxDci) {
    2553         MaxDci = Dci;
    2554       }
    2555 
    2556       InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
    2557       InputContext->EP[Dci-1].MaxPacketSize     = EpDesc->MaxPacketSize;
    2558 
    2559       if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
    2560         //
    2561         // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
    2562         //
    2563         InputContext->EP[Dci-1].MaxBurstSize = 0x0;
    2564       } else {
    2565         InputContext->EP[Dci-1].MaxBurstSize = 0x0;
    2566       }
    2567 
    2568       switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
    2569         case USB_ENDPOINT_BULK:
    2570           if (Direction == EfiUsbDataIn) {
    2571             InputContext->EP[Dci-1].CErr   = 3;
    2572             InputContext->EP[Dci-1].EPType = ED_BULK_IN;
    2573           } else {
    2574             InputContext->EP[Dci-1].CErr   = 3;
    2575             InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
    2576           }
    2577 
    2578           InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
    2579           if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
    2580             EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
    2581             Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
    2582             CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
    2583           }
    2584 
    2585           break;
    2586         case USB_ENDPOINT_ISO:
    2587           if (Direction == EfiUsbDataIn) {
    2588             InputContext->EP[Dci-1].CErr   = 0;
    2589             InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
    2590           } else {
    2591             InputContext->EP[Dci-1].CErr   = 0;
    2592             InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
    2593           }
    2594           break;
    2595         case USB_ENDPOINT_INTERRUPT:
    2596           if (Direction == EfiUsbDataIn) {
    2597             InputContext->EP[Dci-1].CErr   = 3;
    2598             InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
    2599           } else {
    2600             InputContext->EP[Dci-1].CErr   = 3;
    2601             InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
    2602           }
    2603           InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
    2604           InputContext->EP[Dci-1].MaxESITPayload   = EpDesc->MaxPacketSize;
    2605           //
    2606           // Get the bInterval from descriptor and init the the interval field of endpoint context
    2607           //
    2608           if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
    2609             Interval = EpDesc->Interval;
    2610             //
    2611             // Hard code the interval to MAX first, need calculate through the bInterval field of Endpoint descriptor.
    2612             //
    2613             InputContext->EP[Dci-1].Interval = 6;
    2614           } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
    2615             Interval = EpDesc->Interval;
    2616             ASSERT (Interval >= 1 && Interval <= 16);
    2617             //
    2618             // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
    2619             //
    2620             InputContext->EP[Dci-1].Interval         = Interval - 1;
    2621             InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
    2622             InputContext->EP[Dci-1].MaxESITPayload   = 0x0002;
    2623             InputContext->EP[Dci-1].MaxBurstSize     = 0x0;
    2624             InputContext->EP[Dci-1].CErr             = 3;
    2625           }
    2626 
    2627           if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
    2628             EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
    2629             Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
    2630             CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
    2631           }
    2632           break;
    2633 
    2634         case USB_ENDPOINT_CONTROL:
    2635         default:
    2636           ASSERT (0);
    2637           break;
    2638       }
    2639 
    2640       PhyAddr  = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);
    2641       PhyAddr &= ~(0x0F);
    2642       PhyAddr |= ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
    2643       InputContext->EP[Dci-1].PtrLo = PhyAddr;
    2644       InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);
    2645 
    2646       EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
    2647     }
     2979    Dci = XhcInitializeEndpointContext64 (Xhc, SlotId, DeviceSpeed, InputContext, IfDesc);
     2980    if (Dci > MaxDci) {
     2981      MaxDci = Dci;
     2982    }
     2983 
    26482984    IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
    26492985  }
    … …  
    26552991  //
    26562992  ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
    2657   CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (InputContext);
    2658   CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (InputContext);
     2993  PhyAddr  = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
     2994  CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (PhyAddr);
     2995  CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (PhyAddr);
    26592996  CmdTrbCfgEP.CycleBit = 1;
    26602997  CmdTrbCfgEP.Type     = TRB_TYPE_CON_ENDPOINT;
    … …  
    26673004             (TRB_TEMPLATE **) (UINTN) &EvtTrb
    26683005             );
    2669   ASSERT_EFI_ERROR(Status);
     3006  if (EFI_ERROR (Status)) {
     3007    DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
     3008  } else {
     3009    Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
     3010  }
    26703011
    26713012  return Status;
    26723013}
    26733014
     3015/**
     3016  Stop endpoint through XHCI's Stop_Endpoint cmd.
     3017
     3018  @param  Xhc                   The XHCI Instance.
     3019  @param  SlotId                The slot id to be configured.
     3020  @param  Dci                   The device context index of endpoint.
     3021
     3022  @retval EFI_SUCCESS           Stop endpoint successfully.
     3023  @retval Others                Failed to stop endpoint.
     3024
     3025**/
     3026EFI_STATUS
     3027EFIAPI
     3028XhcStopEndpoint (
     3029  IN USB_XHCI_INSTANCE      *Xhc,
     3030  IN UINT8                  SlotId,
     3031  IN UINT8                  Dci
     3032  )
     3033{
     3034  EFI_STATUS                    Status;
     3035  EVT_TRB_COMMAND_COMPLETION    *EvtTrb;
     3036  CMD_TRB_STOP_ENDPOINT         CmdTrbStopED;
     3037
     3038  DEBUG ((EFI_D_INFO, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
     3039
     3040  //
     3041  // Send stop endpoint command to transit Endpoint from running to stop state
     3042  //
     3043  ZeroMem (&CmdTrbStopED, sizeof (CmdTrbStopED));
     3044  CmdTrbStopED.CycleBit = 1;
     3045  CmdTrbStopED.Type     = TRB_TYPE_STOP_ENDPOINT;
     3046  CmdTrbStopED.EDID     = Dci;
     3047  CmdTrbStopED.SlotId   = SlotId;
     3048  Status = XhcCmdTransfer (
     3049             Xhc,
     3050             (TRB_TEMPLATE *) (UINTN) &CmdTrbStopED,
     3051             XHC_GENERIC_TIMEOUT,
     3052             (TRB_TEMPLATE **) (UINTN) &EvtTrb
     3053             );
     3054  if (EFI_ERROR(Status)) {
     3055    DEBUG ((EFI_D_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
     3056  }
     3057
     3058  return Status;
     3059}
     3060
     3061/**
     3062  Set interface through XHCI's Configure_Endpoint cmd.
     3063
     3064  @param  Xhc           The XHCI Instance.
     3065  @param  SlotId        The slot id to be configured.
     3066  @param  DeviceSpeed   The device's speed.
     3067  @param  ConfigDesc    The pointer to the usb device configuration descriptor.
     3068  @param  Request       USB device request to send.
     3069
     3070  @retval EFI_SUCCESS   Successfully set interface.
     3071
     3072**/
     3073EFI_STATUS
     3074EFIAPI
     3075XhcSetInterface (
     3076  IN USB_XHCI_INSTANCE        *Xhc,
     3077  IN UINT8                    SlotId,
     3078  IN UINT8                    DeviceSpeed,
     3079  IN USB_CONFIG_DESCRIPTOR    *ConfigDesc,
     3080  IN EFI_USB_DEVICE_REQUEST   *Request
     3081  )
     3082{
     3083  EFI_STATUS                  Status;
     3084  USB_INTERFACE_DESCRIPTOR    *IfDescActive;
     3085  USB_INTERFACE_DESCRIPTOR    *IfDescSet;
     3086  USB_INTERFACE_DESCRIPTOR    *IfDesc;
     3087  USB_ENDPOINT_DESCRIPTOR     *EpDesc;
     3088  UINTN                       NumEp;
     3089  UINTN                       EpIndex;
     3090  UINT8                       EpAddr;
     3091  UINT8                       Direction;
     3092  UINT8                       Dci;
     3093  UINT8                       MaxDci;
     3094  EFI_PHYSICAL_ADDRESS        PhyAddr;
     3095  VOID                        *RingSeg;
     3096
     3097  CMD_TRB_CONFIG_ENDPOINT     CmdTrbCfgEP;
     3098  INPUT_CONTEXT               *InputContext;
     3099  DEVICE_CONTEXT              *OutputContext;
     3100  EVT_TRB_COMMAND_COMPLETION  *EvtTrb;
     3101
     3102  Status = EFI_SUCCESS;
     3103
     3104  InputContext  = Xhc->UsbDevContext[SlotId].InputContext;
     3105  OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
     3106  //
     3107  // XHCI 4.6.6 Configure Endpoint
     3108  // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
     3109  // Context and Add Context flags as follows:
     3110  // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop
     3111  // Context and Add Context flags to '0'.
     3112  //
     3113  // Except the interface indicated by Reqeust->Index, no impact to other interfaces.
     3114  // So the default Drop Context and Add Context flags can be '0' to cover 1).
     3115  //
     3116  ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
     3117  CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));
     3118
     3119  ASSERT (ConfigDesc != NULL);
     3120
     3121  MaxDci = 0;
     3122
     3123  IfDescActive = NULL;
     3124  IfDescSet = NULL;
     3125
     3126  IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
     3127  while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {
     3128    if (IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) {
     3129      if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {
     3130        if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {
     3131          //
     3132          // Find out the active interface descriptor.
     3133          //
     3134          IfDescActive = IfDesc;
     3135        } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {
     3136          //
     3137          // Find out the interface descriptor to set.
     3138          //
     3139          IfDescSet = IfDesc;
     3140        }
     3141      }
     3142    }
     3143    IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
     3144  }
     3145
     3146  //
     3147  // XHCI 4.6.6 Configure Endpoint
     3148  // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
     3149  // Context and Add Context flags as follows:
     3150  // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set
     3151  // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.
     3152  // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set
     3153  // the Drop Context flag to '1' and Add Context flag to '0'.
     3154  // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context
     3155  // and Add Context flags shall be set to '1'.
     3156  //
     3157  // Below codes are to cover 2), 3) and 4).
     3158  //
     3159
     3160  if ((IfDescActive != NULL) && (IfDescSet != NULL)) {
     3161    NumEp = IfDescActive->NumEndpoints;
     3162    EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);
     3163    for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
     3164      while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
     3165        EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
     3166      }
     3167
     3168      EpAddr    = (UINT8) (EpDesc->EndpointAddress & 0x0F);
     3169      Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
     3170
     3171      Dci = XhcEndpointToDci (EpAddr, Direction);
     3172      ASSERT (Dci < 32);
     3173      if (Dci > MaxDci) {
     3174        MaxDci = Dci;
     3175      }
     3176      //
     3177      // XHCI 4.3.6 - Setting Alternate Interfaces
     3178      // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
     3179      //
     3180      Status = XhcStopEndpoint (Xhc, SlotId, Dci);
     3181      if (EFI_ERROR (Status)) {
     3182        return Status;
     3183      }
     3184      //
     3185      // XHCI 4.3.6 - Setting Alternate Interfaces
     3186      // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
     3187      //
     3188      if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] != NULL) {
     3189        RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingSeg0;
     3190        if (RingSeg != NULL) {
     3191          UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
     3192        }
     3193        FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
     3194        Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;
     3195      }
     3196
     3197      //
     3198      // Set the Drop Context flag to '1'.
     3199      //
     3200      InputContext->InputControlContext.Dword1 |= (BIT0 << Dci);
     3201
     3202      EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
     3203    }
     3204
     3205    //
     3206    // XHCI 4.3.6 - Setting Alternate Interfaces
     3207    // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate
     3208    // Interface setting, to '0'.
     3209    //
     3210    // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.
     3211    //
     3212
     3213    //
     3214    // XHCI 4.3.6 - Setting Alternate Interfaces
     3215    // 4) For each endpoint enabled by the Configure Endpoint Command:
     3216    //   a. Allocate a Transfer Ring.
     3217    //   b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.
     3218    //   c. Initialize the Endpoint Context data structure.
     3219    //
     3220    Dci = XhcInitializeEndpointContext (Xhc, SlotId, DeviceSpeed, InputContext, IfDescSet);
     3221    if (Dci > MaxDci) {
     3222      MaxDci = Dci;
     3223    }
     3224
     3225    InputContext->InputControlContext.Dword2 |= BIT0;
     3226    InputContext->Slot.ContextEntries         = MaxDci;
     3227    //
     3228    // XHCI 4.3.6 - Setting Alternate Interfaces
     3229    // 5) Issue and successfully complete a Configure Endpoint Command.
     3230    //
     3231    ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
     3232    PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
     3233    CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (PhyAddr);
     3234    CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (PhyAddr);
     3235    CmdTrbCfgEP.CycleBit = 1;
     3236    CmdTrbCfgEP.Type     = TRB_TYPE_CON_ENDPOINT;
     3237    CmdTrbCfgEP.SlotId   = Xhc->UsbDevContext[SlotId].SlotId;
     3238    DEBUG ((EFI_D_INFO, "SetInterface: Configure Endpoint\n"));
     3239    Status = XhcCmdTransfer (
     3240               Xhc,
     3241               (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
     3242               XHC_GENERIC_TIMEOUT,
     3243               (TRB_TEMPLATE **) (UINTN) &EvtTrb
     3244               );
     3245    if (EFI_ERROR (Status)) {
     3246      DEBUG ((EFI_D_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));
     3247    } else {
     3248      //
     3249      // Update the active AlternateSetting.
     3250      //
     3251      Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;
     3252    }
     3253  }
     3254
     3255  return Status;
     3256}
     3257
     3258/**
     3259  Set interface through XHCI's Configure_Endpoint cmd.
     3260
     3261  @param  Xhc           The XHCI Instance.
     3262  @param  SlotId        The slot id to be configured.
     3263  @param  DeviceSpeed   The device's speed.
     3264  @param  ConfigDesc    The pointer to the usb device configuration descriptor.
     3265  @param  Request       USB device request to send.
     3266
     3267  @retval EFI_SUCCESS   Successfully set interface.
     3268
     3269**/
     3270EFI_STATUS
     3271EFIAPI
     3272XhcSetInterface64 (
     3273  IN USB_XHCI_INSTANCE        *Xhc,
     3274  IN UINT8                    SlotId,
     3275  IN UINT8                    DeviceSpeed,
     3276  IN USB_CONFIG_DESCRIPTOR    *ConfigDesc,
     3277  IN EFI_USB_DEVICE_REQUEST   *Request
     3278  )
     3279{
     3280  EFI_STATUS                  Status;
     3281  USB_INTERFACE_DESCRIPTOR    *IfDescActive;
     3282  USB_INTERFACE_DESCRIPTOR    *IfDescSet;
     3283  USB_INTERFACE_DESCRIPTOR    *IfDesc;
     3284  USB_ENDPOINT_DESCRIPTOR     *EpDesc;
     3285  UINTN                       NumEp;
     3286  UINTN                       EpIndex;
     3287  UINT8                       EpAddr;
     3288  UINT8                       Direction;
     3289  UINT8                       Dci;
     3290  UINT8                       MaxDci;
     3291  EFI_PHYSICAL_ADDRESS        PhyAddr;
     3292  VOID                        *RingSeg;
     3293
     3294  CMD_TRB_CONFIG_ENDPOINT     CmdTrbCfgEP;
     3295  INPUT_CONTEXT_64            *InputContext;
     3296  DEVICE_CONTEXT_64           *OutputContext;
     3297  EVT_TRB_COMMAND_COMPLETION  *EvtTrb;
     3298
     3299  Status = EFI_SUCCESS;
     3300
     3301  InputContext  = Xhc->UsbDevContext[SlotId].InputContext;
     3302  OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
     3303  //
     3304  // XHCI 4.6.6 Configure Endpoint
     3305  // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
     3306  // Context and Add Context flags as follows:
     3307  // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop
     3308  // Context and Add Context flags to '0'.
     3309  //
     3310  // Except the interface indicated by Reqeust->Index, no impact to other interfaces.
     3311  // So the default Drop Context and Add Context flags can be '0' to cover 1).
     3312  //
     3313  ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
     3314  CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));
     3315
     3316  ASSERT (ConfigDesc != NULL);
     3317
     3318  MaxDci = 0;
     3319
     3320  IfDescActive = NULL;
     3321  IfDescSet = NULL;
     3322
     3323  IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
     3324  while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {
     3325    if (IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) {
     3326      if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {
     3327        if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {
     3328          //
     3329          // Find out the active interface descriptor.
     3330          //
     3331          IfDescActive = IfDesc;
     3332        } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {
     3333          //
     3334          // Find out the interface descriptor to set.
     3335          //
     3336          IfDescSet = IfDesc;
     3337        }
     3338      }
     3339    }
     3340    IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
     3341  }
     3342
     3343  //
     3344  // XHCI 4.6.6 Configure Endpoint
     3345  // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
     3346  // Context and Add Context flags as follows:
     3347  // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set
     3348  // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.
     3349  // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set
     3350  // the Drop Context flag to '1' and Add Context flag to '0'.
     3351  // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context
     3352  // and Add Context flags shall be set to '1'.
     3353  //
     3354  // Below codes are to cover 2), 3) and 4).
     3355  //
     3356
     3357  if ((IfDescActive != NULL) && (IfDescSet != NULL)) {
     3358    NumEp = IfDescActive->NumEndpoints;
     3359    EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);
     3360    for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
     3361      while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
     3362        EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
     3363      }
     3364
     3365      EpAddr    = (UINT8) (EpDesc->EndpointAddress & 0x0F);
     3366      Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
     3367
     3368      Dci = XhcEndpointToDci (EpAddr, Direction);
     3369      ASSERT (Dci < 32);
     3370      if (Dci > MaxDci) {
     3371        MaxDci = Dci;
     3372      }
     3373      //
     3374      // XHCI 4.3.6 - Setting Alternate Interfaces
     3375      // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
     3376      //
     3377      Status = XhcStopEndpoint (Xhc, SlotId, Dci);
     3378      if (EFI_ERROR (Status)) {
     3379        return Status;
     3380      }
     3381      //
     3382      // XHCI 4.3.6 - Setting Alternate Interfaces
     3383      // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
     3384      //
     3385      if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] != NULL) {
     3386        RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingSeg0;
     3387        if (RingSeg != NULL) {
     3388          UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
     3389        }
     3390        FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
     3391        Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;
     3392      }
     3393
     3394      //
     3395      // Set the Drop Context flag to '1'.
     3396      //
     3397      InputContext->InputControlContext.Dword1 |= (BIT0 << Dci);
     3398
     3399      EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
     3400    }
     3401
     3402    //
     3403    // XHCI 4.3.6 - Setting Alternate Interfaces
     3404    // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate
     3405    // Interface setting, to '0'.
     3406    //
     3407    // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.
     3408    //
     3409
     3410    //
     3411    // XHCI 4.3.6 - Setting Alternate Interfaces
     3412    // 4) For each endpoint enabled by the Configure Endpoint Command:
     3413    //   a. Allocate a Transfer Ring.
     3414    //   b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.
     3415    //   c. Initialize the Endpoint Context data structure.
     3416    //
     3417    Dci = XhcInitializeEndpointContext64 (Xhc, SlotId, DeviceSpeed, InputContext, IfDescSet);
     3418    if (Dci > MaxDci) {
     3419      MaxDci = Dci;
     3420    }
     3421
     3422    InputContext->InputControlContext.Dword2 |= BIT0;
     3423    InputContext->Slot.ContextEntries         = MaxDci;
     3424    //
     3425    // XHCI 4.3.6 - Setting Alternate Interfaces
     3426    // 5) Issue and successfully complete a Configure Endpoint Command.
     3427    //
     3428    ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
     3429    PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
     3430    CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (PhyAddr);
     3431    CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (PhyAddr);
     3432    CmdTrbCfgEP.CycleBit = 1;
     3433    CmdTrbCfgEP.Type     = TRB_TYPE_CON_ENDPOINT;
     3434    CmdTrbCfgEP.SlotId   = Xhc->UsbDevContext[SlotId].SlotId;
     3435    DEBUG ((EFI_D_INFO, "SetInterface64: Configure Endpoint\n"));
     3436    Status = XhcCmdTransfer (
     3437               Xhc,
     3438               (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
     3439               XHC_GENERIC_TIMEOUT,
     3440               (TRB_TEMPLATE **) (UINTN) &EvtTrb
     3441               );
     3442    if (EFI_ERROR (Status)) {
     3443      DEBUG ((EFI_D_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));
     3444    } else {
     3445      //
     3446      // Update the active AlternateSetting.
     3447      //
     3448      Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;
     3449    }
     3450  }
     3451
     3452  return Status;
     3453}
    26743454
    26753455/**
    … …  
    26953475  EVT_TRB_COMMAND_COMPLETION  *EvtTrb;
    26963476  INPUT_CONTEXT               *InputContext;
     3477  EFI_PHYSICAL_ADDRESS        PhyAddr;
    26973478
    26983479  ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
    … …  
    27083489
    27093490  ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
    2710   CmdTrbEvalu.PtrLo    = XHC_LOW_32BIT (InputContext);
    2711   CmdTrbEvalu.PtrHi    = XHC_HIGH_32BIT (InputContext);
     3491  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
     3492  CmdTrbEvalu.PtrLo    = XHC_LOW_32BIT (PhyAddr);
     3493  CmdTrbEvalu.PtrHi    = XHC_HIGH_32BIT (PhyAddr);
    27123494  CmdTrbEvalu.CycleBit = 1;
    27133495  CmdTrbEvalu.Type     = TRB_TYPE_EVALU_CONTXT;
    … …  
    27203502             (TRB_TEMPLATE **) (UINTN) &EvtTrb
    27213503             );
    2722   ASSERT (!EFI_ERROR(Status));
    2723 
     3504  if (EFI_ERROR (Status)) {
     3505    DEBUG ((EFI_D_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
     3506  }
    27243507  return Status;
    27253508}
    … …  
    27473530  EVT_TRB_COMMAND_COMPLETION  *EvtTrb;
    27483531  INPUT_CONTEXT_64            *InputContext;
     3532  EFI_PHYSICAL_ADDRESS        PhyAddr;
    27493533
    27503534  ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
    … …  
    27603544
    27613545  ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
    2762   CmdTrbEvalu.PtrLo    = XHC_LOW_32BIT (InputContext);
    2763   CmdTrbEvalu.PtrHi    = XHC_HIGH_32BIT (InputContext);
     3546  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
     3547  CmdTrbEvalu.PtrLo    = XHC_LOW_32BIT (PhyAddr);
     3548  CmdTrbEvalu.PtrHi    = XHC_HIGH_32BIT (PhyAddr);
    27643549  CmdTrbEvalu.CycleBit = 1;
    27653550  CmdTrbEvalu.Type     = TRB_TYPE_EVALU_CONTXT;
    … …  
    27723557             (TRB_TEMPLATE **) (UINTN) &EvtTrb
    27733558             );
    2774   ASSERT (!EFI_ERROR(Status));
    2775 
     3559  if (EFI_ERROR (Status)) {
     3560    DEBUG ((EFI_D_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
     3561  }
    27763562  return Status;
    27773563}
    … …  
    28003586{
    28013587  EFI_STATUS                  Status;
    2802 
    28033588  EVT_TRB_COMMAND_COMPLETION  *EvtTrb;
    28043589  INPUT_CONTEXT               *InputContext;
    28053590  DEVICE_CONTEXT              *OutputContext;
    28063591  CMD_TRB_CONFIG_ENDPOINT     CmdTrbCfgEP;
     3592  EFI_PHYSICAL_ADDRESS        PhyAddr;
    28073593
    28083594  ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
    … …  
    28273613
    28283614  ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
    2829   CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (InputContext);
    2830   CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (InputContext);
     3615  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
     3616  CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (PhyAddr);
     3617  CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (PhyAddr);
    28313618  CmdTrbCfgEP.CycleBit = 1;
    28323619  CmdTrbCfgEP.Type     = TRB_TYPE_CON_ENDPOINT;
    … …  
    28393626              (TRB_TEMPLATE **) (UINTN) &EvtTrb
    28403627              );
    2841   ASSERT (!EFI_ERROR(Status));
    2842 
     3628  if (EFI_ERROR (Status)) {
     3629    DEBUG ((EFI_D_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
     3630  }
    28433631  return Status;
    28443632}
    … …  
    28663654{
    28673655  EFI_STATUS                  Status;
    2868 
    28693656  EVT_TRB_COMMAND_COMPLETION  *EvtTrb;
    28703657  INPUT_CONTEXT_64            *InputContext;
    28713658  DEVICE_CONTEXT_64           *OutputContext;
    28723659  CMD_TRB_CONFIG_ENDPOINT     CmdTrbCfgEP;
     3660  EFI_PHYSICAL_ADDRESS        PhyAddr;
    28733661
    28743662  ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
    … …  
    28933681
    28943682  ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
    2895   CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (InputContext);
    2896   CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (InputContext);
     3683  PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
     3684  CmdTrbCfgEP.PtrLo    = XHC_LOW_32BIT (PhyAddr);
     3685  CmdTrbCfgEP.PtrHi    = XHC_HIGH_32BIT (PhyAddr);
    28973686  CmdTrbCfgEP.CycleBit = 1;
    28983687  CmdTrbCfgEP.Type     = TRB_TYPE_CON_ENDPOINT;
    … …  
    29053694              (TRB_TEMPLATE **) (UINTN) &EvtTrb
    29063695              );
    2907   ASSERT (!EFI_ERROR(Status));
    2908 
     3696  if (EFI_ERROR (Status)) {
     3697    DEBUG ((EFI_D_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
     3698  }
    29093699  return Status;
    29103700}

  • trunk/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h

    r48674 r58459  
    33  This file contains the definition for XHCI host controller schedule routines.
    44
    5 Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>
     5Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
    66This program and the accompanying materials
    77are licensed and made available under the terms and conditions of the BSD License
    … …  
    173173  VOID                            *Data;
    174174  UINTN                           DataLen;
     175  VOID                            *DataPhy;
     176  VOID                            *DataMap;
    175177  EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
    176178  VOID                            *Context;
    … …  
    10401042  );
    10411043
     1044/**
     1045  Set interface through XHCI's Configure_Endpoint cmd.
     1046
     1047  @param  Xhc           The XHCI Instance.
     1048  @param  SlotId        The slot id to be configured.
     1049  @param  DeviceSpeed   The device's speed.
     1050  @param  ConfigDesc    The pointer to the usb device configuration descriptor.
     1051  @param  Request       USB device request to send.
     1052
     1053  @retval EFI_SUCCESS   Successfully set interface.
     1054
     1055**/
     1056EFI_STATUS
     1057EFIAPI
     1058XhcSetInterface (
     1059  IN USB_XHCI_INSTANCE        *Xhc,
     1060  IN UINT8                    SlotId,
     1061  IN UINT8                    DeviceSpeed,
     1062  IN USB_CONFIG_DESCRIPTOR    *ConfigDesc,
     1063  IN EFI_USB_DEVICE_REQUEST   *Request
     1064  );
     1065
     1066/**
     1067  Set interface through XHCI's Configure_Endpoint cmd.
     1068
     1069  @param  Xhc           The XHCI Instance.
     1070  @param  SlotId        The slot id to be configured.
     1071  @param  DeviceSpeed   The device's speed.
     1072  @param  ConfigDesc    The pointer to the usb device configuration descriptor.
     1073  @param  Request       USB device request to send.
     1074
     1075  @retval EFI_SUCCESS   Successfully set interface.
     1076
     1077**/
     1078EFI_STATUS
     1079EFIAPI
     1080XhcSetInterface64 (
     1081  IN USB_XHCI_INSTANCE        *Xhc,
     1082  IN UINT8                    SlotId,
     1083  IN UINT8                    DeviceSpeed,
     1084  IN USB_CONFIG_DESCRIPTOR    *ConfigDesc,
     1085  IN EFI_USB_DEVICE_REQUEST   *Request
     1086  );
    10421087
    10431088/**
    … …  
    13071352
    13081353/**
     1354  Free an allocated URB.
     1355
     1356  @param  Xhc                   The XHCI device.
     1357  @param  Urb                   The URB to free.
     1358
     1359**/
     1360VOID
     1361XhcFreeUrb (
     1362  IN USB_XHCI_INSTANCE    *Xhc,
     1363  IN URB                  *Urb
     1364  );
     1365
     1366/**
    13091367  Create a transfer TRB.
    13101368
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