Changeset 66327 in vbox for trunk/src/VBox

Timestamp:

Mar 29, 2017 10:12:02 AM (8 years ago)

Author:

vboxsync

Message:

IEM,CPUM: Implemented clflush Mb (0f ae /7).

Location:

trunk/src/VBox

Files:

• VMM/VMMAll/IEMAllCImpl.cpp.h (modified) (1 diff)
• VMM/VMMAll/IEMAllInstructionsPython.py (modified) (4 diffs)
• VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (1 diff)
• VMM/VMMR3/CPUMR3CpuId.cpp (modified) (2 diffs)
• ValidationKit/bootsectors/bs3-cpu-generated-1-template.c (modified) (5 diffs)
• ValidationKit/bootsectors/bs3-cpu-generated-1.h (modified) (3 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h

@@ -6775 +6775 @@
 
 /**
+ * Implements 'CLFLUSH' and 'CLFLUSHOPT'.
+ *
+ * This is implemented in C because it triggers a load like behviour without
+ * actually reading anything.  Since that's not so common, it's implemented
+ * here.
+ *
+ * @param   iEffSeg         The effective segment.
+ * @param   GCPtrEff        The address of the image.
+ */
+IEM_CIMPL_DEF_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
+{
+    /*
+     * Pretend to do a load w/o reading (see also iemCImpl_monitor and iemMemMap).
+     */
+    VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrEff);
+    if (rcStrict == VINF_SUCCESS)
+    {
+        RTGCPHYS GCPhysMem;
+        rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrEff, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
+        if (rcStrict == VINF_SUCCESS)
+        {
+            iemRegAddToRipAndClearRF(pVCpu, cbInstr);
+            return VINF_SUCCESS;
+        }
+    }
+
+    return rcStrict;
+}
+
+
+/**
  * Implements 'FINIT' and 'FNINIT'.
  *

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py

@@ -174 +174 @@
     # ModR/M.rm - memory only.
     'Ma':   ( 'IDX_UseModRM',       'rm',     '%Ma',  'Ma',      ), ##< Only used by BOUND.
+    'MbRO': ( 'IDX_UseModRM',       'rm',     '%Mb',  'Mb',      ),
     'Mq':   ( 'IDX_UseModRM',       'rm',     '%Mq',  'Mq',      ),
 
@@ -1781 +1782 @@
         """
         Tag:        \@opcode
-        Value:      0x?? | /reg | mr/reg | 11 /reg | !11 /reg | 11 mr/reg | !11 mr/reg
+        Value:      0x?? | /reg (TODO: | mr/reg | 11 /reg | !11 /reg | 11 mr/reg | !11 mr/reg)
 
         The opcode byte or sub-byte for the instruction in the context of a map.
@@ -1789 +1790 @@
         # Flatten and validate the value.
         sOpcode = self.flattenAllSections(aasSections);
-        if sOpcode in g_kdSpecialOpcodes:
+        if _isValidOpcodeByte(sOpcode):
             pass;
-        elif not _isValidOpcodeByte(sOpcode):
+        elif len(sOpcode) == 2 and sOpcode[0] == '/' and sOpcode[1] in '012345678':
+            pass;
+        else:
             return self.errorComment(iTagLine, '%s: invalid opcode: %s' % (sTag, sOpcode,));
 
@@ -2637 +2640 @@
             # Check the parameter locations for the encoding.
             if g_kdIemForms[sForm][1] is not None:
-                for iOperand, sWhere in enumerate(g_kdIemForms[sForm][1]):
-                    if oInstr.aoOperands[iOperand].sWhere != sWhere:
-                        self.error('%s: current instruction @op%u and a_Form location does not match: %s vs %s (%s)'
-                                   % (sMacro, iOperand + 1, oInstr.aoOperands[iOperand].sWhere, sWhere, sForm,));
+                if len(g_kdIemForms[sForm][1]) != len(oInstr.aoOperands):
+                    self.error('%s: The a_Form=%s has a different operand count: %s (form) vs %s'
+                               % (sMacro, sForm, len(g_kdIemForms[sForm][1]), len(oInstr.aoOperands) ));
+                else:
+                    for iOperand, sWhere in enumerate(g_kdIemForms[sForm][1]):
+                        if oInstr.aoOperands[iOperand].sWhere != sWhere:
+                            self.error('%s: current instruction @op%u and a_Form location does not match: %s vs %s (%s)'
+                                       % (sMacro, iOperand + 1, oInstr.aoOperands[iOperand].sWhere, sWhere, sForm,));
 
         # Stats.

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h

@@ -5839 +5839 @@
 FNIEMOP_UD_STUB_1(iemOp_Grp15_xsaveopt, uint8_t, bRm);
 
-/** Opcode 0x0f 0xae mem/7. */
-FNIEMOP_STUB_1(iemOp_Grp15_clflush,  uint8_t, bRm);
+/**
+ * @opmaps      grp15
+ * @opcode      /7
+ * @oppfx       none
+ * @opcpuid     clfsh
+ * @opgroup     og_sse2_cachectl
+ * @optest      op1=1 ->
+ * @oponlytest
+ */
+FNIEMOP_DEF_1(iemOp_Grp15_clflush,  uint8_t, bRm)
+{
+    /** @todo clflushopt is same with 66h prefix.   */
+    IEMOP_MNEMONIC1(M_MEM, CLFLUSH, clflush, MbRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fClFlush)
+        return IEMOP_RAISE_INVALID_OPCODE();
+
+    IEM_MC_BEGIN(2, 0);
+    IEM_MC_ARG(uint8_t,         iEffSeg,                                 0);
+    IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
+    IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+    IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
+    IEM_MC_CALL_CIMPL_2(iemCImpl_clflush_clflushopt, iEffSeg, GCPtrEff);
+    IEM_MC_END();
+    return VINF_SUCCESS;
+}
 
 

trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

@@ -1635 +1635 @@
         pFeatures->fMonitorMWait        = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
         pFeatures->fMovCmpXchg16b       = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
+        pFeatures->fClFlush             = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
 
         /* Structured extended features. */
@@ -1642 +1643 @@
             pFeatures->fAvx2                = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
             pFeatures->fAvx512Foundation    = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
+            pFeatures->fClFlushOpt          = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
         }
 

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c

@@ -1544 +1544 @@
             break;
 
+        case BS3CG1ENC_MODRM_MbRO:
+            if (iEncoding == 0)
+            {
+                off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)) - 1;
+                off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
+                                               (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
+                                               1, 0, BS3CG1OPLOC_MEM);
+            }
+            else
+                break;
+            pThis->cbCurInstr = off;
+            iEncoding++;
+            break;
+
+
         case BS3CG1ENC_FIXED:
             if (iEncoding == 0)
@@ -1805 +1820 @@
             pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
             pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
+            break;
+
+        case BS3CG1ENC_MODRM_MbRO:
+            pThis->iRmOp             = 0;
+            pThis->aOperands[0].cbOp = 1;
+            pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM;
             break;
 
@@ -1914 +1935 @@
         case BS3CG1CPU_GE_80486:
         case BS3CG1CPU_GE_Pentium:
+        case BS3CG1CPU_CLFSH:
             return false;
 
@@ -2020 +2042 @@
             {
                 ASMCpuIdExSlow(7, 0, 0/*leaf*/, 0, &fEax, &fEbx, &fEcx, &fEdx);
-
                 switch (pThis->enmCpuTest)
                 {
@@ -2031 +2052 @@
             }
             return false;
+
+        case BS3CG1CPU_CLFSH:
+            if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
+            {
+                ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, NULL, &fEdx);
+                if (fEdx & X86_CPUID_FEATURE_EDX_CLFSH)
+                    return true;
+            }
+            return false;
+
 
         default:

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h

@@ -69 +69 @@
 
     BS3CG1OP_Ma,
+    BS3CG1OP_MbRO,
     BS3CG1OP_Mq,
 
@@ -101 +102 @@
     BS3CG1ENC_MODRM_Vq_Mq,
     BS3CG1ENC_MODRM_Vdq_Wdq,
+    BS3CG1ENC_MODRM_MbRO,
 
     BS3CG1ENC_FIXED,
@@ -150 +152 @@
     BS3CG1CPU_AVX,
     BS3CG1CPU_AVX2,
+    BS3CG1CPU_CLFSH,
+
     BS3CG1CPU_END
 } BS3CG1CPU;