VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0

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Diff Rev Age Author Log Message
(edit) @12070   16 years vboxsync And another fix
(edit) @12069   16 years vboxsync Build fix
(edit) @12068   16 years vboxsync More release logging for the VERR_VMX_INVALID_VMCS_PTR case.
(edit) @12063   16 years vboxsync Compile fix
(edit) @12062   16 years vboxsync Harmless update (unused code).
(edit) @11767   16 years vboxsync VT-x: always enable caching in cr0.
(edit) @11763   16 years vboxsync Host CR0 CD, NW & ET bits are not restored after a VM exit. We must …
(edit) @11761   16 years vboxsync Filter out X86_CR0_CACHE_DISABLE as well for VT-x. (duh!)
(edit) @11757   16 years vboxsync No room for this
(edit) @11756   16 years vboxsync Use the wbinvd intercept if it's present in the secondary control.
(edit) @11706   16 years vboxsync No need to enable VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS
(edit) @11697   16 years vboxsync Comment update
(edit) @11696   16 years vboxsync Enabled MSR bitmap for VT-x.
(edit) @11575   16 years vboxsync Sync back CR2 as it can be changed behind our back in the nested …
(edit) @11568   16 years vboxsync Cleanup
(edit) @11517   16 years vboxsync More logging
(edit) @11516   16 years vboxsync Forgot IA32_MSR_STAR syncing.
(edit) @11488   16 years vboxsync stoswd emulation fix (DF).
(edit) @11474   16 years vboxsync AMD-V: Corrected current asid handling. (multiple VMs could end up …
(edit) @11398   16 years vboxsync Always sync back the TPR value.
(edit) @11311   16 years vboxsync VMM: ELEMENTS -> RT_ELEMENTS.
(edit) @11133   16 years vboxsync compiler warnings
(edit) @10886   16 years vboxsync Fixes for syncing back sysenter MSRs.
(edit) @10858   16 years vboxsync We can't rely on #NM handling in kernel mode, so do what we did before …
(edit) @10849   16 years vboxsync 32 bits build fix
(edit) @10844   16 years vboxsync VMMR0: Fixed bogus pSession argument passed to vmmR0EntryExWorker when …
(edit) @10843   16 years vboxsync intnet: Implemented activation on power on & resume, deactivation on …
(edit) @10835   16 years vboxsync Obsolete comment removed
(edit) @10833   16 years vboxsync Backed out 33617. Doesn't solve anything.
(edit) @10832   16 years vboxsync TPR shadow changes.
(edit) @10828   16 years vboxsync Update
(edit) @10817   16 years vboxsync Started with EPT support.
(edit) @10806   16 years vboxsync intnet: Push the session down to all the INTNETR0* apis.
(edit) @10805   16 years vboxsync VMM+SUPDrv: Changed the VMMR0EntryEx interface to also take the …
(edit) @10746   16 years vboxsync Added pSession argument to all the intnet request packets.
(edit) @10724   16 years vboxsync Bumped the SUPDRV_IOC_VERSION major as the changes to the fast path on …
(edit) @10721   16 years vboxsync Missing update for last error handling.
(edit) @10716   16 years vboxsync TPR fix for VT-x
(edit) @10687   16 years vboxsync Save the FPU control word and MXCSR on entry and restore them …
(edit) @10683   16 years vboxsync Backed out 33399; must save the host context on entry due to long …
(edit) @10682   16 years vboxsync Saving of the host state is done correctly already for VT-x. (not …
(edit) @10673   16 years vboxsync Comment added.
(edit) @10672   16 years vboxsync Added a comment about the fact that we trash our own FPU state. Could …
(edit) @10667   16 years vboxsync Sync back TPR if necessary.
(edit) @10663   16 years vboxsync Created tstIntNet-1 for checking that capturing an interface works on …
(edit) @10661   16 years vboxsync Reduce the number of world switches caused by cr8 writes by checking …
(edit) @10655   16 years vboxsync Guest MSR_K6_EFER_FFXSR value is not relevant. Always manually …
(edit) @10647   16 years vboxsync Manual saving of XMM registers. Use new FPU/MMX/XMM state saving for …
(edit) @10630   16 years vboxsync Newer functions for handling fpu save/restore in ring 0.
(edit) @10609   16 years vboxsync Check for unexpected rescheduling.
(edit) @10607   16 years vboxsync Guest state loading and host state saving *must* be done after TPR …
(edit) @10572   16 years vboxsync Use NIL_RTR0MEMOBJ and ASMMemZeroPage.
(edit) @10566   16 years vboxsync Comment
(edit) @10542   16 years vboxsync Go directly to the halted state when encountering a hlt instruction …
(edit) @10537   16 years vboxsync Updated HWACCMDumpRegs
(edit) @10509   16 years vboxsync And again
(edit) @10508   16 years vboxsync Stupid compiler
(edit) @10506   16 years vboxsync Assertion
(edit) @10505   16 years vboxsync Easier to grep for
(edit) @10504   16 years vboxsync Don't violate my own rules…
(edit) @10503   16 years vboxsync More logging
(edit) @10502   16 years vboxsync Take precautions for being rescheduled to a different cpu due to long …
(edit) @10500   16 years vboxsync Clarified comment
(edit) @10499   16 years vboxsync Another paranoid assertion.
(edit) @10498   16 years vboxsync Added warning
(edit) @10497   16 years vboxsync Another edge case where we need to flush the TLB.
(edit) @10491   16 years vboxsync Logging
(edit) @10489   16 years vboxsync AMD-V: Always flush the TLB the first time a cpu is used.
(edit) @10480   16 years vboxsync Must monitor CR8 writes. (for now)
(edit) @10473   16 years vboxsync MMIO instruction emulation for OR, BT and XOR added.
(edit) @10471   16 years vboxsync warning
(edit) @10466   16 years vboxsync Write back cached TPR
(edit) @10465   16 years vboxsync Cleaned up
(edit) @10464   16 years vboxsync More assertions
(edit) @10463   16 years vboxsync Use the TPR threshold feature.
(edit) @10458   16 years vboxsync TPR & interrupt dispatch updates.
(edit) @10450   16 years vboxsync Added VMMGetSvnRev() (exported) and changed VMMR0Init and VMMGCInit …
(edit) @10360   16 years vboxsync Removed the same assertion as before in the AMD-V code.
(edit) @10356   16 years vboxsync Safety precaution
(edit) @10355   16 years vboxsync TPR updates
(edit) @10354   16 years vboxsync Extra assertion
(edit) @10353   16 years vboxsync TPR caching for VT-x. Removed the CR8 register from CPUMCTX.
(edit) @10331   16 years vboxsync Removed the assertion completely.
(edit) @10330   16 years vboxsync Wrong assertion. Due to ring 3 far jumps the assertion condition can …
(edit) @10301   16 years vboxsync Wrong place for the assertion
(edit) @10299   16 years vboxsync Force a TLB flush on a mode switch too.
(edit) @10297   16 years vboxsync More assertions.
(edit) @10269   16 years vboxsync Logging updates
(edit) @10206   16 years vboxsync Fixed regression introduced by TPR caching. (never execute code that …
(edit) @10202   16 years vboxsync removed VBOX_WITH_PDM_LOCK
(edit) @10110   16 years vboxsync More TPR updates
(edit) @10108   16 years vboxsync More CR8 updates
(edit) @10097   16 years vboxsync Derive CPL from cs, not ss.
(edit) @10095   16 years vboxsync logging change
(edit) @10066   16 years vboxsync Paranoid assertion
(edit) @10064   16 years vboxsync Missing log group
(edit) @10019   16 years vboxsync Updated for accepted shadow page modes.
(edit) @10018   16 years vboxsync Wrong assertion + logging updates
(edit) @10015   16 years vboxsync Don't forget to sync back MSR_K8_KERNEL_GS_BASE.
(edit) @10014   16 years vboxsync Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow …
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