|
|
|
@106739
|
4 months |
vboxsync |
Disassembler: Decode more barrier and addg/subg instructions, bugref:10394
|
|
|
|
@106737
|
4 months |
vboxsync |
Disassembler: Decode adc/adcs/sbc/sbcs/rmif/setf8/setf16 instructions, …
|
|
|
|
@106735
|
4 months |
vboxsync |
Disassembler: Decode pacga instruction, bugref:10394
|
|
|
|
@106734
|
4 months |
vboxsync |
Disassembler: Decode immediate variants of cmmn/ccmp instructions, …
|
|
|
|
@106706
|
4 months |
vboxsync |
Disassembler: Decode 3-source register data processing instructions, …
|
|
|
|
@106705
|
4 months |
vboxsync |
Disassembler: Decode conditional select instructions, bugref:10394
|
|
|
|
@106694
|
4 months |
vboxsync |
Disassembler: Decode ldnp/stnp non temporal hint load/store …
|
|
|
|
@106680
|
4 months |
vboxsync |
Disasembler: Decode extr instruction, bugref:10394
|
|
|
|
@106679
|
4 months |
vboxsync |
Disasembler: Decode unprivileged load/store instructions, bugref:10394
|
|
|
|
@106668
|
4 months |
vboxsync |
Disassembler/testcase/tstDisasmArmv8-1-asm.S: Exclude some …
|
|
|
|
@106659
|
4 months |
vboxsync |
Disassembler: Decode post-indexed load/store instructions, bugref:10394
|
|
|
|
@106657
|
4 months |
vboxsync |
Disassembler: Decode pre-indexed load instructions, bugref:10394
|
|
|
|
@106649
|
4 months |
vboxsync |
Disassembler: Decode more branch instructions, change the opcode table …
|
|
|
|
@106632
|
4 months |
vboxsync |
Disassembler: Decode more hint instructions instructions, bugref:10394
|
|
|
|
@106631
|
4 months |
vboxsync |
Disassembler: Decode data processing 1-source instructions, bugref:10394
|
|
|
|
@106627
|
4 months |
vboxsync |
Disassembler: Decode irg, gmi and subp instructions, bugref:10394
|
|
|
|
@106626
|
4 months |
vboxsync |
Disassembler: Re-arrange the ARMv8 tables to allow for multiple …
|
|
|
|
@106616
|
4 months |
vboxsync |
Disassembler: Fix decoding instructions which take sp as a register …
|
|
|
|
@106018
|
6 months |
vboxsync |
Disassembler/ArmV8: Updates and start on floating point and SIMD …
|
|
|
|
@106004
|
6 months |
vboxsync |
Disassembler/ArmV8: Updates and start on floating point and SIMD …
|
|
|
|
@105858
|
6 months |
vboxsync |
Disassembler/ARMv8: Implement decoding of the ldr/str …
|
|
|
|
@105857
|
6 months |
vboxsync |
Disassembler/ARMv8: Implement decoding of the ldr/str (unscaled …
|
|
|
|
@105848
|
6 months |
vboxsync |
Disassembler/ARMv8: Support disassembling the load/store register …
|
|
|
|
@105830
|
6 months |
vboxsync |
Disassembler/ARMv8: Implement decoding of the ldp/stp unsigned variant …
|
|
|
|
@105815
|
6 months |
vboxsync |
Disassembler/ARMv8: Started decoding more ldr/str instruction …
|
|
|
|
@105810
|
6 months |
vboxsync |
Disassembler/ARMv8: Implement disassembly of ccmp/ccmn register …
|
|
|
|
@105796
|
6 months |
vboxsync |
Disassembler/ARMv8: Start some very simple alias conversion for orr -> …
|
|
|
|
@105793
|
6 months |
vboxsync |
Disassembler/ARMv8: Updates, decode br/blr instructions, add them to …
|
|
|
|
@105790
|
6 months |
vboxsync |
Disassembler/ARMv8: Updates, decode add/adds/sub/subs shifted …
|
|
|
|
@105785
|
6 months |
vboxsync |
Disassembler/ARMv8: Updates, decode basic ldr/str (unsigned with …
|
|
|
|
@105779
|
6 months |
vboxsync |
Disassembler/ARMv8: Updates, decode more instructions, add them to the …
|
|
|
|
@105759
|
6 months |
vboxsync |
Disassembler/testcase: Add tstDisasmArmv8-1 testcase for testing the …
|
|
|
|
@105758
|
6 months |
vboxsync |
Disassembler/testcase: Add tstDisasmArmv8-1 testcase for testing the …
|
|
|
|
@105748
|
6 months |
vboxsync |
Disassembler/testcase: Add tstDisasmArmv8-1 testcase for testing the …
|
