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tstDisasmArmv8-1-asm.S

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	Rev	Age	Author	Log Message
(edit)	@106817	4 months	vboxsync	Disassembler: Decode SIMD load/store multiple structures …
(edit)	@106816	4 months	vboxsync	Disassembler: Decode SIMD load/store multiple structures …
(edit)	@106805	4 months	vboxsync	Disassembler: Decode RCW compare and swap and RCW compare and swap …
(edit)	@106791	4 months	vboxsync	Disassembler: Decode Advanced SIMD load/store multiple structures …
(edit)	@106783	4 months	vboxsync	Disassembler: Decode Load/Store ordered instructions, bugref:10394
(edit)	@106782	4 months	vboxsync	Disassembler: Decode Load/Store exclusive pair instructions, bugref:10394
(edit)	@106777	4 months	vboxsync	Disassembler: Decode Load/Store exclusive register instructions, …
(edit)	@106774	4 months	vboxsync	Disassembler: Compare and swap instructions, bugref:10394 [fix]
(edit)	@106772	4 months	vboxsync	Disassembler: Compare and swap instructions, bugref:10394
(edit)	@106770	4 months	vboxsync	Disassembler: Decode load/store memory tags instructions, bugref:10394
(edit)	@106768	4 months	vboxsync	Disassembler: Decode ldr/ldrsw (literal) instructions, bugref:10394
(edit)	@106767	4 months	vboxsync	Disassembler: Decode atomic memory operation instructions (FEAT_LSE, …
(edit)	@106760	4 months	vboxsync	Disassembler: Decode Add/Subtract (extended register) instructions, …
(edit)	@106758	4 months	vboxsync	Disassembler: Decode ldraa/ldrab instructions, bugref:10394
(edit)	@106757	4 months	vboxsync	Disassembler: Decode SIMD ldr/str (immediate pre index) instructions, …
(edit)	@106756	4 months	vboxsync	Disassembler: Decode SIMD ldr/str (immediate post index) instructions, …
(edit)	@106754	4 months	vboxsync	Disassembler: Decode SIMD ldnp/stnp (no allocate register pair) …
(edit)	@106752	4 months	vboxsync	Disassembler: Decode SIMD ldur/stur (unscaled immediate) instructions, …
(edit)	@106751	4 months	vboxsync	Disassembler: Decode SIMD ldr/str (register offset) instructions, …
(edit)	@106746	4 months	vboxsync	Disassembler: Decode SIMD ldr/str instructions, bugref:10394
(edit)	@106739	4 months	vboxsync	Disassembler: Decode more barrier and addg/subg instructions, bugref:10394
(edit)	@106737	4 months	vboxsync	Disassembler: Decode adc/adcs/sbc/sbcs/rmif/setf8/setf16 instructions, …
(edit)	@106735	4 months	vboxsync	Disassembler: Decode pacga instruction, bugref:10394
(edit)	@106734	4 months	vboxsync	Disassembler: Decode immediate variants of cmmn/ccmp instructions, …
(edit)	@106706	4 months	vboxsync	Disassembler: Decode 3-source register data processing instructions, …
(edit)	@106705	4 months	vboxsync	Disassembler: Decode conditional select instructions, bugref:10394
(edit)	@106694	4 months	vboxsync	Disassembler: Decode ldnp/stnp non temporal hint load/store …
(edit)	@106680	4 months	vboxsync	Disasembler: Decode extr instruction, bugref:10394
(edit)	@106679	4 months	vboxsync	Disasembler: Decode unprivileged load/store instructions, bugref:10394
(edit)	@106668	4 months	vboxsync	Disassembler/testcase/tstDisasmArmv8-1-asm.S: Exclude some …
(edit)	@106659	4 months	vboxsync	Disassembler: Decode post-indexed load/store instructions, bugref:10394
(edit)	@106657	4 months	vboxsync	Disassembler: Decode pre-indexed load instructions, bugref:10394
(edit)	@106649	4 months	vboxsync	Disassembler: Decode more branch instructions, change the opcode table …
(edit)	@106632	4 months	vboxsync	Disassembler: Decode more hint instructions instructions, bugref:10394
(edit)	@106631	4 months	vboxsync	Disassembler: Decode data processing 1-source instructions, bugref:10394
(edit)	@106627	4 months	vboxsync	Disassembler: Decode irg, gmi and subp instructions, bugref:10394
(edit)	@106626	4 months	vboxsync	Disassembler: Re-arrange the ARMv8 tables to allow for multiple …
(edit)	@106616	4 months	vboxsync	Disassembler: Fix decoding instructions which take sp as a register …
(edit)	@106018	6 months	vboxsync	Disassembler/ArmV8: Updates and start on floating point and SIMD …
(edit)	@106004	6 months	vboxsync	Disassembler/ArmV8: Updates and start on floating point and SIMD …
(edit)	@105858	6 months	vboxsync	Disassembler/ARMv8: Implement decoding of the ldr/str …
(edit)	@105857	6 months	vboxsync	Disassembler/ARMv8: Implement decoding of the ldr/str (unscaled …
(edit)	@105848	6 months	vboxsync	Disassembler/ARMv8: Support disassembling the load/store register …
(edit)	@105830	6 months	vboxsync	Disassembler/ARMv8: Implement decoding of the ldp/stp unsigned variant …
(edit)	@105815	6 months	vboxsync	Disassembler/ARMv8: Started decoding more ldr/str instruction …
(edit)	@105810	6 months	vboxsync	Disassembler/ARMv8: Implement disassembly of ccmp/ccmn register …
(edit)	@105796	6 months	vboxsync	Disassembler/ARMv8: Start some very simple alias conversion for orr -> …
(edit)	@105793	6 months	vboxsync	Disassembler/ARMv8: Updates, decode br/blr instructions, add them to …
(edit)	@105790	6 months	vboxsync	Disassembler/ARMv8: Updates, decode add/adds/sub/subs shifted …
(edit)	@105785	6 months	vboxsync	Disassembler/ARMv8: Updates, decode basic ldr/str (unsigned with …
(edit)	@105779	6 months	vboxsync	Disassembler/ARMv8: Updates, decode more instructions, add them to the …
(edit)	@105759	6 months	vboxsync	Disassembler/testcase: Add tstDisasmArmv8-1 testcase for testing the …
(edit)	@105758	6 months	vboxsync	Disassembler/testcase: Add tstDisasmArmv8-1 testcase for testing the …
(add)	@105748	6 months	vboxsync	Disassembler/testcase: Add tstDisasmArmv8-1 testcase for testing the …

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