|
|
|
@55312
|
10 years |
vboxsync |
CPUM: Must load additional extended CPU state when added to (guest) XCR0.
|
|
|
|
@55292
|
10 years |
vboxsync |
HM,CPUM,IEM: XSETBV fixes and adjustments.
|
|
|
|
@55289
|
10 years |
vboxsync |
IEM,CPUM: Implemented XSETBV and XGETBV.
|
|
|
|
@55229
|
10 years |
vboxsync |
CPUM,IEM: Expose GuestFeatures and HostFeatures (exploded CPUID), …
|
|
|
|
@55062
|
10 years |
vboxsync |
Remove CPUFeatures and CPUFeaturesExt from CPUM, use HostFeatures …
|
|
|
|
@55000
|
10 years |
vboxsync |
CPUMCTXCORE elimination.
|
|
|
|
@54862
|
10 years |
vboxsync |
Corrected x86.h/mac typo.
|
|
|
|
@54760
|
10 years |
vboxsync |
CPUMGetGuestCpuId: Fixed APIC ID assertions to read the pLeaf values …
|
|
|
|
@54737
|
10 years |
vboxsync |
VMM,REM: CPUID revamp - almost there now.
|
|
|
|
@54714
|
10 years |
vboxsync |
PATM,CPUM: CPUID patch update.
|
|
|
|
@54674
|
10 years |
vboxsync |
CPUM: Working on refactoring the guest CPUID handling.
|
|
|
|
@53467
|
10 years |
vboxsync |
VMM: Removed VBOX_WITH_NEW_MSR_CODE and the code marked ifndef …
|
|
|
|
@52770
|
10 years |
vboxsync |
VMM/CPUM: Fix EFER WRMSR to ignore EFER.LMA bit, trunk regression …
|
|
|
|
@52717
|
10 years |
vboxsync |
VMM/CPUM: Raise #GP(0) while writing to disallowed EFER bits.
|
|
|
|
@51729
|
10 years |
vboxsync |
Recently missed header updates.
|
|
|
|
@51728
|
10 years |
vboxsync |
VMM: Add MWait Extensions as a CPUM feature to allow configuring it …
|
|
|
|
@51720
|
10 years |
vboxsync |
VMM: Doxygen bugref comment consistency.
|
|
|
|
@51301
|
11 years |
vboxsync |
VMM: Retire aGuestCpuIdHyper legacy array.
|
|
|
|
@50785
|
11 years |
vboxsync |
CPUMAllRegs: comment nit.
|
|
|
|
@49972
|
11 years |
vboxsync |
CPUM: More msr hacking.
|
|
|
|
@49893
|
11 years |
vboxsync |
MSR rewrite: initial hacking - half disabled.
|
|
|
|
@49849
|
11 years |
vboxsync |
VMM: Use EFER.LMA in PAE-paging mode check rather than EFER.LME.
|
|
|
|
@49549
|
11 years |
vboxsync |
VMM/CPUM/MSRs: when returning the APIC base, don't rely upon the CPUID …
|
|
|
|
@49479
|
11 years |
vboxsync |
VMM: Warnings.
|
|
|
|
@49360
|
11 years |
vboxsync |
Stopgap MSR fixes (better MSR implementation is underways, just very …
|
|
|
|
@49355
|
11 years |
vboxsync |
VMM/CPUM: MSR_P4_LASTBRANCH_* is not Intel-specific
|
|
|
|
@49354
|
11 years |
vboxsync |
Stop gap MSR fixes (better MSR implementation is underways, just very …
|
|
|
|
@49019
|
11 years |
vboxsync |
VMM: FPU cleanup.
|
|
|
|
@48697
|
11 years |
vboxsync |
build fix
|
|
|
|
@48695
|
11 years |
vboxsync |
CPUM: MSR_CORE_THREAD_COUNT and MSR_FLEX_RATIO for snow leopard.
|
|
|
|
@48602
|
11 years |
vboxsync |
LogRel consistency.
|
|
|
|
@48567
|
11 years |
vboxsync |
CPUMR0: Avoid EFER writes whenever possible. Don't know which kernels …
|
|
|
|
@48544
|
11 years |
vboxsync |
VMM/CPUM: Guest and Hyper-debug state pending 32->64 switcher case helpers.
|
|
|
|
@48368
|
11 years |
vboxsync |
Implement MSR_PKG_CST_CONFIG_CONTROL for mac os x.
|
|
|
|
@48357
|
11 years |
vboxsync |
The intel_pstate Linux driver depends on these two MSRs
|
|
|
|
@48308
|
11 years |
vboxsync |
VMM: Log cosmetics.
|
|
|
|
@48203
|
11 years |
vboxsync |
Ignore IA32_PMC0/1, too.
|
|
|
|
@48202
|
11 years |
vboxsync |
Ignore MSR_IA32_PERFEVTSEL1 and MSR_IA32_PERFEVTSEL0 reads. Should …
|
|
|
|
@48151
|
11 years |
vboxsync |
Netware 6 is reading MSR_P4_LASTBRANCH_0 (0x1db).
|
|
|
|
@48144
|
11 years |
vboxsync |
Allow reading P5_MC_ADDR and P5_MC_TYPE.
|
|
|
|
@48142
|
11 years |
vboxsync |
intel manuals hints that there should be at least 8 variables one.
|
|
|
|
@48141
|
11 years |
vboxsync |
QNX doesn't believe our MTRR_CAP report and messes with the variable …
|
|
|
|
@48119
|
11 years |
vboxsync |
Another intel MSR.
|
|
|
|
@48077
|
11 years |
vboxsync |
ignore MSR_K8_VM_CR on AMD
|
|
|
|
@48075
|
11 years |
vboxsync |
Another MSR people like to read.
|
|
|
|
@48066
|
11 years |
vboxsync |
CPUM: Fake MSR_IA32_MCG_STATUS reads. Corrected MSR names, IA32_MCP …
|
|
|
|
@48026
|
11 years |
vboxsync |
Ignore MSR_IA32_DEBUGCTL access for now, should be virtualized later.
|
|
|
|
@48024
|
11 years |
vboxsync |
Since AMD has MSR_IA32_MCP_CAP, we have to fake the other machine …
|
|
|
|
@48000
|
11 years |
vboxsync |
Windows 7 want MSR_IA32_MCP_CAP on AMD64 too.
|
|
|
|
@47996
|
11 years |
vboxsync |
More MSRs fixes on AMD64. MSR_K8_NB_CFG is for recent linux kernels …
|
|
|
|
@47988
|
11 years |
vboxsync |
Solaris reads MSR_RAPL_POWER_UNIT, give it some fake values.
|
|
|
|
@47942
|
11 years |
vboxsync |
CPUM: Ignore MSR_K8_INT_PENDING access.
|
|
|
|
@47939
|
11 years |
vboxsync |
Ignore MSR_K8_SYSCFG on AMD64 like we used to do.
|
|
|
|
@47828
|
11 years |
vboxsync |
CPUMRecalcHyperDRx: Fixed raw-mode assertion.
|
|
|
|
@47714
|
11 years |
vboxsync |
CPUMRecalcHyperDRx: Host single stepping in HM-mode fix.
|
|
|
|
@47706
|
11 years |
vboxsync |
Must be careful in ring-3 too.
|
|
|
|
@47661
|
11 years |
vboxsync |
build fix
|
|
|
|
@47660
|
11 years |
vboxsync |
VMM: Debug register handling redo. (only partly tested on AMD-V so far.)
|
|
|
|
@47652
|
11 years |
vboxsync |
VMM: Removed all VBOX_WITH_OLD_[VTX|AMDV]_CODE bits.
|
|
|
|
@47328
|
11 years |
vboxsync |
CPUM,++: Fix DR6 and DR7 read-as-1 (RA1) and read-as-zero (RAZ) values …
|
|
|
|
@47242
|
11 years |
vboxsync |
Another CPL update. SS.RPL may not be the same as CPL in 64-bit mode …
|
|
|
|
@47225
|
11 years |
vboxsync |
Exploring conforming segments in BS2 test case.
|
|
|
|
@46286
|
12 years |
vboxsync |
VMM/HMVMXR0: Avoid saving/restoring EFER whenever possible on every …
|
|
|
|
@46165
|
12 years |
vboxsync |
Made dSYM-bundle loading work as well as line numbers in the stack …
|
|
|
|
@45965
|
12 years |
vboxsync |
VMM: Facility for getting the highest-priority pending interrupt from …
|
|
|
|
@45798
|
12 years |
vboxsync |
Fixed up and enabled Netware WP0+RO+US hack.
|
|
|
|
@45485
|
12 years |
vboxsync |
- *: Where possible, drop the #ifdef VBOX_WITH_RAW_RING1 when …
|
|
|
|
@45291
|
12 years |
vboxsync |
VMM: HM bits.
|
|
|
|
@45276
|
12 years |
vboxsync |
Ring-1 compression patches, courtesy of trivirt AG:
- main: diff to …
|
|
|
|
@45142
|
12 years |
vboxsync |
VMM: Don't LogRel on CPUMClearGuestCpuIdFeature().
|
|
|
|
@43974
|
12 years |
vboxsync |
VMM: Fix MSR range values for X2APIC, add in the X2APIC TPR MSR.
|
|
|
|
@43860
|
12 years |
vboxsync |
VMM/CPUMAllRegs: todo/question.
|
|
|
|
@43667
|
12 years |
vboxsync |
VMM: APIC refactor, cache APIC base MSR during init phase.
|
|
|
|
@43657
|
12 years |
vboxsync |
VMM: APIC refactor. Moved APIC base MSR to the VCPU (where it belongs) …
|
|
|
|
@43387
|
12 years |
vboxsync |
VMM: HM cleanup.
|
|
|
|
@43151
|
12 years |
vboxsync |
VMM: typos.
|
|
|
|
@42705
|
12 years |
vboxsync |
CPUM: Set FF when needed (VBOX_WITH_IEM only). Made CPUMRawSetEFlags …
|
|
|
|
@42647
|
12 years |
vboxsync |
CPUM: More intel MSRs that NT4 reads when booting on intel systems.
|
|
|
|
@42640
|
12 years |
vboxsync |
CPUM: Stubbed MSR_IA32_BIOS_SIGN_ID and MSR_IA32_BIOS_UPDT_TRIG.
|
|
|
|
@42452
|
12 years |
vboxsync |
CPUMAllRegs.cpp: Documented some return values on a few CPUMSetGuest* …
|
|
|
|
@42427
|
12 years |
vboxsync |
VMM: Fixed some selector arithmetic, introducing a new constand and …
|
|
|
|
@42420
|
12 years |
vboxsync |
Eliminating CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID and …
|
|
|
|
@42407
|
12 years |
vboxsync |
VMM: Futher work on dealing with hidden segment register, esp. when …
|
|
|
|
@42193
|
12 years |
vboxsync |
IEM: Integration work…
|
|
|
|
@42188
|
12 years |
vboxsync |
VMM: Changed a few ifndef IN_RING0 to ifndef VBOX_WITH_RAW_MODE_NOT_R0.
|
|
|
|
@42186
|
12 years |
vboxsync |
SELM,DIS,CPUM,EM: Hidden selector register cleanups.
|
|
|
|
@42166
|
12 years |
vboxsync |
CPUMGetGuestCPL: Use hidden SS register values in raw-mode too.
|
|
|
|
@42165
|
12 years |
vboxsync |
CPUMIsGuestIn64BitCode/CPUMIsGuestIn64BitCodeEx changes together with …
|
|
|
|
@42034
|
12 years |
vboxsync |
Doxygen.
|
|
|
|
@42033
|
12 years |
vboxsync |
VMM: RDTSCP support bits.
|
|
|
|
@42024
|
12 years |
vboxsync |
VMM: RDTSCP support on Intel. Segregated some common CPU features from …
|
|
|
|
@41976
|
12 years |
vboxsync |
VMM: Switcher and TRPM fixes wrt hypervisor traps and tstVMM.
|
|
|
|
@41965
|
12 years |
vboxsync |
VMM: ran scm. Mostly svn:keywords changes (adding Revision).
|
|
|
|
@41943
|
12 years |
vboxsync |
VMM: Avoid stale selector issues in RC so there will be no need to try …
|
|
|
|
@41940
|
12 years |
vboxsync |
CPUMRaw[SG]etEFlags: Drop pCtxCore.
|
|
|
|
@41939
|
12 years |
vboxsync |
CPUMGetGuestCPL: Drop the context core pointer and use the Guest state …
|
|
|
|
@41931
|
12 years |
vboxsync |
TRPM: Save state directly to the CPUMCPU context member instead of …
|
|
|
|
@41906
|
12 years |
vboxsync |
CPUM: Combined the visible and hidden selector register data into one …
|
|
|
|
@41905
|
12 years |
vboxsync |
CPUMCTX++: Rearranging the CPUMCTX structure in preparation of some …
|
|
|
|
@41836
|
13 years |
vboxsync |
Doxygen.
|
|
|
|
