|
|
@17106
|
16 years |
vboxsync |
VMM,REM: Removed the single page limitation on the TSS monitoring and …
|
|
|
@15635
|
16 years |
vboxsync |
More logging
|
|
|
@15634
|
16 years |
vboxsync |
Check parameter size correctly (disabled smsw).
|
|
|
@15633
|
16 years |
vboxsync |
Smsw emlution (inactive).
|
|
|
@15632
|
16 years |
vboxsync |
Extra instruction
|
|
|
@15426
|
16 years |
vboxsync |
EMAll: STOSWD - reject REP operations that crossess pages. The shadow …
|
|
|
@15421
|
16 years |
vboxsync |
EMAll: BTS, BTR and BTC looks fine to me for all 32-bit hosts since …
|
|
|
@15420
|
16 years |
vboxsync |
EMAll: ADD, ADC and SUB - the first is used a bit by windows.
|
|
|
@15419
|
16 years |
vboxsync |
EMAll: Corrected PGMVerifyAccess call in the STOSDW emulation to pass …
|
|
|
@15418
|
16 years |
vboxsync |
EMAll: AND, OR and XOR on darwin/R0 - the first two are for vista64.
|
|
|
@15413
|
16 years |
vboxsync |
#3202: CMPXCHG - 64-bit solaris optimziation.
|
|
|
@15412
|
16 years |
vboxsync |
EMAll: Whitelisted XCHG for >4 bytes operations (64-bit ubuntu 8.10 …
|
|
|
@15188
|
16 years |
vboxsync |
Some typos corrected.
|
|
|
@15184
|
16 years |
vboxsync |
typos
|
|
|
@15181
|
16 years |
vboxsync |
Restrict instruction emulation for 64 bits guests on 32 bits hosts.
|
|
|
@15161
|
16 years |
vboxsync |
Backed out accidental commit 40567
|
|
|
@15160
|
16 years |
vboxsync |
Compile fix
|
|
|
@14755
|
16 years |
vboxsync |
#1865: Converted 4 PGM*2HC* conversion functions to RTR3PTR.
|
|
|
@14562
|
16 years |
vboxsync |
Corrected wrong pointer calculation
|
|
|
@14411
|
16 years |
vboxsync |
RDTSCP support added. Enabled only for AMD-V guests.
|
|
|
@14257
|
16 years |
vboxsync |
cpuid clears the high dwords of the 64 bits registers.
|
|
|
@14251
|
16 years |
vboxsync |
Correction
|
|
|
@14249
|
16 years |
vboxsync |
More logging (msr)
|
|
|
@14248
|
16 years |
vboxsync |
Rdmsr must also clear the high dword of 64 bits registers.
|
|
|
@14247
|
16 years |
vboxsync |
Rdtsc: must clear the high dwords.
|
|
|
@14082
|
16 years |
vboxsync |
Must mask off the reference count from the HC physical address
|
|
|
@13832
|
16 years |
vboxsync |
IN_GC -> IN_RC.
|
|
|
@13825
|
16 years |
vboxsync |
VMM: %VX64 -> %RX64
|
|
|
@13823
|
16 years |
vboxsync |
VMM: %VGv -> %RGv
|
|
|
@13822
|
16 years |
vboxsync |
VMM: %VRv -> %RRv
|
|
|
@13820
|
16 years |
vboxsync |
VMM: %VG* inspection - an awfaul lot of these, hope I got it all right…
|
|
|
@13819
|
16 years |
vboxsync |
VMM: %VH* -> %RH*.
|
|
|
@13818
|
16 years |
vboxsync |
VMM: %Vrc -> %Rrc, %Vra -> %Rra.
|
|
|
@13816
|
16 years |
vboxsync |
VMM: VBOX_SUCCESS -> RT_SUCCESS, VBOX_FAILURE -> RT_FAILURE.
|
|
|
@13566
|
16 years |
vboxsync |
EMAll.cpp: doxygen.
|
|
|
@13565
|
16 years |
vboxsync |
#1865: REM (VMM bits) - moved EMFlushREMTBs to REMFlushTBs, deleted …
|
|
|
@13561
|
16 years |
vboxsync |
Emulate (lock) cmpxchg8b in ring 0 & 3. Added testcase for instruction …
|
|
|
@13532
|
16 years |
vboxsync |
CPUMQueryGuestCtxPtr doesn't need to return a status. It can never fail.
|
|
|
@13447
|
16 years |
vboxsync |
Logging change
|
|
|
@13351
|
16 years |
vboxsync |
Fully emulated lmsw.
|
|
|
@13267
|
16 years |
vboxsync |
lmsw: corrected exit path
|
|
|
@13266
|
16 years |
vboxsync |
lmsw emulation: 16 bits operand
|
|
|
@13265
|
16 years |
vboxsync |
Lmsw emulation.
|
|
|
@13235
|
16 years |
vboxsync |
PGM: Merged PGMGCInvalidatePage into PGMInvalidatePage nad fixed the …
|
|
|
@13193
|
16 years |
vboxsync |
uint64_t conversion fix
|
|
|
@13161
|
16 years |
vboxsync |
Emulate WBINVD
|
|
|
@13146
|
16 years |
vboxsync |
#1865: Renamed PGMPhysReadGCPhys -> PGMPhysSimpleReadGCPhys, …
|
|
|
@13144
|
16 years |
vboxsync |
#1865: Implmented the alternative R0 code for darwin (turned out to be …
|
|
|
@13020
|
16 years |
vboxsync |
Knut-compatibility fixes
|
|
|
@13013
|
16 years |
vboxsync |
infrastructure work for X2APIC support
|
|
|
@12989
|
16 years |
vboxsync |
VMM + VBox/cdefs.h: consolidated all the XYZ*DECLS of the VMM into …
|
|
|
@12801
|
16 years |
vboxsync |
Lidt/lgdt emulation fix for 16 bits operand size.
|
|
|
@12786
|
16 years |
vboxsync |
Real-mode support for VT-x. (currently disabled)
|
|
|
@12773
|
16 years |
vboxsync |
EMInterpretLMSW: LMSW cannot change AM or WP, so no need to check …
|
|
|
@12760
|
16 years |
vboxsync |
EMAll: Disabled the assertions reported in bug #2609, bug #1931 and on …
|
|
|
@12688
|
16 years |
vboxsync |
#1865: EM - one pointer and statistics. Added a couple of more samples …
|
|
|
@12657
|
16 years |
vboxsync |
#1865: CPUM. Also added missing aliasing for DR4&5 to the guest DRx …
|
|
|
@12307
|
16 years |
vboxsync |
Logging
|
|
|
@12305
|
16 years |
vboxsync |
Flush the recompiler's TB cache each time we detect writes to …
|
|
|
@12121
|
16 years |
vboxsync |
Committed hardware breakpoint support for VT-x and AMD-V. Untested and …
|
|
|
@11764
|
16 years |
vboxsync |
Got rid of PAT cpuid feature hack. Properly fixed now.
|
|
|
@11748
|
16 years |
vboxsync |
More logging
|
|
|
@11736
|
16 years |
vboxsync |
warning
|
|
|
@11714
|
16 years |
vboxsync |
Enable the PAT cpuid feature when switching to long mode.
|
|
|
@11692
|
16 years |
vboxsync |
Disabled microcode version passthru. Code is sufficient to make sure …
|
|
|
@11691
|
16 years |
vboxsync |
Allow the MSR_IA32_BIOS_SIGN_ID query only for Intel CPUs.
|
|
|
@11690
|
16 years |
vboxsync |
Pass the host's MSR_IA32_BIOS_SIGN_ID on to the guest. This msr …
|
|
|
@11688
|
16 years |
vboxsync |
Some more MSR logging
|
|
|
@11522
|
16 years |
vboxsync |
Activated (lock) cmpxchg emulation for VT-x and AMD-V. Watch for …
|
|
|
@11509
|
16 years |
vboxsync |
Added R0/HC emulation of (lock) cmpxchg. Not activated.
|
|
|
@11492
|
16 years |
vboxsync |
Fixed the non-rep stoswd case (rdi must be updated).
|
|
|
@11488
|
16 years |
vboxsync |
stoswd emulation fix (DF).
|
|
|
@11453
|
16 years |
vboxsync |
More compile issues
|
|
|
@11452
|
16 years |
vboxsync |
Minor correction
|
|
|
@11450
|
16 years |
vboxsync |
Access verfication for stoswd emulation.
|
|
|
@11424
|
16 years |
vboxsync |
Emulate stosw/d/q ourselves.
|
|
|
@10883
|
16 years |
vboxsync |
Wrmsr fix for MSR_IA32_SYSENTER_CS
|
|
|
@10661
|
16 years |
vboxsync |
Reduce the number of world switches caused by cr8 writes by checking …
|
|
|
@10473
|
16 years |
vboxsync |
MMIO instruction emulation for OR, BT and XOR added.
|
|
|
@10362
|
16 years |
vboxsync |
More verbose assertion
|
|
|
@10358
|
16 years |
vboxsync |
Implemented cr8 reading (PDMApicGetTPR).
|
|
|
@10274
|
16 years |
vboxsync |
More logging
|
|
|
@10270
|
16 years |
vboxsync |
Logging update
|
|
|
@10216
|
16 years |
vboxsync |
-> Unsupported
|
|
|
@10215
|
16 years |
vboxsync |
Missed MSR_IA32_MTRR_CAP
|
|
|
@10213
|
16 years |
vboxsync |
Log more MSRs
|
|
|
@10210
|
16 years |
vboxsync |
Support MSR_K6_EFER_FFXSR if X86_CPUID_AMD_FEATURE_EDX_FFXSR is set.
|
|
|
@10209
|
16 years |
vboxsync |
Logging update
|
|
|
@10107
|
16 years |
vboxsync |
Added CR8 write (alias for APIC TPR write).
|
|
|
@10088
|
16 years |
vboxsync |
Log MSR names
|
|
|
@10016
|
16 years |
vboxsync |
Corrected parameter types (const).
Use SELMToFlatEx instead of …
|
|
|
@10013
|
16 years |
vboxsync |
AMD64 shadow & real or protected mode without paging combo.
Flush TLB …
|
|
|
@9989
|
16 years |
vboxsync |
Enabled rdmsr/wrmsr emulation again. (VT-x & AMD-v regression fixed)
|
|
|
@9984
|
16 years |
vboxsync |
Big instruction emulation update for 64 bits mode. Watch for regressions!
|
|
|
@9817
|
17 years |
vboxsync |
fs & gs base cleanup
|
|
|
@9750
|
17 years |
vboxsync |
Backed out 32074 for now. (regressions)
|
|
|
@9747
|
17 years |
vboxsync |
Logging update
|
|
|
@9745
|
17 years |
vboxsync |
Enabled 64 bits mov instruction emulation.
|
|
|
@9726
|
17 years |
vboxsync |
Deal with long mode related changes to EFER, CR0 & CR4
|
|
|
@9725
|
17 years |
vboxsync |
Ignore MSR_K6_EFER_LMA
|
|
|