|
|
|
@11575
|
16 years |
vboxsync |
Sync back CR2 as it can be changed behind our back in the nested …
|
|
|
|
@11568
|
16 years |
vboxsync |
Cleanup
|
|
|
|
@11474
|
16 years |
vboxsync |
AMD-V: Corrected current asid handling. (multiple VMs could end up …
|
|
|
|
@10886
|
16 years |
vboxsync |
Fixes for syncing back sysenter MSRs.
|
|
|
|
@10683
|
16 years |
vboxsync |
Backed out 33399; must save the host context on entry due to long …
|
|
|
|
@10682
|
16 years |
vboxsync |
Saving of the host state is done correctly already for VT-x. (not …
|
|
|
|
@10667
|
16 years |
vboxsync |
Sync back TPR if necessary.
|
|
|
|
@10661
|
16 years |
vboxsync |
Reduce the number of world switches caused by cr8 writes by checking …
|
|
|
|
@10647
|
16 years |
vboxsync |
Manual saving of XMM registers.
Use new FPU/MMX/XMM state saving for …
|
|
|
|
@10609
|
16 years |
vboxsync |
Check for unexpected rescheduling.
|
|
|
|
@10607
|
16 years |
vboxsync |
Guest state loading and host state saving *must* be done after TPR …
|
|
|
|
@10572
|
16 years |
vboxsync |
Use NIL_RTR0MEMOBJ and ASMMemZeroPage.
|
|
|
|
@10566
|
16 years |
vboxsync |
Comment
|
|
|
|
@10542
|
16 years |
vboxsync |
Go directly to the halted state when encountering a hlt instruction …
|
|
|
|
@10537
|
16 years |
vboxsync |
Updated HWACCMDumpRegs
|
|
|
|
@10509
|
16 years |
vboxsync |
And again
|
|
|
|
@10508
|
16 years |
vboxsync |
Stupid compiler
|
|
|
|
@10506
|
16 years |
vboxsync |
Assertion
|
|
|
|
@10505
|
16 years |
vboxsync |
Easier to grep for
|
|
|
|
@10504
|
16 years |
vboxsync |
Don't violate my own rules…
|
|
|
|
@10503
|
16 years |
vboxsync |
More logging
|
|
|
|
@10502
|
16 years |
vboxsync |
Take precautions for being rescheduled to a different cpu due to long …
|
|
|
|
@10500
|
16 years |
vboxsync |
Clarified comment
|
|
|
|
@10499
|
16 years |
vboxsync |
Another paranoid assertion.
|
|
|
|
@10498
|
16 years |
vboxsync |
Added warning
|
|
|
|
@10497
|
16 years |
vboxsync |
Another edge case where we need to flush the TLB.
|
|
|
|
@10491
|
16 years |
vboxsync |
Logging
|
|
|
|
@10489
|
16 years |
vboxsync |
AMD-V: Always flush the TLB the first time a cpu is used.
|
|
|
|
@10480
|
16 years |
vboxsync |
Must monitor CR8 writes. (for now)
|
|
|
|
@10458
|
16 years |
vboxsync |
TPR & interrupt dispatch updates.
|
|
|
|
@10354
|
16 years |
vboxsync |
Extra assertion
|
|
|
|
@10353
|
16 years |
vboxsync |
TPR caching for VT-x. Removed the CR8 register from CPUMCTX.
|
|
|
|
@10331
|
16 years |
vboxsync |
Removed the assertion completely.
|
|
|
|
@10330
|
16 years |
vboxsync |
Wrong assertion. Due to ring 3 far jumps the assertion condition can …
|
|
|
|
@10299
|
16 years |
vboxsync |
Force a TLB flush on a mode switch too.
|
|
|
|
@10297
|
16 years |
vboxsync |
More assertions.
|
|
|
|
@10269
|
16 years |
vboxsync |
Logging updates
|
|
|
|
@10206
|
16 years |
vboxsync |
Fixed regression introduced by TPR caching. (never execute code that …
|
|
|
|
@10110
|
16 years |
vboxsync |
More TPR updates
|
|
|
|
@10108
|
16 years |
vboxsync |
More CR8 updates
|
|
|
|
@10097
|
16 years |
vboxsync |
Derive CPL from cs, not ss.
|
|
|
|
@10095
|
16 years |
vboxsync |
logging change
|
|
|
|
@10066
|
16 years |
vboxsync |
Paranoid assertion
|
|
|
|
@10018
|
16 years |
vboxsync |
Wrong assertion + logging updates
|
|
|
|
@10015
|
16 years |
vboxsync |
Don't forget to sync back MSR_K8_KERNEL_GS_BASE.
|
|
|
|
@10014
|
16 years |
vboxsync |
Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow …
|
|
|
|
@10011
|
16 years |
vboxsync |
Compile fix
|
|
|
|
@10010
|
16 years |
vboxsync |
Updates for 64 bits mode (invlpg - amd-v)
|
|
|
|
@9988
|
16 years |
vboxsync |
Unconditionally update the sysenter msrs.
|
|
|
|
@9897
|
16 years |
vboxsync |
Updates for executing 64 bits guest code with AMD-V.
|
|
|
|
@9720
|
17 years |
vboxsync |
Emulate rdmsr & wrmsr.
Note that Intel mentions a (slightly different) …
|
|
|
|
@9718
|
17 years |
vboxsync |
Single instruction emulation for rd/wrmsr
|
|
|
|
@9708
|
17 years |
vboxsync |
Use RIP everywhere
|
|
|
|
@9660
|
17 years |
vboxsync |
Correction
|
|
|
|
@9659
|
17 years |
vboxsync |
SELMGetCpuModeFromSelector is a better name.
|
|
|
|
@9658
|
17 years |
vboxsync |
Renamed SELMIsSelector32Bit to SELMGetSelectorType.
|
|
|
|
@9457
|
17 years |
vboxsync |
Reapplied fixed 31707.
|
|
|
|
@9453
|
17 years |
vboxsync |
Backed out 31707
|
|
|
|
@9452
|
17 years |
vboxsync |
Preparing for 64 bits vmlaunch/vmresume.
|
|
|
|
@9411
|
17 years |
vboxsync |
Use a union for esp & rsp, so they are in-sync.
|
|
|
|
@9407
|
17 years |
vboxsync |
HWACCM updates.
|
|
|
|
@9385
|
17 years |
vboxsync |
Backed out some of the changes. Broke VT-x
|
|
|
|
@9383
|
17 years |
vboxsync |
VT-x/AMD-V updates for 64 bits guests
|
|
|
|
@9212
|
17 years |
vboxsync |
Major changes for sizeof(RTGCPTR) == uint64_t.
Introduced RCPTRTYPE …
|
|
|
|
@9188
|
17 years |
vboxsync |
Same IF fix for halt instructions in VT-x.
|
|
|
|
@9184
|
17 years |
vboxsync |
If CF=0 HLT should never resume.
|
|
|
|
@9125
|
17 years |
vboxsync |
AMD-V: setup PAT guest register for nested paging
|
|
|
|
@9122
|
17 years |
vboxsync |
Logging update
|
|
|
|
@9120
|
17 years |
vboxsync |
Updates
|
|
|
|
@9116
|
17 years |
vboxsync |
Added stat counter for physical page invalidation.
|
|
|
|
@9115
|
17 years |
vboxsync |
HWACCM: Invalidate pages changed by PGMHandlerPhysicalPageTempOff. …
|
|
|
|
@9110
|
17 years |
vboxsync |
Minor update
|
|
|
|
@9092
|
17 years |
vboxsync |
We need a real shadow paging backend for PGMHandlerPhysicalPageTempOff …
|
|
|
|
@9082
|
17 years |
vboxsync |
More statistics
|
|
|
|
@9075
|
17 years |
vboxsync |
Fixed wrong call to TRPMResetTrap
|
|
|
|
@9074
|
17 years |
vboxsync |
Log normal page faults in nested paging mode too (DEBUG only).
|
|
|
|
@9073
|
17 years |
vboxsync |
Updated logging
|
|
|
|
@9064
|
17 years |
vboxsync |
Properly deal with CR3 changes in nested paging mode.
|
|
|
|
@9038
|
17 years |
vboxsync |
Sync back the debug registers too (fixed gdb/dbx weirdness on solaris).
|
|
|
|
@9033
|
17 years |
vboxsync |
Statistics for SVM_EXIT_NPF
|
|
|
|
@9029
|
17 years |
vboxsync |
Removed assertion
|
|
|
|
@9026
|
17 years |
vboxsync |
More updates for nested paging. (setting up the paging mode)
|
|
|
|
@9021
|
17 years |
vboxsync |
Nested paging updates. Extra paging mode added to prevent illegal …
|
|
|
|
@9008
|
17 years |
vboxsync |
Changes for proper flushing of the TLB for physical registration changes.
|
|
|
|
@8965
|
17 years |
vboxsync |
Nested paging updates
|
|
|
|
@8952
|
17 years |
vboxsync |
Nested paging updates
|
|
|
|
@8948
|
17 years |
vboxsync |
Nested paging updates
|
|
|
|
@8945
|
17 years |
vboxsync |
Updated comment
|
|
|
|
@8944
|
17 years |
vboxsync |
Fixed problem with erratum 170 cpus.
|
|
|
|
@8943
|
17 years |
vboxsync |
AMD-V: flush TLB when the flush count for the cpu has changed
AMD-V: …
|
|
|
|
@8941
|
17 years |
vboxsync |
Intercept task switches as well. (they can change CR3)
|
|
|
|
@8914
|
17 years |
vboxsync |
Moved cpu id check around for tlb flushing.
|
|
|
|
@8901
|
17 years |
vboxsync |
Always enable caching
|
|
|
|
@8900
|
17 years |
vboxsync |
Some updates
|
|
|
|
@8881
|
17 years |
vboxsync |
Wrong assertion
|
|
|
|
@8880
|
17 years |
vboxsync |
More logging
|
|
|
|
@8878
|
17 years |
vboxsync |
Don't automatically flush the TLB when we remain on the same cpu (on …
|
|
|
|
@8876
|
17 years |
vboxsync |
ASID based TLB flushing
|
|
|
|
@8871
|
17 years |
vboxsync |
Updated assertion
|
|
|
|
@8870
|
17 years |
vboxsync |
Intercept mwait as well (AMD-V)
|
|
|
|
